CN103378148A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103378148A CN103378148A CN2012101099640A CN201210109964A CN103378148A CN 103378148 A CN103378148 A CN 103378148A CN 2012101099640 A CN2012101099640 A CN 2012101099640A CN 201210109964 A CN201210109964 A CN 201210109964A CN 103378148 A CN103378148 A CN 103378148A
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof. A groove is first formed in a silicon substrate. A hiding layer is formed on a sidewall of the groove. The depth of the groove is increased to expose a portion of the silicon substrate, and the exposed portion of the silicon substrate forms a silicon oxide layer during thermal oxidation. The silicon oxide layer is removed afterwards. A recess is formed in the silicon substrate, and silicon material left above the recess forms a bridging structure across the recess. The semiconductor device is capable of forming a semiconductor nanowire transistor structure on the bridging structure made of the silicon material to replace a silicon structure on an insulator in the prior art, and can well control the dimensions of the bridging structure by controlling the process conditions during the oxidation, thereby providing precise dimensional control for the semiconductor nanowire transistor structure formed subsequently.
Description
Technical field
The present invention relates to semiconductor device and manufacture method, relate in particular to a kind of semiconductor device and manufacture method thereof of semiconductor nanowire transistor structure.
Background technology
Recent decades, MOS field-effect transistor (metal-oxide-semiconductor field effect transistor, MOSFET) continuous trend development to minification is to gather way, to improve assembly integrated level and the cost that reduces integrated circuit.Along with the integrated level of semiconductor device is more and more higher, when grid width constantly shortens, mean that source electrode and drain electrode increase gradually for the influence degree that the current potential of raceway groove (Channel) causes, therefore, when grid width foreshortened to a certain degree, " short-channel effect " caused the state that opens or closes of the uncontrollable in fact raceway groove of voltage that applies on the grid.Comprise that with the mode that solves short-channel effect the doping content, the minimizing thickness of grid oxide layer that increase the Semiconductor substrate body engage with using shallow source/drain electrode traditionally.Yet when grid width foreshortens to 50nm when following, aforesaid way is difficult to suppress short-channel effect gradually, thereby the planar MOSFET transistor has reached the lower limit of device size.Gradually the substitute is the multiple-gate transistors tubular construction, the multiple-gate transistors tubular construction can improve capacitive coupling effect between grid and raceway groove, increase grid to the control ability of channel potential, suppress short-channel effect, thereby make transistor size continue development to constantly dwindling trend.
Wherein, common FinFET (FinFET), the grid of comprising of multigrid transistor wraps up transistor (Gate-All-Around transistor entirely, GAA transistor) and etc. structure, along with size is constantly dwindled, device architecture enters nano-grade size, the semiconductor nanowire transistor structure is arisen at the historic moment, and efficiently solves short-channel effect (Short Channel Effect, SCE).
In the prior art, a kind of method of semiconductor nanowire transistor structure is to be formed on the silicon-on-insulator substrate (SOI substrate), silicon on insulated substrate comprises and buries oxide structure and be positioned at the silicon layer that buries on the oxide structure, behind the etching silicon layer, removal is positioned at the oxide structure that buries under the silicon layer, thereby makes silicon layer form the bridging structure, and forms pan below the bridging structure, in subsequent technique, on described bridging structure and form the semiconductor nanowire transistor structure on every side.
Because the cost of SOI substrate is relatively high, how pan and the bridging structure that is located at above the pan become the industry problem demanding prompt solution in common silicon layer structure.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor nanowire transistor structure, controlled semiconductor device and manufacture method thereof of size of being used to form.
For solving the problems of the technologies described above, the invention provides a kind of semiconductor device, be used to form the semiconductor nanowire transistor structure, described semiconductor device comprises silicon substrate, is formed with pan on the described silicon substrate and is located at the bridging structure that a plurality of flat shape on the described pan is arranged.
Further, the interface of described bridging structure is circular.
Further, the diameter of the circular cross-section of described bridging structure is 5nm～50nm.
Further, adjacent bridging structure distance is 5nm～50nm.
The present invention also provides a kind of manufacture method of semiconductor device, and described semiconductor device is used for forming the semiconductor nanowire transistor structure, and described manufacture method may further comprise the steps:
Silicon substrate is provided, covers hard mask layer at described silicon substrate;
The for the first time described hard mask layer of dry etching part and silicon substrate are to form a plurality of grooves;
Sidewall at described groove forms barrier bed;
The described silicon substrate of dry etching for the second time increases the degree of depth of described groove;
Carry out thermal oxidation technology, form silicon oxide layer in the silicon substrate that the layer that is not blocked in the described groove blocks;
Remove described barrier bed and silicon oxide layer, to form pan and a plurality of bridging structures that are positioned on the described pan at described silicon substrate.
Further, the material of described hard mask layer is silicon nitride or silicon oxynitride, and the thickness of described hard mask layer is 10nm～500nm.
Further, behind first time dry etching, the degree of depth of described groove in described silicon substrate is 5nm～60nm.
Further, the formation step of described barrier bed comprises:
On described hard mask layer, the bottom surface of described groove and sidewall deposition block film;
Etching remove be positioned on the described hard mask layer and the bottom surface of described groove block film, form barrier bed with the sidewall at described groove.
Further, the thickness 2nm～20nm of described barrier bed.
Further, behind second time dry etching, the degree of depth of described groove in described silicon substrate is 10nm～500nm.
Further, the temperature of described thermal oxidation technology is that 600 ℃～1200 ℃, time are 5 seconds～10 hours.
Further, the gas that passes into of described thermal oxidation technology is oxygen, and intake is 0.1SLM～100SLM.1. further, described thermal oxidation technology pass into the mist that gas is oxygen and hydrogen, the intake of oxygen and hydrogen is respectively 0.1SLM～50SLM.
Further, the cross section of described bridging structure is circular.
Further, the diameter of the circular cross-section of described bridging structure is 5nm～50nm.
Further, distance is 5nm～50nm between the adjacent bridging structure.
In sum, semiconductor device of the present invention and manufacture method thereof, by at first in silicon substrate, forming groove, and after trenched side-wall forms barrier bed, continue to increase the silicon substrate that gash depth exposes with bottom surface and partial sidewall at described groove, then carry out thermal oxidation technology, the partial silicon substrate that bottom surface and partial sidewall at described groove are exposed forms silicon oxide layer, and the partial silicon substrate that the layer that is blocked blocks is not oxidized, thereby after silicon oxide layer is removed, in silicon substrate, form pan, be positioned at the bridging structure that the not removed silicon material in pan top then forms the pan top that is located at, described semiconductor device can replace the prior art silicon on insulated substrate, on the bridging structure of silicon substrate, can form the semiconductor nanowire transistor structure, and can preferably control the size of bridging structure by the process conditions of control in the oxidizing process, for the semiconductor nanowire transistor structure of follow-up formation provides accurate size Control.
Description of drawings
Fig. 1 is the vertical view of semiconductor device described in one embodiment of the invention.
Fig. 2 is the profile along AA ' direction among Fig. 1.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.
Fig. 4～Figure 10 is the structural representation in the manufacture process of semiconductor device in one embodiment of the invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 1 is the vertical view of semiconductor device described in one embodiment of the invention, Fig. 2 is the profile along AA ' direction among Fig. 1, in conjunction with Fig. 1 and Fig. 2, the invention provides a kind of semiconductor device, be used for forming the semiconductor nanowire transistor structure at this semiconductor device, described semiconductor device comprises silicon substrate 100, is formed with pan 108 on this silicon substrate 100 and is located at the bridging structure 110 that a plurality of flat shape on the described pan 108 is arranged.
In subsequent technique, can the bridging structure 110 on described pan 108 form grid structure, grid structure is around the middle part of bridging structure 110, in the bridging structure of grid structure both sides, form source electrode and drain electrode, further carry out other known processing steps, thereby finally form the semiconductor nanowire transistor structure, do not repeat them here.
Wherein, as shown in Figure 2, the cross section of described bridging structure 110 is circular, and described bridging structure 110 integral body are cylindrical.The diameter of the circular cross-section of described bridging structure 110 is 5nm～50nm, and the distance between the adjacent bridging structure 110 is 5nm～50nm.Distance between the diameter of the circular cross-section of described bridging structure 110 and the bridging structure can specifically be determined according to the dimensional requirement of semiconductor nanowire transistor structure.
In conjunction with above-mentioned semiconductor device, the present invention also provides a kind of manufacture method of semiconductor device, may further comprise the steps:
Step S01: silicon substrate is provided, covers hard mask layer at described silicon substrate;
Step S02: carry out for the first time dry etch process, etched portions hard mask layer and silicon substrate are to form a plurality of grooves;
Step S03: the sidewall at described groove forms barrier bed;
Step S04: carry out for the second time dry etch process, the described silicon substrate of etching increases the degree of depth of described groove;
Step S05: carry out thermal oxidation technology, form silicon oxide layer in the silicon substrate that the layer that is not blocked in the described groove blocks;
Step S06: remove described barrier bed and silicon oxide layer, to form pan and a plurality of bridging structures that are positioned on the described pan at described silicon substrate.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention, Fig. 4～Figure 10 is the structural representation in the manufacture process of semiconductor device in one embodiment of the invention, describes the manufacture method of semiconductor device of the present invention in detail below in conjunction with Fig. 1～Figure 10.
As shown in Figure 4, in step S01, provide silicon substrate 100, cover hard mask layer 102 at described silicon substrate 100; The material of described hard mask layer 102 can be silicon nitride or silicon oxynitride; the thickness of described hard mask layer 102 can be 10nm～500nm; wherein that better is 100nm, adopts above-mentioned thickness in follow-up multiple etching process, to protect silicon substrate 100 not need the zone of etching.
As shown in Figure 5, in step S02, carry out the dry etch process first time, the described hard mask layer 102 of etched portions and silicon substrate 100 are to form a plurality of groove 200; Detailed process is: at first cover photoresist (not indicating among the figure) at described hard mask layer 102, utilize exposure, the described photoresist of developing process patterning, expose the hard mask layer 102 that wish forms groove, then take described patterning photoresist as mask, the described hard mask layer 102 of etching is until expose described silicon substrate 100, remove again described patterning photoresist, take described hard mask layer 102 as mask, the described silicon substrate 100 of dry etching, thus form described groove 200.Behind first time dry etching, the depth H 1 of described groove 200 in described silicon substrate 100 is 5nm～60nm, this depth bounds can effectively be controlled the size of the bridging structure of follow-up formation, thereby improves the mechanical strength of bridging structure when satisfying the technological requirement of size of bridging structure.
As shown in Figure 6 and Figure 7, in step S03, at the sidewall formation barrier bed 104 of described groove 200; The formation step of described barrier bed 104 comprises: on described hard mask layer 102, the bottom surface of described groove 100 and sidewall deposition block film 104a; Then, etching remove be positioned on the described hard mask layer 102 and the bottom surface of described groove 100 block film 104a, form as shown in Figure 6 barrier bed 104 with the sidewall at described groove 200.Wherein, the thickness of described barrier bed 104 is 2nm～20nm, can the sidewall of groove 200 on forming good interface, protect well its silicon substrate that blocks 100 zones.
As shown in Figure 8, in step S04, carry out the dry etch process second time, the described silicon substrate of etching increases the degree of depth of described groove 200; Behind the described second time dry etching, the depth bounds H2 of described groove 200 in described silicon substrate 100 is 10nm～500nm.
As shown in Figure 9, in step S05, carry out thermal oxidation technology, form silicon oxide layer 106 in layer 104 silicon substrate that blocks 100 that are not blocked in the described groove 200; Silicon substrate 100 in groove 200 bottom surfaces and partial sidewall exposure forms silicon oxide layer 106 in the subsequent thermal oxidizing process, and layer 104 partial silicon substrate of blocking 100 unreacteds that are blocked, the silicon substrate 100 in this unreacted zone will form the bridging structure follow-up.Wherein, carry out in the thermal oxidation technology process, the temperature of described thermal oxidation technology is 600 ℃～1200 ℃, time is 5 seconds～10 hours, it is oxygen that thermal oxidation technology passes into gas, intake is 0.1SLM～100SLM, perhaps pass into the mist of oxygen and hydrogen, the intake of oxygen and hydrogen is respectively 0.1SLM～50SLM (Standard Liter per Minute) in the mist, by the control intake, ambient temperature and time can be controlled the thickness that silicon oxide layer 106 forms, and then can control and be arranged in the silicon substrate 100 that oxidation reaction does not occur described barrier bed 104 sidewalls.
In conjunction with Fig. 9 and shown in Figure 10, in step S06, remove barrier bed 104 and silicon oxide layer 102, to form pan 108 and a plurality of bridging structures 110 that are positioned on the pan 108 at described silicon substrate 100, wherein the degree of depth of the final pan H3 that forms is 10nm～600nm, and the cross section of described bridging structure 110 is circular.
In subsequent technique, can the described bridging structure 110 on described pan 108 form grid structure, grid structure is around the middle part of bridging structure 110, in the bridging structure of grid structure both sides, form source electrode and drain electrode, further carry out other processing steps, thereby finally form the semiconductor nanowire transistor structure.The process that forms grid structure, source electrode, drain electrode is the technological means that those of ordinary skills were familiar with, so repeat no more.
In sum, in sum, semiconductor device of the present invention and manufacture method thereof, by at first in silicon substrate, forming groove, and after trenched side-wall forms barrier bed, continue to increase the silicon substrate that gash depth exposes with bottom surface and partial sidewall at described groove, then carry out thermal oxidation technology, the partial silicon substrate that bottom surface and partial sidewall at described groove are exposed forms silicon oxide layer, and the partial silicon substrate that the layer that is blocked blocks is not oxidized, thereby after silicon oxide layer is removed, in silicon substrate, form pan, be positioned at the bridging structure that the not removed silicon material in pan top then forms the pan top that is located at, described semiconductor device can replace the prior art silicon on insulated substrate, on the bridging structure of silicon substrate, can form the semiconductor nanowire transistor structure, and can preferably control the size of bridging structure by the process conditions of control in the oxidizing process, for the semiconductor nanowire transistor structure of follow-up formation provides accurate size Control.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (16)
1. a semiconductor device is used to form the semiconductor nanowire transistor structure, it is characterized in that, described semiconductor device comprises silicon substrate, is formed with pan on the described silicon substrate and is located at the bridging structure that a plurality of flat shape on the described pan is arranged.
2. semiconductor device as claimed in claim 1 is characterized in that, the cross section of described bridging structure is circular.
3. semiconductor device as claimed in claim 2 is characterized in that, the diameter in the cross section of described bridging structure is 5nm～50nm.
4. such as the described semiconductor device of any one in the claims 1 to 3, it is characterized in that the distance between the adjacent bridging structure is 5nm～50nm.
5. the manufacture method of a semiconductor device, described semiconductor device are used for forming the semiconductor nanowire transistor structure, comprising:
Silicon substrate is provided, covers hard mask layer at described silicon substrate;
Carry out for the first time dry etch process, etched portions hard mask layer and silicon substrate are to form a plurality of grooves;
Sidewall at described groove forms barrier bed;
Carry out for the second time dry etch process, the described silicon substrate of etching increases the degree of depth of described groove;
Carry out thermal oxidation technology, form silicon oxide layer in the silicon substrate that the layer that is not blocked in the described groove blocks;
Remove described barrier bed and silicon oxide layer, to form pan and a plurality of bridging structures that are positioned on the described pan at described silicon substrate.
6. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, the material of described hard mask layer is silicon nitride or silicon oxynitride, and the thickness of described hard mask layer is 10nm～500nm.
7. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, after the execution dry etch process first time, the degree of depth of described groove in described silicon substrate is 5nm～60nm.
8. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, the formation step of described barrier bed comprises:
On described hard mask layer, the bottom surface of described groove and sidewall deposition block film;
Etching remove be positioned on the described hard mask layer and the bottom surface of described groove block film, form barrier bed with the sidewall at described groove.
9. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, the thickness 2nm～20nm of described barrier bed.
10. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, after the execution dry etch process second time, the degree of depth of described groove in described silicon substrate is 10nm～500nm.
11. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, the temperature of described thermal oxidation technology is that 600 ℃～1200 ℃, time are 5 seconds～10 hours.
12. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, the gas that passes into of described thermal oxidation technology is oxygen, and intake is 0.1SLM～100SLM.
13. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, described thermal oxidation technology pass into the mist that gas is oxygen and hydrogen, the intake of oxygen and hydrogen is respectively 0.1SLM～50SLM.
14. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, the cross section of described bridging structure is circular.
15. the manufacture method of semiconductor device as claimed in claim 14 is characterized in that, the diameter in the cross section of described bridging structure is 5nm～50nm.
16. the manufacture method such as the described semiconductor device of any one in the claim 5 to 15 is characterized in that, the distance between the adjacent bridging structure is 5nm～50nm.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295677A (en) * | 2007-04-27 | 2008-10-29 | 北京大学 | Production method of bulk silicon nano line transistor device |
| US20100047973A1 (en) * | 2006-12-21 | 2010-02-25 | Commissariat A L'energie Atomique | Method for forming microwires and/or nanowires |
| US20100193770A1 (en) * | 2009-02-04 | 2010-08-05 | International Business Machines Corporation | Maskless Process for Suspending and Thinning Nanowires |
| CN102110648A (en) * | 2009-12-24 | 2011-06-29 | 中国科学院微电子研究所 | Method for preparing bulk silicon gate-all-around metal oxide semiconductor field effect transistors |
| CN102315170A (en) * | 2011-05-26 | 2012-01-11 | 北京大学 | Method for manufacturing silicon nanowire FET (field effect transistor) based on wet etching |
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- 2012-04-13 CN CN201210109964.0A patent/CN103378148B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100047973A1 (en) * | 2006-12-21 | 2010-02-25 | Commissariat A L'energie Atomique | Method for forming microwires and/or nanowires |
| CN101295677A (en) * | 2007-04-27 | 2008-10-29 | 北京大学 | Production method of bulk silicon nano line transistor device |
| US20100193770A1 (en) * | 2009-02-04 | 2010-08-05 | International Business Machines Corporation | Maskless Process for Suspending and Thinning Nanowires |
| CN102110648A (en) * | 2009-12-24 | 2011-06-29 | 中国科学院微电子研究所 | Method for preparing bulk silicon gate-all-around metal oxide semiconductor field effect transistors |
| CN102315170A (en) * | 2011-05-26 | 2012-01-11 | 北京大学 | Method for manufacturing silicon nanowire FET (field effect transistor) based on wet etching |
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