CN102820334A - Fin field effect transistor structure and method for forming fin field effect transistor structure - Google Patents
Fin field effect transistor structure and method for forming fin field effect transistor structure Download PDFInfo
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- CN102820334A CN102820334A CN201110151663XA CN201110151663A CN102820334A CN 102820334 A CN102820334 A CN 102820334A CN 201110151663X A CN201110151663X A CN 201110151663XA CN 201110151663 A CN201110151663 A CN 201110151663A CN 102820334 A CN102820334 A CN 102820334A
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Abstract
The invention discloses a fin field effect transistor structure and a method for forming the fin field effect transistor structure. The fin field effect transistor structure comprises a base material, a fin structure, an insulating layer and a grid electrode structure. The fin structure is positioned on the base material, is directly connected with the base material and comprises fin conductor layers and bottlenecks. The insulating layer covers the base material and is provided with a protruded side surface and a bottom surface, the protruded side surface is formed by partially surrounding the bottlenecks of the fin structure, and the bottom surface is in direct contact with the base material, so that the protruded side surface extends to the lower side of the fin structure. The grid electrode structure partially surrounds the fin structure.
Description
Technical field
The present invention relates to a kind of fin formula field effect transistor structure, and the method that forms multiple fin formula field effect transistor structure.The present invention particularly relates to a kind of method of using the difference that forms oxide possibly come construction fin formula field-effect transistor, is used for reducing fin formula field-effect transistor leakage problem, or increases the solution of heat radiation.
Background technology
Semiconductor industry continues the important goal of research and development, is to increase the usefulness of semiconductor element, and the power consumption that reduces semiconductor element.Increasing on this approach of semiconductor element usefulness, prior art has been developed to utilize and has been helped the different crystal plane orientation that hole or electronics flow and come lift elements usefulness.
For instance, be established in n type passage (n-channel) metal-oxide semiconductor (MOS) on (100) silicon wafer face (metal-oxide-semiconductor, MOS) transistor unit can obtain higher carrier mobility; P type passage (p-channel) the MOS transistor element that is established on (110) silicon wafer face then obtains higher carrier mobility.Therefore prior art is when construction plane formula (planar) complementary (complementary) metal-oxide semiconductor transistor component (CMOS device); Once utilized modes such as substrate bonded technology; The silicon layer that will have different crystal plane orientation is made into board structure; And n type passage MOS transistor element grown up in (100) crystal face, and p type passage MOS transistor element is grown up in (110) crystal face, to promote the electrical performance of cmos element.
Yet,, use the real difficult micro that continues of MOS transistor manufacture craft of conventional planar formula along with the element development gets into 65 nanometer technologies after the generation.Therefore, prior art proposes with solid multi-grid transistor unit such as fin formula field-effect transistor (Fin Field effect transistor, FinFET) solution route of element replacement flat crystal tube elements.Yet, owing to the bottom of fin formula field-effect transistor directly links to each other with base material, so the problem of serious leakage current is arranged when operation.On the other hand, fin formula field-effect transistor is based upon insulating barrier silicon-covered substrate (SOI substrate), then can increases production cost because of the high price of insulating barrier silicon-covered substrate (SOI substrate) if want to solve the problem of leakage current.
Therefore, still need at present to solve above-mentioned awkward multi-gated transistor component structure and manufacture method.
Summary of the invention
So the present invention proposes a kind of method that forms various fin formula field effect transistor structure, to obtain the multiple fin formula field effect transistor structure that can satisfy different demands.The present invention uses the different possibilities that form oxide, just can come the fin formula field-effect transistor of construction different structure.On the one hand, the inventive method can need not to use expensive insulating barrier silicon-covered substrate, just can form the fin formula field effect transistor structure that is positioned on the insulating barrier, and have end face and bottom surface at least one uneven architectural feature wherein of insulating barrier.On the other hand, the inventive method can also form and have the fin formula structure that directly links to each other with base material with neck part.These neck parts both can reduce the problem of fin formula field-effect transistor leakage current, did not disturb the heat dissipation problem of fin formula field-effect transistor simultaneously again.
The present invention at first proposes a kind of fin formula field effect transistor structure, and it comprises base material, fin formula structure, insulating barrier and grid structure.Insulating barrier covering substrates, and the bottom surface that has end face and directly contact, wherein at least one unevenness of end face and bottom surface with base material.Fin formula structure then is positioned on the insulating barrier, and comprises fin formula conductor layer and one group of source/drain.Grid structure then part surrounds fin formula structure, and comprises a grid conducting layer and a gate dielectric that surrounds fin formula structure.
In an embodiment of the present invention, insulating barrier comprises a plurality of U-shapeds bottom surface, makes fin formula structure between adjacent U-shaped bottom surface.In another embodiment of the present invention, fin formula field effect transistor structure more comprises the cap layer that covers fin formula conductor layer.In further embodiment of this invention, fin formula structure has the drift angle of round passivation.In yet another embodiment of the invention, insulating barrier does not contain stress in fact.
Secondly the present invention proposes a kind of fin formula field effect transistor structure, and it comprises base material, fin formula structure, insulating barrier and grid structure.Fin formula structure is positioned on the base material and with base material and directly links to each other.Fin formula structure comprises fin formula conductor layer and neck part.Insulating barrier is covering substrates then, and has the raised side that part forms around the neck part of fin formula structure, and the bottom surface that directly contacts with base material.Raised side extends to fin formula structure below.Grid structure partly surrounds fin formula structure, comprises a grid conducting layer and a gate dielectric that surrounds fin formula structure again.
In an embodiment of the present invention, fin formula field effect transistor structure more comprises the shallow trench isolation that is positioned at insulating barrier below and leaves.These shallow trench isolations are from having the top that directly contacts with insulating barrier, and the top of also leaving greater than shallow trench isolation, the bottom surface of insulating barrier.
The present invention proposes a kind of method that forms fin formula field effect transistor structure again.At first, a base material is provided and is positioned at the fin formula structure on the base material.Fin formula structure comprises mask layer, resilient coating, cap layer, fin formula conductor layer and a clearance wall around mask layer, resilient coating, cap layer, fin formula conductor layer.Secondly; The base material etching step that comprises lateral etches step and vertical etching step; And second depression that in base material, forms first depression and link to each other with first depression, wherein at least one of first depression and second depression has a raised side that extends to below the fin formula structure.Afterwards, form the oxide layer of filling up first depression and second depression.Continue, form part and surround the grid structure of fin formula structure.
In an embodiment of the present invention, the lateral etches step can or be carried out before vertical etching step afterwards.In another embodiment of the present invention, use the furnace oxidation method to form required oxide layer with the oxidation base material.In further embodiment of this invention, the lateral etches step can form required neck part in fin formula structure.In yet another embodiment of the invention, the width of neck part is the 40%-60% of fin formula structure width.
Description of drawings
The method sketch map of Fig. 1 to Fig. 8 B various fin formula field effect transistor structure for the present invention forms;
Fig. 9 A is a kind of fin formula of the present invention field effect transistor structure sketch map;
Fig. 9 B is the another kind of fin formula of the present invention field effect transistor structure sketch map.
The main element symbol description
100 fin formula field effect transistor structures
101 base materials
102 second depressions
103 first depressions
104 neck parts
105 raised sides
109 layings
110 fin formula structures
111 mask layers
112 resilient coatings
113 cap layers
114 clearance walls
115 side-wall material layers
116 drift angles
117 fin formula conductor layers
118 source/drains
119 resilient coatings
120 oxide layers
121 end faces
122 bottom surfaces
130 grid structures
131 gate dielectrics
132 gate material layers
Embodiment
The present invention provides a kind of method that forms various fin formula field effect transistor structure, to obtain the multiple fin formula field effect transistor structure that can satisfy different demands.In the methods of the invention, form the difference of oxide mode, just can come the fin formula field-effect transistor of construction different structure.On the one hand; The inventive method can need not to use expensive insulating barrier silicon-covered substrate (SOI substrate); Just can obtain being positioned at the fin formula field effect transistor structure on the insulating barrier, and have end face and bottom surface at least one uneven architectural feature wherein of insulating barrier.On the other hand, the inventive method can also form, and the fin formula structure that directly links to each other with base material with neck part so both can reduce the problem of fin formula field-effect transistor leakage current, does not influence the heat dissipation problem of fin formula field-effect transistor simultaneously again.
Fig. 1 to Fig. 8 B illustrates the method that the present invention forms various fin formula field effect transistor structure, to obtain the multiple fin formula field effect transistor structure that can satisfy different demands.The present invention forms the method for fin formula field effect transistor structure, and is at first as shown in Figure 3, base material 101 is provided and is positioned at least one fin formula structure 110 on the base material 101.Fin formula structure 110 comprises mask layer 111, resilient coating 112, cap layer 113, fin formula conductor layer 117 and clearance wall 114.
The method of formation fin formula structure 110 is institute's illustration as follows.At first, as shown in Figure 1, mask layer 111, resilient coating 112 and cap layer 113 are provided on base material 101.Cap layer 113 can comprise silicon oxynitride, and uses for example sedimentation, globality ground covering substrates 101.On cap layer 113, use for example sedimentation then, form the resilient coating 112 that comprises Si oxide.Then, on resilient coating 112, form the mask layer 111 of patterning, make mask layer 111 have the pattern of definition fin formula structure 110.Mask layer 111 can be hard mask, for example comprises the hard mask of silicon nitride.The method that forms patterned mask layer 111 can be that the use etching method is incited somebody to action the pattern of patterning photoresist (figure does not show) in advance, is transferred in the mask layer 111.
Secondly, as shown in Figure 1, use patterned mask layer 111 as an etching mask, and carry out a fin formula etch structures step.Fin formula etch structures step can remove resilient coating 112, the cap layer 113 and base material 101 of part, and defines fin formula structure 110 structure roughly.So the base material 101 of cap layer 113 below parts becomes fin formula conductor layer 117.Can use dry ecthing method to carry out fin formula etch structures step.For example, utilize CF
4, O
2Come resilient coating 112 and cap layer 113 are carried out dry ecthing with He.In addition, can also use HBr, O
2With He base material 101 is carried out dry ecthing.
Then, as shown in Figure 2, on mask layer 111, resilient coating 112, cap layer 111 and base material 101, form a side-wall material layer 115, to cover formed material layer of background and fin formula conductor layer 117 comprehensively.Side-wall material layer 115 can comprise silicon nitride.Depending on the circumstances or the needs of the situation, before deposited sidewalls material layer 115, can also form with the oxide earlier is another main resilient coating 119, make resilient coating 119 become the second side-wall material layer, and side-wall material layer 115 becomes the first side wall material layer.
Next, just can be as shown in Figure 3, carry out a sidewall etch step, and remove the side-wall material layer 115 of part, with resilient coating 119 depending on the circumstances or the needs of the situation.Obtain to protect the clearance wall 114 of fin formula conductor layer 117 at last, with aforesaid fin formula structure 110.In other words, clearance wall 114 can comprise side-wall material layer 115 and resilient coating 119 depending on the circumstances or the needs of the situation.In addition, clearance wall 114 can be around mask layer 111, resilient coating 112, cap layer 113 and fin formula conductor layer 117.The sidewall etch step also may remove the fin formula structure 110 of part, and obtains the drift angle (corner-rounded) 116 of circle passivation.
Continue, shown in Fig. 4 and Fig. 5 A, utilize mask layer 111 and clearance wall 114 to be used as mask, carry out a base material etching step, and second depression 102 that in base material 101, forms one first depression 103 and link to each other with first depression 103.The position of first depression 103 and second depression 102 is relative, and for example second depression 102 can be around first depression 103.Form first depression 103 and second depression, 102 base material etching steps are not single etching step, comprise etching process repeatedly usually, and set up the first required depression 103 and second depression 102 respectively.
For example, the base material etching step comprises at least once lateral etches step and at least once vertical etching step.Because the order of lateral etches step of the present invention and vertical etching step is also non-key, thus can be depending on the circumstances or the needs of the situation, carry out the lateral etches step earlier or carry out earlier vertical etching step one of them, carry out the required etching step of another time again.
This preferred embodiment can be carried out vertical etching step earlier, and is as shown in Figure 4, sets up first depression 103.For example, use SF
6Come base material 101 is carried out dry ecthing with He, remove the base material 101 of exposure, and form first depression 103 of required size.For example, down remove 5nm～100nm again from clearance wall 114.Subsequently, shown in Fig. 5 A, use dry ecthing method, or dry ecthing method cooperates wet etch method to carry out the lateral etches step, forms the second required depression 102, below fin formula structure 110, form neck part 104 simultaneously.For example, dry ecthing method utilizes SF
6Come base material 101 is carried out dry ecthing with He.Or wet etch method utilizes ammoniacal liquor (NH
3) and low concentration hydrogen peroxide solution (H
2O
2) come base material 101 is carried out wet etching.Note that second depression 102 is preferably wedge shape, that is it carries out etching and forms the below that raised side 105 extends to fin formula structure 110 along specific silicon wafer face.Can certainly carry out the lateral etches step earlier, shown in Fig. 5 B, can consider to combine Fig. 6 B.Depending on the circumstances or the needs of the situation, the width of neck part 104 can be between 3 microns (μ m) and between 10 microns, or the width of neck part 104 is the 40%-60% of fin formula structure 110 width.
Next, form the oxide layer of filling up first depression 103 and second depression 102.Can use diverse ways to form oxide layer.Use diverse ways, formed oxide layer structure maybe be different, make that the structure of final fin formula field-effect transistor is also different.
In the present invention's one first execution mode, can form the oxide layer that supports fin formula structure 110 fully.Please refer to Fig. 6 A, after accomplishing required first depression 103 and second depression 102, just can use oxidizing process to form the oxide layer 120 that supports fin formula structure 110 fully.For example; The base material 101 that uses the furnace oxidation method to come oxidation to be exposed to the open air; That is the silicon atom in the base material 101 of the contiguous fin formula of oxidation structure 110, first depression 103 and second depression 102; Comprise comprehensive (bulk) oxide layer 120 of silica with formation, can be used as a field oxide of isolating base material 101 and fin formula structure 110.The thickness of oxide layer 120 can be 10nm～200nm.At this moment, neck part 104 promptly disappears because of oxidizing process.
Because the cause that is introduced into of oxygen atom, oxide layer 120 can be filled up second depression 102, and almost occupies most first depression 103, and only residual a little first depression 103.In addition, because silicon atom is by the cause of direct oxidation, oxide layer 120 can present very not smooth end face 121 and bottom surface 122, and different with the flat surfaces that uses sedimentation to form (figure does not show), and oxide layer 120 does not contain stress in fact.
Because the function of mask layer 111, resilient coating 112, clearance wall 114 is to be used for protecting fin formula structure 110; Be not etched or oxidation step injures; Therefore; After accomplishing above-mentioned etching or oxidation step, just can remove clearance wall 114, mask layer 111 and resilient coating 112, shown in Fig. 7 A.For example, use wet etch step to remove clearance wall 114.If the gap side wall 114 includes a first material layer and the second sidewall layer, removing the spacer 114 that is, a Merger removing the first layer and the second side wall material layer.
In the present invention's one second execution mode, can form the oxide layer that covers fin formula structure 110 fully.Please refer to Fig. 6 B; After accomplishing required first depression 103 and second depression 102; The oxide layer 120 that just can use sedimentation to form to cover fin formula structure 110 fully and fill up first depression 103 and second depression 102, and the silicon atom in the not oxidation base material 101.
For example, (Spin-On Dielectric SOD), and at the silica containing liquid substance of wafer surface rotary coating, utilizes liquid height filling chink ability, reaches good spreadability to use method of spin coating.Then in liquefaction and with high annealing; Can liquefied material be transformed into the solid oxide layer; Also can use sedimentation to form to cover fully the oxide layer 120 of fin formula structure 110, first depression 103 and second depression 102; Make insulating barrier 120 can comprise oxide, for example silicon dioxide or silicon oxynitride.Note that fin formula structure 110 still directly links to each other with base material 101 owing to there is not the oxidized cause of silicon atom.Depending on the circumstances or the needs of the situation, before sedimentation, can also on the inwall of first depression 103 and second depression 102, be pre-formed a laying 109.Can form laying 109 via oxidation base material 101.Laying 109 can be used for removing flat because etching step and lattice structure can also be repaired in addition to reduce leakage current in base material 101 surfaces of alligatoring.
Next; Please refer to Fig. 7 B; Can carry out a chemico-mechanical polishing (CMP) and etch-back (pullback) step, cut down oxide layer 120 partly, make the outer surface of oxide layer 120 directly contact rough trimming with the bottom of clearance wall 114 via manufacture craft control (process control).So oxide layer 120 is filled up first depression 103 and second depression 102 just, but expose fin formula structure 110 again fully.Operable dry ecthing condition can be CF
4+ O
2With Ar, the wet etching condition can be a dilute hydrofluoric acid, carries out this etch-back (pull back) step.Fill up the oxide layer 120 of first depression 103,, can also be regarded as semiconductor element shallow trench isolation commonly used and leave because go deep in the base material.
Because the function of mask layer 111, resilient coating 112, clearance wall 114 is to be used for protecting fin formula structure 110; Be not etched or oxidation step injures; Therefore; After accomplishing above-mentioned etching or oxidation step, for example oxide layer 120 is filled up after first depression 103 and second depression 102, promptly can remove mask layer 111, resilient coating 112, clearance wall 114.If the gap side wall 114 includes a first material layer and the second sidewall layer, removing the spacer 114 that is, a Merger removing the first layer and the second side wall material layer.
After forming step,, can't influence the grid structure formation step that continuation will be carried out though can form distinct oxide layer 120 through above-mentioned oxide layer.After removing clearance wall 114, just can form required gate dielectric 131.Nowadays the structure of Background 7A promptly becomes the structure shown in Fig. 8 A.Again, depending on the circumstances or the needs of the situation, also can remove cap layer 113, so nowadays the structure of Fig. 7 B promptly becomes the structure shown in Fig. 8 B.Gate dielectric 131 can be general dielectric material, for example high-quality silica, or the dielectric material of high-k, for example HfO
2Or HfZrO
2Or ZrO
2Or BaTiO
3Or Al
2O
3Or Ta
2O
5Or La
2O
3Or Pr
2O
3Form the method for required gate dielectric 131, be present technique personage's common knowledge, so do not add to give unnecessary details.
Afterwards, i.e. formation is positioned on the fin formula structure 110, and controls the grid structure 130 of fin formula structure 110.No matter be the structure shown in Fig. 8 A; Or the structure shown in Fig. 8 B; Can form grid structure 130, make the structure of Fig. 8 A nowadays promptly become the fin formula field effect transistor structure 100 shown in Fig. 9 A, or nowadays the structure of Fig. 8 B become the fin formula field effect transistor structure 100 shown in Fig. 9 B.
For example, on gate dielectric 131, deposit a gate material layers 132 earlier comprehensively, re-use engraving method and define gate material layers 132.If cap layer 113 stays, gate dielectric 131 i.e. direct contact cap cap rock 113.If cap layer 113 is removed, gate dielectric 131 promptly can directly center on fin formula structure 110.At last, patterning grid dielectric layer 131 becomes grid structure 130 with gate material layers 132, so just accomplished the method that the present invention forms various fin formula field effect transistor structure.
The inventive method can obtain the structure of at least two kinds of fin formula field-effect transistors.
At first, shown in Fig. 9 A, in the present invention one first embodiment, a kind of fin formula field effect transistor structure 100 is provided.The fin formula field effect transistor structure 100 of first embodiment of the invention comprises base material 101, fin formula structure 110, insulating barrier 120 and grid structure 130.Normally a kind of semiconductor substrate of base material 101, silicon for example, and can be under suitable situation oxidation and form silica.Insulating barrier 120 is got by the silicon atom direct oxidation in the base material 101, so the insulating barrier 120 of full wafer (bulky) can direct covering substrates 101.Therefore, fin formula field effect transistor structure 100 of the present invention need not higher silicon-coated insulated (SOI) substrate of use cost, and has the advantage on the production cost.
The bottom surface 122 that insulating barrier 120 itself has end face 121 and directly contacts with base material 101.Owing to insulating barrier 120 is got by the silicon atom direct oxidation in the base material 101; Therefore end face 121 and bottom surface 122 at least one and uneven; For example, insulating barrier 120 comprises a plurality of U-shapeds bottom surface 122, and different with the flat surfaces that uses sedimentation to form (figure does not show).And insulating barrier 120 so does not in fact contain stress yet.
110 on fin formula structure is positioned on the insulating barrier 120, and comprises fin formula conductor layer 117 and be positioned at one of fin formula conductor layer 117 both sides group source/drain 118.The preferably has the drift angle (rounded corner) 116 of round passivation above the fin formula structure 110.In the fin formula field effect transistor structure 100 of the present invention, can comprise not only fin formula structure 110, so fin formula structure 110 can also be between adjacent U-shaped bottom surface 122.The fin formula conductor layer 117 of fin formula structure 110 is the part of base material 101 originally, but because the obstruct of insulating barrier 120, and separate fully with base material 101.Depending on the circumstances or the needs of the situation, can also comprise the cap layer 113 that covers fin formula conductor layer 117 among the fin formula structure 110, it can comprise the nitrogen-oxygen-silicon thing.
130 of grid structures surround fin formula structures 110 from three steering portions, and comprise the gate dielectric 131 and gate material layers 132 that surrounds fin formula structure.The grid structure 130 that extends forms continuous U-shaped usually, can control the fin formula structure 110 of many groups simultaneously.If remove cap layer 113,130 of grid structures can be from three direction control fin formula structures 110.If keep cap layer 113,130 of grid structures are from both direction control fin formula structure 110.
Secondly, shown in Fig. 9 B, in the present invention one second embodiment, another kind of fin formula field effect transistor structure 100 is provided again.The fin formula field effect transistor structure 100 of second embodiment of the invention comprises base material 101, fin formula structure 110, insulating barrier 120 and grid structure 130.Normally a kind of semiconductor substrate of base material 101, for example silicon.The preferably has the drift angle 116 of round passivation above the fin formula structure 110.Depending on the circumstances or the needs of the situation, can also comprise the cap layer 113 that covers fin formula conductor layer 117 among the fin formula structure 110, it can comprise the nitrogen-oxygen-silicon thing.If grid structure 130 can then remove cap layer 113 from three direction control fin formula structures 110.If grid structure 130 then keeps cap layer 113 from both direction control fin formula structure 110.Insulating barrier 120 does not contain stress in fact.
The difference of second embodiment of the invention and first embodiment of the invention is; Insulating barrier 120 in the second embodiment of the invention is with the mode of deposition; Insert near the fin formula structure 110, then be arranged in first depression 103 and second depression 102 of base material 101, but not full wafer covering substrates 101.Insulating barrier 120 can comprise silicon dioxide or silicon oxynitride.Shown in Fig. 5 A, second depression 102 is preferably wedge shape, and its raised side 105 extends to the below of fin formula structure 110, therefore in fin formula structure 110, forms a neck part 104.
Fill up insulating barrier 120 covering substrates 101 not only in first depression 103 and second depression 102, and have the raised side 105 that part forms around the neck part 104 of fin formula structure 110, and the bottom surface 122 that directly contacts with base material 101.Raised side 105 extends to fin formula structure 110 belows.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (37)
1. fin formula field effect transistor structure comprises:
Base material;
Insulating barrier, it covers this base material, and the bottom surface that has end face and directly contact with this base material, wherein at least one unevenness of this end face and this bottom surface;
Fin formula structure, it is positioned on this insulating barrier, and comprises a fin formula conductor layer and one group of source/drain; And
Grid structure, its part is surrounded this fin formula structure.
2. fin formula field effect transistor structure as claimed in claim 1, wherein this insulating barrier comprises a plurality of U-shapeds bottom surface, makes this fin formula structure between this adjacent U-shaped bottom surface.
3. fin formula field effect transistor structure as claimed in claim 1 also comprises:
Cap layer, it covers this fin formula conductor layer.
4. fin formula field effect transistor structure as claimed in claim 1, wherein this cap layer comprises the nitrogen-oxygen-silicon thing.
5. fin formula field effect transistor structure as claimed in claim 1, wherein this fin formula structure has a drift angle (corner-rounded) of round passivation.
6. fin formula field effect transistor structure as claimed in claim 1, wherein this insulating barrier does not contain stress in fact.
7. fin formula field effect transistor structure comprises:
Base material;
Fin formula structure, it is positioned on this base material and with this base material and directly links to each other, and this fin formula structure comprises fin formula conductor layer and neck part;
Insulating barrier, it covers this base material, and has the raised side that part forms around this neck part of this fin formula structure, and a bottom surface that directly contacts with this base material, and wherein this raised side extends to below this fin formula structure; And
Grid structure, its part is surrounded this fin formula structure.
8. fin formula field effect transistor structure as claimed in claim 7 also comprises:
Cap layer, it covers this fin formula conductor layer.
9. fin formula field effect transistor structure as claimed in claim 7 also comprises:
Shallow trench isolation leaves, and it is positioned at this insulating barrier below, and has a top that directly contacts with this insulating barrier, and wherein this bottom surface is greater than this top.
10. fin formula field effect transistor structure as claimed in claim 8, wherein this cap layer comprises the nitrogen-oxygen-silicon thing.
11. fin formula field effect transistor structure as claimed in claim 7, wherein this fin formula structure has a drift angle (corner-rounded) of round passivation.
12. fin formula field effect transistor structure as claimed in claim 7, wherein this insulating barrier does not contain stress in fact.
13. fin formula field effect transistor structure as claimed in claim 7 also comprises:
Laying is positioned at this shallow trench isolation and leaves and this insulating barrier, and between this base material and this fin formula structure.
14. fin formula field effect transistor structure as claimed in claim 7, wherein the width of this neck part is between 3 microns (μ m) and between 10 microns.
15. fin formula field effect transistor structure as claimed in claim 7, wherein the width of this neck part is the 40%-60% of this fin formula structure width.
16. a method that forms fin formula field effect transistor structure comprises:
One base material is provided and is positioned at the fin formula structure on this base material;
Carry out a base material etching step; It comprises a lateral etches step and a vertical etching step; With one second depression that in this base material, forms one first depression and link to each other with this first depression, wherein at least one of this first depression and this second depression has a raised side that extends to below this fin formula structure;
Form an oxide layer, to fill up this first depression and this second depression; And
Form a grid structure, surround this fin formula structure with part.
17. the method for formation fin formula field effect transistor structure as claimed in claim 16 is wherein carried out this vertical etching step before this lateral etches step.
18. the method for formation fin formula field effect transistor structure as claimed in claim 16 is wherein carried out this vertical etching step after this lateral etches step.
19. the method for formation fin formula field effect transistor structure as claimed in claim 16, wherein this fin formula structure comprises mask layer, resilient coating, cap layer, fin formula conductor layer and a clearance wall around this mask layer, this resilient coating, this cap layer, this fin formula conductor layer.
20. the method for formation fin formula field effect transistor structure as claimed in claim 19, the method that wherein forms this fin formula structure comprises:
This base material is provided, be positioned at this cap layer on this base material, be positioned on this cap layer this resilient coating be positioned at this mask layer on this resilient coating;
Carry out a fin formula etch structures step with this mask layer as an etching mask, and remove this resilient coating, this cap layer and this base material of part;
Form a side-wall material layer, with this mask layer of comprehensive covering, this resilient coating, this cap layer and this base material; And
Carry out a sidewall etch step, and remove this side-wall material layer partly to obtain this clearance wall.
21. the method for formation fin formula field effect transistor structure as claimed in claim 20, wherein this side-wall material layer comprises the first side wall material layer and the second side-wall material layer.
22. the method for formation fin formula field effect transistor structure as claimed in claim 20, wherein this fin formula etch structures step comprises dry etching steps.
23. the method for formation fin formula field effect transistor structure as claimed in claim 22, wherein this fin formula etch structures step also comprises wet etch step.
24. the method for formation fin formula field effect transistor structure as claimed in claim 16 is wherein used dry ecthing method, cooperates wet etch method wherein one to carry out this lateral etches step with dry ecthing method.
25. the method for formation fin formula field effect transistor structure as claimed in claim 16, wherein this lateral etches step comprises dry etching steps.
26. the method for formation fin formula field effect transistor structure as claimed in claim 25, wherein this lateral etches step also comprises wet etch step.
27. the method for formation fin formula field effect transistor structure as claimed in claim 16, wherein use a furnace oxidation method with this base material of oxidation forming this oxide layer, and this oxide layer becomes a field oxide of isolating this base material and this fin formula structure.
28. the method for formation fin formula field effect transistor structure as claimed in claim 27 also comprises:
After forming this oxide layer, remove this sidewall with wet etching.
29. the method for formation fin formula field effect transistor structure as claimed in claim 16, wherein this vertical etching step is formed for this first depression that a shallow trench isolation leaves.
30. the method for formation fin formula field effect transistor structure as claimed in claim 16, wherein this lateral etches step forms a neck part in this fin formula structure.
31. the method for formation fin formula field effect transistor structure as claimed in claim 30, wherein the width of this neck part is between 3 microns (μ m) and between 10 microns.
32. the method for formation fin formula field effect transistor structure as claimed in claim 30, wherein the width of this neck part is the 40%-60% of this fin formula structure width.
33. the method for formation fin formula field effect transistor structure as claimed in claim 19 also comprises:
This base material of oxidation is to form a laying, and it is positioned on the inwall of this first depression and this second depression.
34. the method for formation fin formula field effect transistor structure as claimed in claim 33 also comprises:
Cover this fin formula structure that comprises this sidewall with this oxide layer; And
Remove this oxide layer of part, make the outer surface of this oxide layer directly contact with the bottom of this clearance wall.
35. the method for formation fin formula field effect transistor structure as claimed in claim 19 also comprises:
, this oxide layer removes this clearance wall after filling up this first depression and this second depression.
36. the method for formation fin formula field effect transistor structure as claimed in claim 19 also comprises:
Remove this mask layer and this resilient coating, make a gate dielectric be able to directly contact this cap layer.
37. the method for formation fin formula field effect transistor structure as claimed in claim 19 also comprises:
Remove this cap layer.
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|---|---|---|---|
| CN201110151663.XA CN102820334B (en) | 2011-06-08 | 2011-06-08 | Fin field effect transistor structure and method for forming fin field effect transistor structure |
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| CN201110151663.XA CN102820334B (en) | 2011-06-08 | 2011-06-08 | Fin field effect transistor structure and method for forming fin field effect transistor structure |
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| CN102820334B CN102820334B (en) | 2017-04-12 |
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