CN103378005B - The manufacture method of multiple gate field effect transistor fin structure - Google Patents
The manufacture method of multiple gate field effect transistor fin structure Download PDFInfo
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- CN103378005B CN103378005B CN201210121162.1A CN201210121162A CN103378005B CN 103378005 B CN103378005 B CN 103378005B CN 201210121162 A CN201210121162 A CN 201210121162A CN 103378005 B CN103378005 B CN 103378005B
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Abstract
The invention provides a kind of manufacture method of multiple gate field effect transistor fin structure, comprising: Semiconductor substrate is provided, comprise p type island region and N-type region; N-type region is formed the first mask layer, forms germanium-silicon layer on the semiconductor substrate; Remove described first mask layer; P type island region and N-type region are formed the second mask layer; Etch described second mask layer, form p type island region groove and N-type region groove; Silicon layer is filled in p type island region groove and N-type region groove; Remove the silicon layer beyond p type island region groove and N-type region groove, and carry out back etching technics; The 3rd mask layer is formed in described p type island region groove and N-type region groove; Remove the second mask layer, form p type island region fin structure and N-type region fin structure.By forming p type island region fin structure and N-type region fin structure respectively on p type island region and N-type region, thus can form the different p type island region fin structure of stress and N-type region fin structure, process is simple, reduces manufacturing cost.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to a kind of manufacture method of multiple gate field effect transistor fin structure.
Background technology
Mos field effect transistor (MOSFET) is constantly to the trend development of minification in recent years, this is to gather way, improving Components integration degree and the cost reducing integrated circuit, transistor scales ground reduce, transistor reduce the limit reaching various performance.Wherein the thickness of gate oxide and source/drain junction depth all reach the limit.
Therefore, industry have developed multiple gate field effect transistor (Multi-GateTransistors), and multiple gate field effect transistor technology is a kind of novel circuit configuration technology.Conventional transistor be each transistor only have grid be used for controlling electric current between two construction units by or interrupt, and then formed calculate in required " 0 " and " 1 ".And multiple-gate transistors Manifold technology is each transistor two or three grids, thus improve the ability of transistor controls electric current, i.e. computing capability, and significantly reduce power consumption, decrease the mutual interference between electric current.Wherein, multiple gate field effect transistor is a kind of device architecture be incorporated into by more than one grid in the type FET of individual devices, this means, raceway groove is on multiple surfaces by several gate wraps, thus leakage current when can suppress " cut-off " state more, and the drive current that can strengthen under " conducting " state, so just obtain the device architecture of lower power consumption and performance enhancement.
J.P.Colinge is called in the Americana of " FinFETsandotherMulti-GateTransistors " one section of name and describes polytype multiple gate field effect transistor, comprise double-gated transistor (Double-Gate, FinFET), tri-gate transistors (Tri-Gate), ohm-shaped gate transistor (Ω-Gate) and quadrangle gate transistor (Quad-Gate) etc.
Wherein, for double-gated transistor, double-gated transistor employs two grids to control raceway groove, greatly inhibits short-channel effect.A concrete distortion of double-gated transistor is exactly fin transistor (FinFET), described FinFET comprises vertical fin structure and across the grid in described fin structure side, be respectively source electrode and drain electrode at the both ends of the fin structure of grid both sides, in the fin structure under grid, form raceway groove.As nonplanar device, the size of the fin structure of FinFET determines the length of effective channel of transistor device.FinFET is compacter compared with the MOS transistor of conventional plane, can realize higher transistor density and less overall microelectric technique.In addition, tri-gate transistors is another Common Shape of multiple-gate transistor, and wherein said grid, across at the side of described fin structure and top surface, controls raceway groove to form three, improves the overall performance of device further.
The vertical direction height of fin structure and horizontal direction width and length have tremendous influence to the performance of drive current, short-channel effect and leakage current etc.The fin structure that such as vertical direction height is higher provides higher drive current, the fin structure that horizontal direction width is less can suppress leakage current better, but, because size constantly reduces, fin structure vertical direction height reduces gradually, in device, the mobility of raceway groove can decrease, then the drive current of device can be affected.Therefore, how by a kind of structure and manufacture method thereof of new multiple gate field effect transistor, the mobility improving multiple gate field effect transistor becomes the problem that industry is urgently studied.
Summary of the invention
The object of this invention is to provide a kind of manufacture method that simultaneously can form the multiple gate field effect transistor fin structure of the different N-type fin structure of structure and P type fin structure.
The invention provides a kind of manufacture method of multiple gate field effect transistor fin structure, comprise the following steps: provide Semiconductor substrate, described Semiconductor substrate comprises p type island region and N-type region; Described N-type region is formed the first mask layer, described p type island region and germanium-silicon layer cover the second mask layer; Remove described first mask layer; Described p type island region and germanium-silicon layer cover the second mask layer; Etch described second mask layer, to form p type island region groove and N-type region groove in described second mask layer; Carry out epitaxial growth technology, to fill silicon layer in described p type island region groove and N-type region groove; Utilize cmp to remove silicon layer beyond described p type island region groove and N-type region groove, and carry out back etching technics; Silicon layer in described p type island region groove and N-type region groove forms the 3rd mask layer; Remove described second mask layer, to form p type island region fin structure and N-type region fin structure respectively on described p type island region groove and N-type region groove.
Further, the material of described first mask layer is one in silicon dioxide, boron nitride and agraphitic carbon or its combination.
Further, the thickness of described first mask layer is 5 ~ 100nm.
Further, the forming process of described first mask layer comprises: form the first mask film on the semiconductor substrate; Etching removes the first mask film on described p type island region, to form the first mask layer in described N-type region.
Further, described p type island region is formed in the step of germanium-silicon layer, epitaxial growth method is adopted to form germanium-silicon layer, the reaction temperature of described epitaxial growth method is 500 DEG C ~ 800 DEG C, reactant comprises silane and germane, the range of flow of described silane is 5sccm ~ 20sccm, and the range of flow of described germane is 1sccm ~ 5sccm.
Further, wet etching method is adopted to remove described first mask layer.
Further, the thickness of described germanium-silicon layer is greater than 50 dusts.
Further, the material of described second mask layer is one in silicon dioxide, boron nitride and agraphitic carbon or its combination, adopts chemical vapour deposition technique to be formed.
Further, dry etching or wet etching is utilized to remove described second mask layer.
Further, the material of described 3rd mask layer is silicon nitride, adopts chemical vapour deposition technique to be formed.
Further, the thickness of described 3rd mask layer is 5 ~ 200nm.
Further, chemical mechanical milling method is adopted to remove described 3rd mask layer.
In sum, the manufacture method of multiple gate field effect transistor fin structure of the present invention by forming the first mask layer in described N-type region, described first mask layer is partly remained in N-type gas and is strengthened in structure in subsequent technique, thus p type island region fin structure and N-type region fin structure can be formed on a semiconductor substrate simultaneously, its technical process is simple, and N-type region fin structure is different with the structure of p type island region fin structure, stress is different, thus forms the N-type region FET device and the p type island region FET device structure that meet different process requirement respectively.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor fin structure in one embodiment of the invention.
Fig. 2 ~ Fig. 9 is the structural representation in the manufacture process of multiple gate field effect transistor fin structure in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor fin structure in one embodiment of the invention.The invention provides a kind of manufacture method of multiple gate field effect transistor fin structure, comprise the following steps:
Step S01: Semiconductor substrate is provided, described Semiconductor substrate comprises p type island region and N-type region;
Step S02: form the first mask layer in described N-type region, and germanium-silicon layer is formed on described p type island region;
Step S03: remove described first mask layer;
Step S04: form the second mask layer on described p type island region and N-type region;
Step S05: etch described second mask layer, to form p type island region groove and N-type region groove in described second mask layer;
Step S06: carry out epitaxial growth technology, to fill silicon layer in described p type island region groove and N-type region groove;
Step S07: utilize cmp to remove silicon layer beyond described p type island region groove and N-type region groove, and carry out back etching technics;
Step S08: the silicon layer in described p type island region groove and N-type region groove forms the 3rd mask layer;
Step S09: remove described second mask layer, to form p type island region fin structure and N-type region fin structure respectively on described p type island region groove and N-type region groove.
Fig. 2 ~ Fig. 9 is the structural representation in the manufacture process of multiple gate field effect transistor fin structure in one embodiment of the invention.The manufacture method of multiple gate field effect transistor fin structure in one embodiment of the invention is described in detail below in conjunction with Fig. 1 ~ Fig. 9.
As shown in Figure 2, in step S01, provide Semiconductor substrate 100, described Semiconductor substrate comprises p type island region 10 and N-type region 20; The material of wherein said Semiconductor substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., the p type island region 10 of described Semiconductor substrate 100 and N-type region 20 are respectively used to form p type island region fin structure and N-type region fin structure, and then form p type island region FET and N-type region FET device structure respectively.Because p type island region FET requires different with the stress of the fin structure of N-type region FET, the structure of the p type island region FET fin structure therefore formed and the fin structure of N-type region FET is different.
As shown in Figure 3, in step S02, described N-type region 20 forms the first mask layer 102, described p type island region 20 forms germanium-silicon layer 104; The material of described first mask layer 104 is one in silicon dioxide, boron nitride and agraphitic carbon or its combination.The forming process of described first mask layer 102 comprises: first, and described Semiconductor substrate 100 is formed the first mask film (not indicating in figure); Then, etching removes the first mask film on described p type island region 10, thus forms the first mask layer 102 in described N-type region 20, and described first mask layer 102 preferably thickness is 5 ~ 100nm.The forming process of described germanium-silicon layer 104 comprises: first in described Semiconductor substrate 100, form germanium-silicon film, and recycling photoetching and etching technics remove the described germanium-silicon film of part, to form germanium-silicon layer 104.In preferred embodiment, epitaxial growth method is adopted to form germanium-silicon layer 104, reaction temperature is 500 DEG C ~ 800 DEG C, reactant comprises silane and germane, the range of flow of described silane is 5sccm ~ 20sccm, the range of flow of described germane is 1sccm ~ 5sccm, owing to being coated with the first mask layer 102 in N-type region 20, therefore utilize epitaxially grown selectivity characrerisitic, only on p type island region 10, form germanium-silicon layer 104, the thickness of described germanium-silicon layer 104 is greater than 50 dusts and is less than 200 dusts, epitaxial growth method can reduce the etching injury to germanium-silicon layer 104, improve the interface evenness of germanium-silicon layer 104.
As shown in Fig. 3 ~ Fig. 4, in step S03, dry etching method is adopted to remove described first mask layer 102.
As shown in Figure 4, in step S04, described p type island region 10 and N-type region 20 form the second mask layer 106; The material of described second mask layer 106 can be one in silicon dioxide, boron nitride and agraphitic carbon or its combination.The thickness range of described second mask layer 106 is 20nm ~ 500nm, and the thickness of described second mask layer 106 specifically can be determined according to the thickness of the p type island region fin structure of follow-up formation and N-type region fin structure, will not limit at this.
As shown in Figure 5, in step S05, etch described second mask layer 106, to form p type island region groove 108a and N-type region groove 108b in described second mask layer 106; Specifically formed by following steps: first on described second mask layer 106, apply photoresist, and utilize exposure and developing process to form the photoresist of patterning, then utilize the photoresist of patterning for mask, etch described second mask layer 106, wet etching is adopted to remove described second mask layer 106, stop in p type island region 10 on germanium-silicon layer 104, N-type region 20 stops in described Semiconductor substrate 100, thus form p type island region groove 108a and N-type region groove 108b in described second mask layer 106.
As shown in Figure 6, in step S06, carry out epitaxial growth technology, to fill silicon layer in described p type island region groove 108a and N-type region groove 108b; Utilize the characteristic of the selective growth of epitaxial growth technology, thus only in the p type island region groove 108a and N-type region groove 108b of exposing semiconductor substrate, grow silicon layer 110, until fill full described p type island region groove 108a and N-type region groove 108b.
As shown in Figures 6 and 7, in step S07, utilize cmp to remove silicon layer 110 beyond described p type island region groove 108a and N-type region groove 108b, and carry out back etching technics; Return in etching process, the segment thickness of the silicon layer 110 in p type island region groove 108a and N-type region groove 108b is etched, and makes the height of silicon layer 110 lower than the height of described second mask layer 106.This silicon layer 110 and the difference in height of described second mask layer 106 are the thickness of follow-up formation the 3rd mask layer 112.
As shown in Figure 8, in step S08, the silicon layer 110 in described p type island region groove 108a and N-type region groove 108b forms the 3rd mask layer 112; The material of described 3rd mask layer 112 can be silicon nitride, the forming process of described 3rd mask layer 112 is as follows: first form one deck silicon nitride film with chemical vapour deposition technique, then remove unnecessary silicon nitride film by the method for cmp, thus form the 3rd mask layer 112.
Composition graphs 6, Fig. 8 and Fig. 9; in step S09; remove described second mask layer 106; to form p type island region fin structure 201 and N-type region fin structure 202 respectively on described p type island region groove 108a and N-type region groove 108b; because the 3rd mask layer 112 is silicon nitride material; compared to the second mask layer 106, there is larger etching selection ratio; thus when etching removal the second mask layer 106; the silicon layer 110 below the 3rd mask layer 112 can be protected; finally on described p type island region 20, form p type island region fin structure, described N-type region 10 forms N-type region fin structure.
After the processing step forming fin structure, described Semiconductor substrate 100 is formed the N-type region grid be located on the upper surface at the middle part of described N-type region fin structure 202 and sidewall, and is located at the p type island region grid etc. on the upper surface at middle part of described p type island region fin structure 201 and sidewall.
In sum, the manufacture method of multiple gate field effect transistor fin structure of the present invention by forming the first mask layer in described N-type region, described first mask layer is partly remained in N-type gas and is strengthened in structure in subsequent technique, thus p type island region fin structure and N-type region fin structure can be formed on a semiconductor substrate simultaneously, its technical process is simple, and N-type region fin structure is different with the structure of p type island region fin structure, stress is different, thus forms the N-type region FET device and the p type island region FET device structure that meet different process requirement respectively.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (13)
1. a manufacture method for multiple gate field effect transistor fin structure, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises p type island region and N-type region, and wherein, described Semiconductor substrate is monocrystalline substrate;
Described N-type region is formed the first mask layer, and form germanium-silicon layer on described p type island region;
Remove described first mask layer;
Described p type island region and N-type region cover the second mask layer;
Etch described second mask layer, described p type island region etching stopping on described germanium-silicon layer, described N-type region etching stopping in described Semiconductor substrate, to form p type island region groove and N-type region groove in described second mask layer;
Carry out epitaxial growth technology, to fill silicon layer in described p type island region groove and N-type region groove;
Utilize cmp to remove silicon layer beyond described p type island region groove and N-type region groove, and carry out back etching technics;
Silicon layer in described p type island region groove and N-type region groove forms the 3rd mask layer;
Remove described second mask layer, to form p type island region fin structure and N-type region fin structure respectively on described p type island region groove and N-type region groove.
2. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, is characterized in that, the material of described first mask layer is one in silicon dioxide, boron nitride and agraphitic carbon or its combination.
3. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, it is characterized in that, the thickness of described first mask layer is 5nm ~ 100nm.
4. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, it is characterized in that, the forming process of described first mask layer comprises:
Form the first mask film on the semiconductor substrate;
Etching removes the first mask film on described p type island region, to form the first mask layer in described N-type region.
5. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, it is characterized in that, epitaxial growth method is adopted to form germanium-silicon layer, the reaction temperature of described epitaxial growth method is 500 DEG C ~ 800 DEG C, reactant comprises silane and germane, the range of flow of described silane is 5sccm ~ 20sccm, and the range of flow of described germane is 1sccm ~ 5sccm.
6. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, is characterized in that, adopts wet etching method to remove described first mask layer.
7. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, it is characterized in that, the thickness of described germanium-silicon layer is greater than 50 dusts.
8. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, is characterized in that, the material of described second mask layer is one in silicon dioxide, boron nitride and agraphitic carbon or its combination, adopts chemical vapour deposition technique to be formed.
9. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, it is characterized in that, the thickness range of described second mask layer is 20nm ~ 500nm.
10. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, is characterized in that, utilizes dry etching or wet etching to remove described second mask layer.
The manufacture method of 11. multiple gate field effect transistor fin structures as claimed in claim 1, is characterized in that, the material of described 3rd mask layer is silicon nitride, adopts chemical vapour deposition technique to be formed.
The manufacture method of 12. multiple gate field effect transistor fin structures as claimed in claim 1, is characterized in that, the thickness of described 3rd mask layer is 5nm ~ 200nm.
The manufacture method of 13. multiple gate field effect transistor fin structures as claimed in claim 1, is characterized in that, adopts chemical mechanical milling method to remove described 3rd mask layer.
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| CN104966672B (en) * | 2015-06-30 | 2019-01-25 | 上海华力微电子有限公司 | Fin field effect pipe matrix preparation method |
| CN107275211B (en) * | 2016-04-06 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| CN107316814B (en) * | 2016-04-26 | 2021-11-23 | 联华电子股份有限公司 | Method for manufacturing semiconductor element |
| CN108573851B (en) * | 2017-03-08 | 2021-05-07 | 上海新昇半导体科技有限公司 | Self-aligned seed layer and preparation method of self-aligned film |
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