CN103367293A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN103367293A
CN103367293A CN2013100985634A CN201310098563A CN103367293A CN 103367293 A CN103367293 A CN 103367293A CN 2013100985634 A CN2013100985634 A CN 2013100985634A CN 201310098563 A CN201310098563 A CN 201310098563A CN 103367293 A CN103367293 A CN 103367293A
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Prior art keywords
semiconductor packages
wire
chip
metal pad
conduction column
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CN2013100985634A
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CN103367293B (zh
Inventor
许文松
林子闳
于达人
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MediaTek Inc
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MediaTek Inc
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Priority to CN201611144375.0A priority Critical patent/CN106952883B/zh
Publication of CN103367293A publication Critical patent/CN103367293A/zh
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Abstract

本发明提供一种半导体封装。上述半导体封装包括基板，具有芯片贴附面；以及芯片，通过导电柱状凸块固接于芯片贴附面上，其中芯片包括金属焊垫，电性耦接至导电柱状凸块，其中金属焊垫具有第一边缘和垂直于第一边缘的第二边缘，其中于俯视图中，上述第一边缘的长度不等于上述第二边缘的长度。本发明所提供的半导体封装，通过灵活设置导电柱状凸块及其他元件，能够解决高密度倒装芯片封装的热电特性问题。

Description

半导体封装
技术领域
本发明有关于一种半导体封装，特别是关于一种高密度的倒装芯片封装。
背景技术
为了确保电子产品或通信设备的小型化和多功能性，会要求半导体封装具有小尺寸，多针连接，高速和高功能。输入/输出(I/O)引脚数的增加再加上对高性能集成电路(IC)的需求增加，导致了倒装芯片封装体的发展。
倒装芯片技术使用芯片上凸块以与例如封装基板的封装介质互连。正面朝下的倒装芯片接合至封装基板经过最短的路径。这些技术可以不仅适用于单一芯片封装技术，也可以适用于更高层数或集成层数的封装技术，在更高层数或集成层数的封装技术中的封装体更大，且这些技术可以适用于容纳数个芯片的更复杂的基板，以形成较大的功能单元。使用一区域阵列的上述倒装芯片技术的优点为实现连接至元件的内连接结构具有更高的密度和使内连接结构对封装体具有非常低的电感。然而，多功能芯片封装因增加了输入/输出(I/O)连接数量会导致热电特性问题，举例来说，散热问题、串扰(crosstalk)、讯号传输延迟(Propagation Delay)或射频(RF)电路的电磁干扰等问题。上述热电特性问题会影响产品的可靠度和质量。
因此，在此技术领域中，有需要一种高密度的倒装芯片封装，以改善上述缺点。
发明内容
为了解决上述的热电特性的技术问题，本发明的目的在于提供改良式的半导体封装，以提升倒装芯片封装的内连接结构的密度。
本发明的实施例提供一种半导体封装。上述半导体封装包括基板，具有芯片贴附面。芯片，通过导电柱状凸块固接于上述芯片贴附面上，其中上述芯片包括金属焊垫，电性耦接至上述导电柱状凸块，其中上述金属焊垫具有第一边缘和垂直于上述第一边缘的第二边缘，其中于俯视图中，上述第一边缘的长度不等于上述第二边缘的长度。
本发明的另一实施例提供一种半导体封装。上述半导体封装包括基板，具有芯片贴附面。芯片，通过导电柱状凸块固接于上述芯片贴附面上，其中上述芯片包括金属焊垫，电性耦接至上述导电柱状凸块，其中上述金属焊垫具有沿第一方向的第一长度和沿第二方向的第二长度，其中于俯视图中，上述第一长度不等于上述第二长度，其中上述第一方向和上述第二方向之间的夹角大于0度且小于等于90度。
本发明的又一实施例提供一种半导体封装。上述半导体封装包括基板，具有芯片贴附面。芯片，通过导电柱状凸块固接于上述芯片贴附面上，其中上述芯片包括金属焊垫，电性耦接至上述导电柱状凸块，其中上述金属焊垫仅于上述俯视图中具有二重旋转对称。
本发明的又一实施例提供一种半导体封装。上述半导体封装包括基板，具有芯片贴附面。芯片，固接于上述芯片贴附面上，上述芯片的主动表面是面对上述基板。多个导电柱状凸块的至少一个具有凸块宽度，上述凸块宽度范围可从实质上等于或大于例如位于上述基板的上述芯片贴附面上的上述导线的线宽至小于上述导线的线宽的2.5倍。
本发明的又一实施例提供一种半导体封装。上述半导体封装包括基板。导线，设置于上述基板上。导电柱状凸块，设置于上述导线上，其中上述导电柱状凸块耦接至芯片。
本发明的又一实施例提供一种半导体封装。上述半导体封装包括基板。第一导线，设置于上述基板上。阻焊层，设置于上述基板上，上述阻焊层具有覆盖上述第一导线的一部分的延伸部分，其中阻焊层的延伸部分具有垂直侧壁，垂直侧壁凸出于与其相邻的第一导线的部分的侧壁。用于传递讯号的第二导线，设置于上述基板上。导电柱状凸块，设置于上述第二导线上，且连接至上述半导体芯片的导电凸块。第一导电结构，设置于上述第二导线和上述导电柱状凸块之间或设置于上述第二导线和上述基板之间。芯片，设置于上述第一导线的上方。
根据本发明所提供的半导体封装，通过灵活设置导电柱状凸块及其他元件，能够解决高密度倒装芯片封装的热电特性问题。
附图说明
图1显示本发明一实施例的半导体封装的剖面示意图。
图2显示本发明一实施例的半导体封装的位于芯片上的导电柱状凸块的详细结构剖面示意图。
图3显示本发明一实施例的半导体封装的金属焊垫和导电柱状凸块的俯视示意图。
图4a显示本发明另一实施例的半导体封装的部分的俯视示意图。
图4b显示沿图4a的I-I’切线的部分剖面图。
图5a至5f显示本发明不同实施例的导电柱状凸块的俯视示意图。
图6a显示本发明又一实施例的半导体封装的部分的俯视示意图。
图6b显示沿图6a的A-A’切线的一种可能的剖面示意图。
图6c显示沿图6a的A-A’切线的另一种可能的剖面示意图。
图6d、6e、6f为图6b、6c的放大示意图，显示本发明不同实施例的导电结构的详细结构。
图7a至7f显示本发明不同实施例的额外金属焊垫的俯视示意图。
图8a至8h为本发明不同实施例的导电柱状凸块和其相应的导线的配置俯视示意图，其中上述导线视为用于绕线的讯号/接地线段。
图9a至9h为本发明不同实施例的导电柱状凸块和其相应的导线的配置俯视示意图，其中每一条上述导线具有视为焊垫区的末端部分。
具体实施方式
在说明书及权利要求书当中使用了某些词汇来称呼特定的元件。本领域的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求书并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及权利要求书当中所提及的“包含”是开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此是包含任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表第一装置可直接电气连接于第二装置，或通过其它装置或连接手段间接地电气连接到第二装置。
图1显示本发明实施例的半导体封装500a的部分剖面示意图。图2显示本发明实施例的半导体封装500a的位于芯片上的导电柱状凸块的详细结构的剖面示意图。在本实施例中，半导体封装500a为倒装芯片封装体(flip chip package)，其使用铜柱状凸块(copper pillar bump)的导电柱状凸块以作为半导体芯片和基板之间的连接。请参考图1和2，半导体封装500a包括基板200，其具有芯片贴附面200a。在本发明一实施例中，基板200可由例如硅的半导体材质来形成，或由例如双马来酰亚胺-三氮杂苯树脂(bismaleimide triacine，BT)、聚酰亚胺(polyimide)或ABF绝缘膜(ajinomoto build-up film，ABF)等有机材质来形成。多个导线210a、210b、220a、220b，设置于基板200的芯片贴附面200a上。在本发明一实施例中，导线210a、210b、220a、220b可包括讯号线或接地线，上述讯号线或接地线可用于直接固接(mounted)至基板200的半导体芯片300的输入/输出(input/output，I/O)连接。
基板200的芯片贴附面200a可被阻焊层(solder resistancelayer)260覆盖。在本实施例中，阻焊层260可由感光材料构成，且可通过微影制程以曝光部分的导线210a、210b、220a、220b和一部分芯片贴附面200a。举例来说，可移除阻焊层260内的位于半导体芯片300的正下方的预定开口区，以形成开口防焊物(open solder mask)或开口阻焊物(open solder resist)，使导线210a、210b、220a、220b从其中的预定开口区暴露出来。
半导体芯片300或芯片300固接于基板200的芯片贴附面200a上，上述芯片300具有面向基板200的主动表面(active surface)。芯片300的电路通过新颖的导线-凸块-导线(trace bump trace，TBT)内连接结构内部连接至基板200的电路。上述TBT内连接结构可包括多个板条形状(lathy)的导电柱状凸块230a和230b，设置于芯片300的主动表面上。导电柱状凸块230a和230b的至少一个可由金属堆栈构成，上述金属堆栈包括例如溅镀凸块下金属层的凸块下金属层(under bumpmetallurgy(UBM)layer)(图未显示)、例如电镀铜层232的铜层232和焊锡盖层(solder cap)234。以下会说明导电柱状凸块230a和230b的详细结构。
请参考图1，导电柱状凸块230a和230b分别对应至芯片贴附面200a上的导线210a、210b。在倒装芯片组装制程期间，例如两个导电柱状凸块230a和230b分别接合至导线210a、210b上。由于导电柱状凸块230a和230b具有小尺寸，所以可以降低接合应力、增加接合至导线的空间(bump-to-trace space)，且有效地避免接合至导线的桥接问题(the problem of bump-to-trace bridging)。并且，可得到更大的绕线空间。经过回焊制程之后，可于具有增加的底座高度(stand-off height)H的芯片300和基板200之间的间隙中导入倒装芯片填充材质204。上述增加的底座高度H有助于进行倒装芯片填充材质制程(underfillprocess)。在本发明实施例中，倒装芯片填充材质204可包括毛细倒装芯片填充材质(capillary underfill，CUF)、成型倒装芯片填充材质(molded underfill，MUF)或上述组合。
图2显示本发明实施例的半导体封装的位于芯片300上的导电柱状凸块310的详细结构的剖面示意图。上述导电柱状凸块的剖面示意图为沿导电柱状凸块的长轴方向的剖面示意图。如图2所示，芯片300可包括基座240、位于基座240上方的第一保护层242、位于第一保护层242之上的金属焊垫243、覆盖金属焊垫243和第一保护层242的第二保护层244，以及位于第二保护层244之上的应力缓冲层246。“之上(overlying)”一词可意指但并非限制于“上(on)”或“上方(over)”。在本实施例中，基座240可包括但并非限制于半导体基板、形成于上述半导体基板的主要表面上的电路元件、层间介电层(ILD)和内连接结构。在本发明实施例中，上述内连接结构可包括多个金属层、与金属层交错堆栈的多个介电层，以及穿过位于半导体基板上的介电层的多个介层孔插塞。金属焊垫243属于内连接结构的金属层的最上层金属层。并且，第一保护层242属于内连接结构的介电层的最上层介电层。第一保护层242可包括但并非限制于氮化硅、氧化硅、氮氧化硅或上述组合。第二保护层244可包括但并非限制于氮化硅、氧化硅、氮氧化硅或上述组合。应力缓冲层246可包括但并非限制于聚酰亚胺(polyimide)、聚苯恶唑(polybenzoxazole，PBO)或上述组合。金属焊垫243可包括但并非限制铝、铜或上述合金。应力缓冲层246可包括第二保护层244。
可于应力缓冲层246中形成开口246a以暴露出来至少一部分的金属焊垫243。开口246a可具有任意形状。在本发明一实施例中，开口246a可为沿导电柱状凸块的长轴方向延伸的板条形状(lathy)或椭圆形状。凸块下金属层(UBM layer)231，可形成于开口246a中暴露出来的金属焊垫243上。凸块下金属层231也可延伸于应力缓冲层246的顶面上。在本实施例中，可利用溅镀法形成凸块下金属层231，且凸块下金属层231可包括钛、铜或上述组合。例如电镀铜层的铜层232，可形成于凸块下金属层231上。可利用铜层232和凸块下金属层231填充开口246a，且位于开口246a内的铜层232和凸块下金属层231可形成集成插塞(integral plug)232a，上述集成插塞232a电性耦接导电柱状凸块(230a或230b)和其下的金属焊垫243。焊锡盖层234，可形成于铜层232上。镍层233，可形成于铜层232和焊锡盖层234之间。例如铜层232的铜层可为重布线层(redistribution layer，RDL)的一部分，或可与重布线层(RDL)同时形成。
图3显示本发明实施例的半导体封装的金属焊垫243和导电柱状凸块310的俯视示意图。在本实施例中，为了改善高密度半导体封装的绕线能力，可缩小金属焊垫的尺寸，使金属焊垫于俯视图中的形状类似于相应的导电柱状凸块于俯视图中的形状。在本发明的实施例中，上述金属焊垫可于俯视图中仅具有二重旋转对称(2-fold rotationalsymmetry)。举例来说，上述金属焊垫可为八角形(octangular shape)或椭圆形(oval-shape)。在如图3所示的本发明的实施例中，形成于基板的芯片贴附面上的金属焊垫243可为八角形。金属焊垫243可具有沿第一方向270的第一边缘243a，以及沿第二方向272的第二边缘243b，其中第二边缘243b实质上垂直于第一边缘243a。并且，第一边缘243a不相邻于第二边缘243b。在本实施例中，在俯视图中，沿第一方向270的第一边缘243a可设计不同于沿第二方向272的第二边缘243b。并且，在如图3所示的俯视图中，金属焊垫243沿第一方向270的第一长度L1可设计不同于沿第二方向272的第二长度L2。在本实施例中，第一长度L1和第二长度L2的比率可设计约介于46:45和99:54之间。在本发明实施例中，第一方向270和第二方向272之间的夹角可设计大于0度且小于等于90度。
在本发明另一实施例中，半导体封装的金属焊垫243可为椭圆形或另一种具180度旋转对称的形状，在俯视图中，金属焊垫243沿第一方向270的第一长度L1可设计不同于沿第二方向272的第二长度L2。并且，第一长度L1和第二长度L2的比率可设计约介于46:45和99:54之间。再者，第一方向270和第二方向272之间的夹角可设计大于0度且小于等于90度。举例来说，如果金属焊垫243为椭圆形，第一方向270也会沿着金属焊垫243的长轴(major axis)，而第二方向272也会沿着金属焊垫243的短轴(minor axis)。
如图2和3所示，于应力缓冲层246中形成开口246a以暴露出来至少一部分的金属焊垫243。在如图3所示的实施例中，开口246a在俯视图中为八角形(octangular shape)。并且，开口246a具有沿第一方向270的第三长度L3和不同于第三长度L3的沿第二方向272的第四长度L4。在本发明另一实施例中，开口246a可为椭圆形或另一种具180度旋转对称的形状，类似于金属焊垫243。另外，导电柱状凸块310在俯视图中可为八角形(octangular shape)或椭圆形(oval-shape)。
在本发明其他实施例中，可设计导电柱状凸块对导线的宽度或长度比率，以进一步改善高密度半导体封装的绕线能力。图4a显示本发明另一实施例的半导体封装500b的部分的俯视示意图。图4b显示沿图4a的I-I’切线的部分剖面图。在本实施例中，半导体封装500a为倒装芯片封装体，其使用铜柱状凸块(copper pillar bump)的导电柱状凸块以作为半导体芯片和基板之间的连接。上述图式中的各元件如有与图1至3所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。
在如图4a和4b所示的实施例中，在俯视图中，导电柱状凸块230a和230b可具有沿导线210a、210b延伸的圆滑且些微拉长的轮廓。在本实施例中，例如导电柱状凸块230b的至少一个导电柱状凸块的凸块宽度Wb范围可从实质上等于或大于例如位于基板200的芯片贴附面200a上的导线210b的导线的线宽W至小于导线的线宽W的2.5倍。在本发明的实施例中，例如导电柱状凸块230b的至少一个导电柱状凸块的凸块长度Lb范围可从例如位于基板200的芯片贴附面200a上的导线210b的导线的线宽W的0.5倍至3倍。并且，芯片300可具有一凸块间隙P，介于50μm和200μm之间。
另外，可设计多个导电柱状凸块的至少一个的形状为除了椭圆形之外的形状，以扩大设计选择。图5a至5f显示本发明不同实施例的导电柱状凸块的俯视示意图。如图5a至5f所示，导电柱状凸块230a1至230a6为非圆滑形状(non-round shape)或非对称形状(asymmetricshape)的导电柱状凸块，可了解本发明并非被上述揭露的实施例所限制。
图6a显示本发明又一实施例的半导体封装500c的一部分的俯视示意图。图6b显示沿图6a的A-A’切线的一种可能的剖面示意图。图6c显示沿图6a的A-A’切线的另一种可能的剖面示意图。本发明一实施例的半导体封装500c为倒装芯片封装体，其使用铜柱状凸块(copperpillar bump)的导电柱状凸块以作为半导体芯片和基板之间的连接。如图6a至图6c所示，本发明又一实施例的半导体封装500c包括基板600，基板600具有设置于其上的第一导线602和第二导线604。在本发明一实施例中，基板600可由例如硅的半导体材质来形成，或由例如双马来酰亚胺-三氮杂苯树脂(bismaleimide triacine，BT)、聚酰亚胺(polyimide)或ABF绝缘膜(ajinomoto build-up film，ABF)等有机材质来形成。在本发明一实施例中，第一导线602和第二导线604可包括讯号线或接地线，上述讯号线或接地线可用于直接固接(mounted)至基板600的半导体芯片610的输入/输出(input/output，I/O)连接。在本实施例中，每一条第一导线602具有可视为基板600的垫区域(pad region)的一部分602a，而每一条第二导线604可视为用于绕线(routing)的讯号线段/接地线段。
请再参考图6a至图6c，形成阻焊层(solder resistance layer)606，以覆盖基板200。另外，除了阻焊层606的延伸部分608之外，阻焊层606暴露出基板600与后续固着于(mounted)基板600之上的半导体芯片610之间的重叠区域。请注意，阻焊层606的延伸部分608沿着第二导线604延伸，且覆盖部分第二导线604。并且，除了延伸部分608之外的阻焊层606设置远离于后续固着的半导体芯片610，且与半导体芯片610相距距离d1。在本发明的实施例中，阻焊层606可包括防焊材质(solder mask material)、氧化物、氮化物或氮氧化物。如图6b所示，阻焊层606的延伸部分608覆盖第二导线604的一部分604a。请注意，阻焊层606的延伸部分608的宽度W2设计为大于第二导线604的一部分604a的宽度W1，使得延伸部分608的底面609的一部分暴露于第二导线604的一部分604a之外。且阻焊层606的延伸部分608具有垂直侧壁(vertical sidewall)607，第二导线604的一部分604a具有垂直侧壁605，垂直侧壁607凸出于与其相邻的垂直侧壁605。因此，延伸部分608与第二导线604的一部分604a共同具有T形剖面。
请再参考图6a至图6c，然后，于第一导线602的一部分602a(亦即垫区域)上形成导电柱状凸块616。在本实施例中，每一个导电柱状凸块616可由金属堆栈构成，上述金属堆栈包括例如溅镀凸块下金属层的凸块下金属层(under bump metallurgy(UBM)layer)(图未显示)、铜层614和焊锡盖层(solder cap)612。在本发明另一实施例中，可于导电柱状凸块616和第一导线602的一部分602a(亦即垫区域)之间形成例如镍的导电缓冲层(图未显示)。上述导电缓冲层可作为导电柱状凸块616的种晶层(seed layer)、黏着层(adhesion layer)和/或阻障层(barrierlayer)。在本发明的实施例中，导电柱状凸块616可作为后续形成的导电凸块的焊点，而导电凸块用于传输半导体芯片610的输入/输出(I/O)讯号、接地讯号或电源讯号。因此，导电柱状凸块616可帮助增加凸块结构的机械强度。
请再参考图6a至图6c，将半导体芯片610固着于基板600的一芯片贴附面上，其中半导体芯片610具有设置于其主动表面624上的多个导电凸块或金属焊垫(或接合焊垫)(图未显示)。上述半导体芯片610的金属焊垫通过导电柱状凸块616分别连接至第一导线602的一部分602a(亦即垫区域)，且导电柱状凸块616位于金属焊垫和第二导线602的一部分602a之间。如图6a所示，阻焊层606设置远离于与导电柱状凸块616重叠的第二导线602的一部分602a(亦即垫区域)，且与第二导线602的一部分602a相距至少一距离d2。并且，阻焊层606的延伸部分608位于半导体芯片610的下方，且位于半导体芯片610的主动表面624的下方，且位于半导体芯片610的投影区域(图未显示)内。
请再参考图6a至图6c，可将倒装芯片填充材质620填充基板600和半导体芯片610之间的间隙，且覆盖阻焊层606。倒装芯片填充材质620用以补偿基板、导线和半导体芯片之间热膨胀系数(CTE)的差异。在本实施例中，阻焊层606的延伸部分608的底面609的一部分被倒装芯片填充材质620包裹。
上述倒装芯片填充材质包裹阻焊层的延伸部分的底面的一部分，且阻焊层的延伸部分的宽度大于第二导线的部分的宽度，使上述倒装芯片填充材质会被由阻焊层的延伸部分和第二导线的部分共同构成的T形物锚定(anchored)。因此，可改善现有技术在倒装芯片填充材质和导线之间发生的倒装芯片填充材质分层(underfill delaminationproblem)问题。并且，阻焊层的延伸部分仅延伸进入半导体芯片的投影区域，以覆盖第二导线的一部分，阻焊层的剩余部分会设置为远离于半导体芯片，且与半导体芯片相距一距离，使半导体封装仍然具有足够的空间容许倒装芯片填充材质流动，以填充基板和半导体芯片之间的间隙。因此，阻焊层的延伸部分不会影响填充倒装芯片填充材质的点胶制程的成果。此外，本发明实施例的半导体封装可应用于多种的封装制程。举例来说，可仅使用成型材质(molding compound)来填充基板和半导体芯片之间的间隙。在本发明另一实施例中，可使用成型材质和倒装芯片填充材质两者填充基板和半导体芯片之间的间隙。在本发明其他实施例中，可仅使用倒装芯片填充材质填充基板和半导体芯片之间的间隙。
另外，可于包括讯号线或接地线的第二导线602之下或之上增加额外导电结构，以扩大设计选择。上述额外导电结构的位置可设计与导电柱状凸块重叠或远离于导电柱状凸块。如图6a至图6c所示，导电结构620a、620b、620c或620d设置于第二导线602和导电柱状凸块616之间或设置于第二导线602和基板600之间。在如图6a至图6c所示的本发明的实施例中，导电结构620a1或620c1设置于第二导线602和基板600之间。另外，导电结构620a1或620c1接触第二导线602和基板600，且与导电柱状凸块616重叠。并且，导电结构620b1或620d1设置与部分第二导线602和半导体芯片610重叠，其中部分第二导线602远离于导电柱状凸块616。在如第6a和6c图所示的本发明另一实施例中，导电结构620a2或620c2设置于第二导线602和导电柱状凸块616之间。并且，导电结构620a2或620c2接触第二导线602和导电柱状凸块616，且与导电柱状凸块616重叠。再者，导电结构620b2或620d2设置与部分第二导线602和基板600重叠，其中部分第二导线602远离于导电柱状凸块616。
在本发明的实施例中，导电结构620a、620b、620c或620d可用于传递讯号。在本发明的实施例中，导电结构620a、620b、620c或620d可包括单一层结构。在本实施例中，导电结构620a和620b为单一层结构，而导电结构620c和620d为多层结构。在本发明的实施例中，上述单一层结构可包括导线或金属焊垫。在本发明的实施例中，上述多层结构可包括导线、金属焊垫或上述组合的堆栈结构。在如图6b和6c所示的本发明的实施例中，设置于第二导线602和基板600之间的导电结构620c1/620c2可包括从顶部至底部的导电结构部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3。每一个导电结构部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3可包括导线或金属焊垫。举例来说，导电结构部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3可分别为导线、金属焊垫和另一导线。因此，导电结构部分620c1-1/620c2-1、620c1-2/620c2-2、620c1-3/620c2-3可共同构成包括导线、金属焊垫或上述组合的堆栈结构。然而，应注意的是导电结构部分的数量并无限制。
类似地，在如图6b和6c所示的本发明的实施例中，设置于第二导线602和半导体芯片610之间的导电结构620d1/620d2可包括从顶部至底部的导电结构部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3。每一个导电结构部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3可包括导线或金属焊垫。举例来说，导电结构部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3可分别为导线、金属焊垫和另一导线。因此，导电结构部分620d1-1/620d2-1、620d1-2/620d2-2、620d1-3/620d2-3可共同构成包括导线、金属焊垫或上述组合的堆栈结构。然而，应注意的是导电结构部分的数量并无限制。
图6d、6e、6f为图6b、6c的放大示意图，显示本发明不同实施例的导电结构620a1、620a2、620b2、620c1和620d2的详细结构。图6d为图6b、6c所示的导电结构620a1或620b2的详细配置。在本实施例中，可视为金属焊垫620a1/620b2的导电结构620a1/620b2直接设置于基板600上，且第二导线602设置于金属焊垫620a1/620b2的顶部上。
图6e为图6c所示的导电结构620a2的详细配置。在本实施例中，第二导线602设置于基板600上。并且，可视为金属焊垫620a2的导电结构620a2设置于第二导线602上。再者，导电柱状凸块616设置于金属焊垫620a2的顶部上。
图6f为图6b、6c所示的导电结构620c1或620d2的详细配置。在本实施例中，导电结构620c1/620d2直接设置于基板600上，且,导线(例如图6b、6c所示的第二导线602)或导电柱状凸块(例如图6b、6c所示的导电柱状凸块616)设置于金属焊垫620c1/620d2的顶部上。在本实施例中，金属焊垫620c1/620d2可包括从顶部至底部的导电结构部分620c1-1/620d2-1、620c1-2/620d2-2、620c1-3/620d2-3。在本实施例中，导电结构部分620c1-1/620d2-1、620c1-2/620d2-2、620c1-3/620d2-3可分别为导线620c1-1/620d2-1、金属焊垫620c1-2/620c2-2和另一导线620c1-3/620d2-3。图6f显示金属焊垫620c1-2/620d2-2夹设于导线620c1-1/620d2-1和导线620c1-3/620d2-3之间。在本发明的实施例中，金属焊垫620c1-2/620d2-2可被更多的金属焊垫取代。
增加在第二导线602之下或之上的额外导电结构在俯视图中可具有不同的形状，以扩大设计选择。图7a至7f显示本发明不同实施例的额外导电结构的俯视示意图。如图7a至7f所示，导电结构720a1至720a6为多边形、圆滑形或水滴形的导电结构。举例来说，如图7a所示的导电结构720a1为长方形(rectangular shape)，如图7b所示的导电结构720a2为正方形(square shape)，如图7c所示的导电结构720a3为新月形(crescent shape)，如图7d所示的导电结构720a4为十边形(decagonal shape)，如图7e所示的导电结构720a5为梯形(decagonalshape)，如图7f所示的导电结构720a6为水滴形(drop-shape)。可了解本发明并非被上述揭露的实施例限制。
并且，设置于半导体芯片上的导电柱状凸块与其相应的导线可具有不同的配置，以扩大设计选择。图8a至8h为本发明不同实施例的导电柱状凸块816和其相应的导线804a-804h的配置俯视示意图。在本实施例中，导线804a-804h可包括讯号线或接地线，上述讯号线或接地线可用于直接固接(mounted)至基板(例如图6a所示的基板600)的半导体芯片(例如图6a所示的半导体芯片610)的输入/输出(input/output，I/O)连接。在本实施例中，每一条导线804a-804h可视为用于绕线(routing)的讯号线段/接地线段。
如图8a所示，导线804a包括具有第一宽度103的至少一第一部分101，和具有第二宽度104的第二部分102，且导电柱状凸块816设置于导线804a的第二部分102上。在本实施例中，可设计使导线804a的第二部分102的第二宽度104大于第一部分101的第一宽度103。并且，用于使导电柱状凸块816接合于其上的导线804a的第二部分102的第二宽度104可设计大于导电柱状凸块816的宽度。并且，可设计使导线804a的第二部分102在俯视图中的轮廓类似于导电柱状凸块816在俯视图中的轮廓。因此，在俯视图中，导电柱状凸块816设置于导线804a的第二部分102内。
如图8b所示，导线804b具有均等的宽度(线宽)，且多个(例如三个)彼此接近导电柱状凸块816形成于导线804b上。在本实施例中，具有较小宽度的导电柱状凸块816可共同用来取代具有较大宽度的单一导电柱状凸块举例来说，如图8b所示的导电柱状凸块816的宽度设计小于图8a所示的(单一)导电柱状凸块816的宽度。
如图8c所示，导线804c包括具有第一宽度103的至少一第一部分101，和具有第二宽度104的第二部分102。导电柱状凸块816设置于导线804c的第二部分102上。在本实施例中，可设计使导线804c的第二部分102的第二宽度104大于第一部分101的第一宽度103。并且，用于使导电柱状凸块816接合于其上的导线804c的第二部分102的第二宽度104可设计大于导电柱状凸块816的宽度。在本实施例中，导线804c的第二部分102的仅一侧的相对边缘的轮廓系设计类似于导电柱状凸块816在俯视图中的轮廓。因此，在俯视图中，导电柱状凸块816设置于导线804c的第二部分102内。
如图8d所示，导线804d的第二部分102具有第二宽度104，上述第二宽度104远大于导线804d的第一部分101的第一宽度103，以使多个导电柱状凸块816设置于其上。在本实施例中，可设计使俯视图中的导线804d的第二部分102的边缘环绕所有的导电柱状凸块816。因此，在俯视图中，多个导电柱状凸块816设置于导线804d的第二部分102内。
如图8e所示，导线804e的第二部分102具有第二宽度104，上述第二宽度104远大于导线804e的第一部分101的第一宽度103，以使多个导电柱状凸块816设置于其上。在本实施例中，可设计使导线804e的第二部分102具有均等的宽度(第二宽度104)。并且，在俯视图中，导线804e的第二部分102的相对边缘可彼此平行。
如图8f所示，导线804f包括具有第一宽度103的至少一第一部分101，具有第二宽度104的至少一第二部分102，和具有第三宽度106的至少一第三部分105。在本实施例中，可设计使导线804f的每一个第二部分102位于两个第一部分101之间。并且，可设计使导线804f的每一个第三部分105位于两个第一部分101之间。在本实施例中，可设计使导线804f的第二部分102的第二宽度104和第三部分105的第三宽度106大于第一部分101的第一宽度103。并且，可设计使导线804f的第二部分102的第二宽度104和第三部分105的第三宽度106大于导电柱状凸块816的宽度。注意可设计使导电柱状凸块816接合于导线804f的第二部分102上。并且，可设计使没有导电柱状凸块816接合于导线804f的第三部分105上。再者，可设计使导线804f的第二部分102在俯视图中的轮廓类似于如第8a或8c图所示的导线804a或804c的第二部分102在俯视图中的轮廓。
图8g和8h为导电柱状凸块816的凸块宽度B和导线804g/804h的线宽W之间的关系。在本发明的实施例中，可设计使导线804g的线宽W小于导电柱状凸块816的凸块宽度B。在本发明另一实施例中，可设计使导线804h的线宽W大于导电柱状凸块816的凸块宽度B。在本发明的实施例中，导电柱状凸块816的凸块宽度B和导线804g/804h的线宽W之间的关系可为10W<B<W/10。
图9a至9h为本发明不同实施例的导电柱状凸块916和其相应的导线902a-902h的配置俯视示意图。在本实施例中，导线902a-902h可包括讯号线或接地线，上述讯号线或接地线可用于直接固接(mounted)至基板(例如图6a所示的基板600)的半导体芯片(例如图6a所示的半导体芯片610)的输入/输出(input/output，I/O)连接。在本实施例中，每一条导线902a-902h可具有视为焊垫区的末端部分。
如图9a所示，导线902a包括具有第一宽度103的第一部分101，和具有第二宽度104的第二部分102。在本实施例中，导线902a的第二部分102可视为焊垫部分102。导电柱状凸块916设置于导线902a的第二部分102上。在本实施例中，可设计使导线904a第二部分102的第二宽度104大于第一部分101的第一宽度103。并且，用于使导电柱状凸块916接合于其上的导线902a的第二部分102的第二宽度104可设计大于导电柱状凸块916的宽度。并且，可设计使导线902a的第二部分102在俯视图中的轮廓类似于导电柱状凸块916在俯视图中的轮廓。因此，在俯视图中，导电柱状凸块916设置于导线902a的第二部分102内。
如图9b所示，导线902b具有均等的宽度(线宽)，且多个(例如三个)彼此接近导电柱状凸块916形成于导线902b上。在本实施例中，导线902b的第二部分102可视为焊垫部分102。在本实施例中，具有较小宽度的导电柱状凸块916可共同用来取代具有较大宽度的单一导电柱状凸块举例来说，如图9b所示的导电柱状凸块916的宽度设计小于第9a图所示的(单一)导电柱状凸块916的宽度。
如图9c所示，导线902c包括具有第一宽度103的至少一第一部分101，和具有第二宽度104的第二部分102。在本实施例中，导线902c的第二部分102可视为焊垫部分102。导电柱状凸块916设置于导线902c的第二部分102上。在本实施例中，可设计使导线902c的第二部分102的第二宽度104大于第一部分101的第一宽度103。并且，用于使导电柱状凸块916接合于其上的导线902c的第二部分102的第二宽度104可设计大于导电柱状凸块916的宽度。在本实施例中，导线902c的第二部分102的仅一侧的相对边缘的轮廓设计类似于导电柱状凸块916在俯视图中的轮廓。因此，在俯视图中，导电柱状凸块916设置于导线902c的第二部分102内。
如图9d所示，导线902d的第二部分102具有第二宽度104，上述第二宽度104远大于导线902d的第一部分101的第一宽度103，以使多个导电柱状凸块916设置于其上。在本实施例中，导线902d的第二部分102可视为焊垫部分102。在本实施例中，可设计使俯视图中的导线902d的第二部分102的边缘环绕所有的导电柱状凸块916。因此，在俯视图中，多个导电柱状凸块916设置于导线902d的第二部分102内。
如图9e所示，导线902e的第二部分102具有第二宽度104，上述第二宽度104远大于导线902e的第一部分101的第一宽度103，以使多个导电柱状凸块916设置于其上。在本实施例中，导线902e的第二部分102可视为焊垫部分102。在本实施例中，可设计使导线902e的第二部分102具有均等的宽度(第二宽度104)。并且，在俯视图中，导线902e的第二部分102的相对边缘可彼此平行。
如图9f所示，导线902f包括具有第一宽度103的至少一第一部分101，具有第二宽度104的至少一第二部分102，和具有第三宽度106的至少一第三部分105。在本实施例中，导线902f的最右边的第二部分102可视为焊垫部分102。在本实施例中，可设计使导线902f的每一个第二部分102位于两个第一部分101之间。并且，可设计使导线902f的每一个第三部分105位于两个第一部分101之间。在本实施例中，可设计使导线902f的第二部分102的第二宽度104和第三部分105的第三宽度106大于第一部分101的第一宽度103。并且，可设计使导线902f的第二部分102的第二宽度104和第三部分105的第三宽度106大于导电柱状凸块916的宽度。注意可设计使导电柱状凸块916接合于导线902f的第二部分102上。并且，可设计使没有导电柱状凸块916接合于导线902f的第三部分105上。再者，可设计使导线902f的第二部分102在俯视图中的轮廓类似于如图9a或9c所示的导线902a或902c的第二部分102在俯视图中的轮廓。
图9g和9h为导电柱状凸块916的凸块宽度B和导线902g/902h的线宽W之间的关系。在本发明的实施例中，可设计使导线902g的线宽W小于导电柱状凸块916的凸块宽度B。在本发明另一实施例中，可设计使导线902h的线宽W大于导电柱状凸块916的凸块宽度B。在本发明的实施例中，导电柱状凸块916的凸块宽度B和导线902g/902h的线宽W之间的关系可为10W<B<W/10。
本领域中技术人员应能理解，在不脱离本发明的精神和范围的情况下，可对本发明做许多更动与改变。因此，上述本发明的范围具体应以后附的权利要求界定的范围为准。

Claims (56)

1.一种半导体封装，包括：
基板，具有芯片贴附面；以及
芯片，通过导电柱状凸块固接于所述芯片贴附面上，其中所述芯片包括：
金属焊垫，电性耦接至所述导电柱状凸块，其中所述金属焊垫具有第一边缘和实质上垂直于所述第一边缘的第二边缘，其中于俯视图中，所述第一边缘的长度不等于所述第二边缘的长度。
2.如权利要求1所述的半导体封装，其特征在于，所述芯片更包括：
内联机结构，位于所述基板和所述金属焊垫之间，其中所述内联机结构包括多个金属层和多个介电层，其中所述内联机结构包括由所述多个介电层的最上层介电层形成第一保护层；
第二保护层，设置于所述基板和所述导电柱状凸块之间，且位于所述金属焊垫上；以及
倒装芯片填充材质，位于所述基板和所述芯片之间。
3.如权利要求1所述的半导体封装，其特征在于，于所述俯视图中，所述金属焊垫为八角形。
4.如权利要求2所述的半导体封装，其特征在于，所述金属焊垫由所述内联机结构的所述多个金属层的最上层金属层形成。
5.如权利要求1所述的半导体封装，其特征在于，所述导电柱状凸块由金属堆栈构成，所述金属堆栈包括凸块下金属层、铜层和焊锡盖层。
6.如权利要求1所述的半导体封装，其特征在于，所述俯视图中，所述金属焊垫的形状类似于相应的所述导电柱状凸块的形状。
7.如权利要求1所述的半导体封装，其特征在于，所述金属焊垫于所述俯视图中仅具有二重旋转对称。
8.如权利要求1所述的半导体封装，其特征在于，所述俯视图中，所述导电柱状凸块为八边形或椭圆形。
9.如权利要求2所述的半导体封装，其特征在于，所述第二保护层具有开口，以暴露所述金属焊垫。
10.如权利要求9所述的半导体封装，其特征在于，于所述俯视图中，所述开口为八边形，且所述开口具有彼此垂直的第三边缘和第四边缘，且其中于所述俯视图中，所述第三边缘的长度不等于所述第四边缘的长度。
11.一种半导体封装，包括：
基板，具有芯片贴附面；以及
芯片，通过导电柱状凸块固接于所述芯片贴附面上，其中所述芯片包括：
金属焊垫，电性耦接至所述导电柱状凸块，其中于俯视图中，所述金属焊垫具有沿第一方向的第一长度和沿第二方向的第二长度，且所述第一长度不等于所述第二长度，且其中所述第一方向和所述第二方向之间的夹角大于0度且小于或等于90度。
12.如权利要求11所述的半导体封装，其特征在于，所述芯片更包括：
内联机结构，位于所述基板和所述金属焊垫之间，其中所述内联机结构包括多个金属层和多个介电层，其中所述内联机结构包括由所述多个介电层的最上层介电层形成第一保护层；
第二保护层，设置于所述基板和所述导电柱状凸块之间，且位于所述金属焊垫上；以及
倒装芯片填充材质，位于所述基板和所述芯片之间。
13.如权利要求11所述的半导体封装，其特征在于，于所述俯视图中，所述金属焊垫为八角形或椭圆形。
14.如权利要求12所述的半导体封装，其特征在于，所述金属焊垫由所述内联机结构的所述多个金属层的最上层金属层形成。
15.如权利要求11所述的半导体封装，其特征在于，所述导电柱状凸块由金属堆栈构成，所述金属堆栈包括凸块下金属层、铜层和焊锡盖层。
16.如权利要求11所述的半导体封装，其特征在于，于所述俯视图中，所述金属焊垫的形状类似于相应的所述导电柱状凸块的形状。
17.如权利要求11所述的半导体封装，其特征在于，所述金属焊垫于所述俯视图中仅具有二重旋转对称。
18.如权利要求11所述的半导体封装，其特征在于，于所述俯视图中，所述导电柱状凸块为八边形或椭圆形。
19.如权利要求12所述的半导体封装，其特征在于，所述第二保护层具有开口，以暴露所述金属焊垫。
20.如权利要求19所述的半导体封装，其特征在于，所述开口于所述俯视图中为八边形，且所述开口具有沿所述第一方向的第三长度和沿所述第二方向的第四长度，其中于俯视图中，所述第三长度不等于所述第四长度。
21.如权利要求11所述的半导体封装，其特征在于，所述第一长度和所述第二长度的比率介于46:45和99:54之间。
22.一种半导体封装，包括：
基板，具有芯片贴附面；以及
芯片，通过导电柱状凸块固接于所述芯片贴附面上，其中所述芯片包括：
金属焊垫，电性耦接至所述导电柱状凸块，其中所述金属焊垫于所述俯视图中仅具有二重旋转对称。
23.如权利要求22所述的半导体封装，其特征在于，所述金属焊垫具有第一边缘和实质上垂直于所述第一边缘的第二边缘，其中于俯视图中，所述第一边缘的长度不等于所述第二边缘的长度。
24.如权利要求22所述的半导体封装，其特征在于，于俯视图中，所述金属焊垫具有沿第一方向的第一长度和沿第二方向的第二长度，且所述第一长度不等于所述第二长度，且其中所述第一方向和所述第二方向之间的夹角大于0度且小于或等于90度。
25.如权利要求22所述的半导体封装，其特征在于，所述芯片更包括：
内联机结构，位于所述基板和所述金属焊垫之间，其中所述内联机结构包括多个金属层和多个介电层，其中所述内联机结构包括由所述多个介电层的最上层介电层形成第一保护层；
第二保护层，设置于所述基板和所述导电柱状凸块之间，且位于所述金属焊垫上；以及
倒装芯片填充材质，位于所述基板和所述芯片之间。
26.如权利要求22所述的半导体封装，其特征在于，于所述俯视图中，所述金属焊垫为八角形或椭圆形。
27.如权利要求22所述的半导体封装，其特征在于，所述金属焊垫由所述内联机结构的所述多个金属层的最上层金属层形成。
28.如权利要求25所述的半导体封装，其特征在于，所述导电柱状凸块由金属堆栈构成，所述金属堆栈包括凸块下金属层、铜层和焊锡盖层。
29.如权利要求22所述的半导体封装，其特征在，于所述俯视图中，所述金属焊垫的形状类似于相应的所述导电柱状凸块的形状金属焊垫。
30.如权利要求22所述的半导体封装，其特征在于，于所述俯视图中，所述导电柱状凸块为八边形或椭圆形。
31.如权利要求25所述的半导体封装，其特征在于，所述第二保护层具有开口，以暴露所述金属焊垫。
32.如权利要求31所述的半导体封装，其特征在于，于俯视图中，所述开口为八边形，且其中于俯视图中，所述开口具有沿所述第一方向的第三长度和沿所述第二方向的第四长度，且所述第三长度不等于所述第四长度。
33.如权利要求24所述的半导体封装，其特征在于，所述第一长度和所述第二长度的比率介于46:45和99:54之间。
34.一种半导体封装，包括：
基板；
导线，设置于所述基板上；以及
导电柱状凸块，设置于所述导线上，其中所述导电柱状凸块耦接至芯片。
35.如权利要求34所述的半导体封装，其特征在于，所述导线包括具有第一宽度的第一部分，和具有第二宽度的第二部分，且所述导电柱状凸块设置于所述导线的所述第二部分上。
36.如权利要求35所述的半导体封装，其特征在于，更包括多个导电柱状凸块，设置于所述导线的所述第二部分上。
37.如权利要求34所述的半导体封装，其特征在于，更包括金属焊垫，位于所述基板和所述导线之间。
38.如权利要求37所述的半导体封装，其特征在于，更包括金属焊垫，位于所述导电柱状凸块和所述导线之间。
39.如权利要求34所述的半导体封装，其特征在于，所述导线包括多个导电层和金属焊垫，其中所述金属焊垫夹设于所述多个导电层之间。
40.一种半导体封装，包括：
基板；
第一导线，设置于所述基板上；
第二导线，设置于所述基板上；
半导体芯片，设置于所述第一导线和所述第二导线的上方；
导电柱状凸块，设置于所述第二导线上，且连接至所述半导体芯片的导电凸块；以及
第一导电结构，设置于所述第二导线和所述导电柱状凸块之间或设置于所述第二导线和所述基板之间。
41.如权利要求40所述的半导体封装，其特征在于，更包括：
阻焊层，设置于所述基板上，且具有延伸部分，所述延伸部分覆盖所述第一导线的部分，其中所述阻焊层的所述延伸部分的宽度大于所述第一导线的所述部分的宽度。
42.如权利要求40所述的半导体封装，其特征在于，所述第一导电结构接触所述第二导线，且与所述导电柱状凸块重叠。
43.如权利要求22所述的半导体封装，其特征在于，更包括：
第二导电结构，设置于与所述第二导线的部分和所述半导体芯片重叠，或者与部分所述第二导线和所述基板重叠，其中所述第二导线的所述部分远离于所述导电柱状凸块。
44.如权利要求43所述的半导体封装，其特征在于，所述第一导电结构或第二导电结构包括单一层结构或多层结构。
45.如权利要求44所述的半导体封装，其特征在于，所述单一层结构包括导线或金属焊垫。
46.如权利要求44所述的半导体封装，其特征在，所述多层结构为导线、金属焊垫或上述组合的堆栈结构。
47.如权利要求40所述的半导体封装，其特征在于，所述第一导电结构为多边形、圆滑形或水滴形。
48.如权利要求40所述的半导体封装，其特征在于，所述第二导线包括讯号线或接地线。
49.如权利要求41所述的半导体封装，其特征在于，所述阻焊层设置以一距离远离于所述第二导线的部分，所述部分与所述导电柱状凸块重叠。
50.如权利要求41所述的半导体封装，其特征在于，更包括倒装芯片填充材质，填充所述基板和所述半导体芯片之间的间隙，且覆盖所述阻焊层。
51.如权利要求41所述的半导体封装，其特征在于，所述阻焊层的所述延伸部分与所述第一导线的所述部分共同具有T型剖面。
52.如权利要求41所述的半导体封装，其特征在于，所述阻焊层的所述延伸部分低于所述半导体芯片且位于所述半导体芯片的投影面积内。
53.如权利要求50所述的半导体封装，其特征在于，所述阻焊层的所述延伸部分的底面的部分从所述第一导线的所述部分暴露出来。
54.如权利要求53所述的半导体封装，其特征在于，所述阻焊层的所述延伸部分的所述部分被所述倒装芯片填充材质包裹。
55.如权利要求41所述的半导体封装，其特征在于，所述阻焊层的所述延伸部分具有垂直侧壁，突出于所述第一导线的所述部分的相邻垂直侧壁，所述相邻垂直侧壁相邻于所述垂直侧壁。
56.如权利要求41所述的半导体封装，其特征在于，所述阻焊层的所述延伸部分沿着所述第一导线延伸，且位于所述半导体芯片的芯片贴附面上方。
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US20170186676A1 (en) 2017-06-29
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US9520349B2 (en) 2016-12-13
US20150145127A1 (en) 2015-05-28
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US10553526B2 (en) 2020-02-04
US20130256878A1 (en) 2013-10-03

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