CN103249263A - Manufacturing method of circuit structure for circuit laminated board - Google Patents
Manufacturing method of circuit structure for circuit laminated board Download PDFInfo
- Publication number
- CN103249263A CN103249263A CN2012100259182A CN201210025918A CN103249263A CN 103249263 A CN103249263 A CN 103249263A CN 2012100259182 A CN2012100259182 A CN 2012100259182A CN 201210025918 A CN201210025918 A CN 201210025918A CN 103249263 A CN103249263 A CN 103249263A
- Authority
- CN
- China
- Prior art keywords
- coating layer
- metal level
- circuit
- substrate
- nanometer coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Laminated Bodies (AREA)
Abstract
A manufacturing method of a circuit structure for a circuit laminated board comprises the following steps: a metal layer forming step, a patterning step, a nano plating layer forming step and a covering layer forming step. Mainly, a flat plating layer with the thickness of 5-40 mm is formed on the outer surface of a circuit metal layer, in virtue of the chemical bonding force of a nano plating layer and a covering layer or a substrate, the interface bonding effect is improved; and in addition, the circuit metal layer and the nano plating layer can be formed on a pre-molded board, and after fishing the pressing with the substrate, the pre-molded board is removed. According to the invention, the surface roughening of the circuit metal layer can be omitted, and reserving circuit width for performing size compensation can be further omitted, so that the circuit density can be increased, and more dense circuits can be manufactured on the same area.
Description
Technical field
The present invention relates to a kind of manufacture method of line construction of circuit laminated plates, mainly is plating nanometer coating layer on the circuit metal level.
Background technology
With reference to figure 1, the generalized section of the line construction of prior art circuit laminated plates.The line construction 1 of prior art circuit laminated plates comprises substrate 10, circuit metal level 22 and cover layer 30.The upper surface 15 of substrate 10 is a rough surface; circuit metal level 22 is formed on the upper surface of substrate 10; usually by copper, aluminium, silver, gold one of them is made at least; cover layer 30 is for cohering glue or welding resisting layer; circuit metal level 22 is covered; because circuit metal level 22 is different with the material of cover layer 30; for fear of delamination; usually the surface of circuit metal level 22 can be utilized mode roughenings such as chemistry, machinery or electricity slurry; increase skin-friction coefficient; and improve interfacial property, and make outer surface 25 form a rough surface.
Yet, prior art has some shortcomings with the surface roughening of circuit metal level 22, when making circuit metal level 22, for the surface roughening with circuit metal level 22, need to reserve width usually, with the compensation width that roughening was reduced, yet present line density is more and more higher, makes to be subject to significant restrictions in design, therefore, need a kind of line build-out that reduces to increase line construction and the manufacture method of line density.
Summary of the invention
Main purpose of the present invention provides a kind of manufacture method of line construction of circuit laminated plates, and this method comprises: a metal level forms step, forms metal level at substrate, and this substrate has coarse upper surface; One patterning step utilizes the image transfer mode that this metal layer pattern is turned to a circuit metal level; One nanometer coating layer forms step, and at the outer surface formation one nanometer coating layer of this circuit metal level, this nanometer coating layer has the thickness of 5～40nm, and after forming this nanometer coating layer, the roughness Ra of outer surface＜0.35 μ m, Rz＜3 μ m; And one cover layer form step, form a cover layer at this substrate, this cover layer is for being to cohere glue or a welding resisting layer, so that this circuit metal level and this Nanoalloy coating layer are covered, in this way, make the circuit metal level for having three flat outer surface, and wherein the outer surface of this circuit metal level, this nanometer coating layer are inspected, and can't judge roughness under 1000 times of light microscopes in the section mode.
Another object of the present invention provides a kind of manufacture method of line construction of circuit laminated plates, comprise: a metal level forms step, form a metal level at a preform substrate, this preform substrate has the flat surfaces of roughness Ra＜0.35 μ m, Rz＜3 μ m; One patterning step utilizes the image transfer mode that this metal layer pattern is turned to a circuit metal level; One nanometer coating layer forms step, and at the outer surface formation one nanometer coating layer of this circuit metal level, this nanometer coating layer has the thickness of 5～40nm, and after forming this nanometer coating layer, the roughness Ra of outer surface＜0.35 μ m, Rz＜3 μ m; One pressing step is to be formed with this preform substrate and a substrate pressing of this circuit metal level and this nanometer coating layer, makes this circuit metal level and this nanometer coating layer are embedded in this substrate by edge; And one remove step, is that this preform substrate is separated with this substrate.In this way, make the circuit metal level for having the four sides flat outer surface, wherein the outer surface of the surface of preforming substrate, this circuit metal level and this nanometer coating layer are inspected in the section mode under 1000 times of light microscopes, can't judge roughness.
The manufacture method of the line construction of circuit laminated plates of the present invention, chemical bonded refractory power by nanometer coating layer and cover layer or substrate, and significantly improved the interface effect, and improved existing in order to improve the interface effect with circuit layer on surface of metal roughening, carry out the side effect of dimension compensation and need to reserve line width, because the surfacing of the line construction of circuit laminated plates of the present invention, do not need to reserve line width and carry out dimension compensation, can increase line density, can be at the more intensive circuit of the making of same area.
Description of drawings
Fig. 1 is the generalized section of the line construction of prior art circuit laminated plates.
Fig. 2 is the flow chart of manufacture method of the line construction of first embodiment of the invention circuit laminated plates.
Fig. 3 A to Fig. 3 D is the progressively generalized section of manufacture method of the line construction of first embodiment of the invention circuit laminated plates.
Fig. 4 is the flow chart of manufacture method of the line construction of second embodiment of the invention circuit laminated plates.
Fig. 5 A to Fig. 5 E is the progressively generalized section of manufacture method of the line construction of second embodiment of the invention circuit laminated plates.
Embodiment
Following conjunction with figs. is done more detailed description to embodiments of the present invention, so that those skilled in the art can implement after studying this specification carefully according to this.
With reference to figure 2, the flow chart of the manufacture method of the line construction of first embodiment of the invention circuit laminated plates.The manufacture method S1 of the line construction of first embodiment of the invention circuit laminated plates comprises metal level and forms step S11, patterning step S13, nanometer coating layer formation step S15 and cover layer formation step S17, simultaneously with reference to figure 3A to Fig. 3 D, the progressively generalized section of the manufacture method of the line construction of first embodiment of the invention circuit laminated plates.As shown in Figure 3A, metal level forms step S11 and forms a metal level 20 at a substrate 10, substrate 10 is made by FR4 glass fibre or bismaleimides-cyanate resin (BT resin), and substrate 10 has a coarse upper surface 15, metal level 20 by copper, aluminium, silver, gold one of them is made at least.
Shown in Fig. 3 B, patterning step S13 utilizes traditional image transfer mode, and for example little shadow, wet etching or modes such as laser line, electric paste etching are patterned as circuit metal level 22 with metal level 20.Shown in Fig. 3 C, nanometer coating layer formation step S15 is the outer surface formation one nanometer coating layer 40 at circuit metal level 22, thickness with 5～40nm, and after forming this nanometer coating layer 40, the roughness Ra of outer surface＜0.35 μ m, Rz＜3 μ m, wherein nanometer coating layer 40 is by copper, tin, aluminium, nickel, silver, at least two kinds of gold are made, form nanometer coating layer 40 mode can for electroless plating (namely, chemical plating), evaporation, sputter or ald (Atomic Layer Deposition, ALD), wherein electroless plating is mainly soaked circuit metal level 22 and is placed a chemical replacement solution to carry out atomic substitutions and form, and the composition of this chemical replacement solution comprises alkane diester diol (Alkyleneglycol) 30～35wt% at least, sulfuric acid 10～30wt%, thiocarbamide (Thiourea) 5～10wt%, tin compound 5wt%.
Shown in Fig. 3 D, cover layer forms step S17 and forms a cover layer 30 at substrate 10, and this cover layer 30 covers circuit metal level 22 and Nanoalloy coating layer 40 for cohering glue or welding resisting layer (that is, green lacquer).Method by first embodiment of the invention, circuit metal level 20 is formed have the structure on three smooth surfaces, wherein surface and this nanometer coating layer 40 of circuit metal level 22 are inspected in the section mode under 1000 times of light microscopes, can't judge roughness.
With reference to figure 4, the flow chart of the manufacture method of the line construction of second embodiment of the invention circuit laminated plates.The manufacture method S2 of the line construction of first embodiment of the invention circuit laminated plates comprises metal level and forms step S21, patterning step S23, nanometer coating layer formation step S25, pressing step S27 and remove step S29.
Simultaneously with reference to Fig. 5 A to Fig. 5 E, the progressively generalized section of the manufacture method of the line construction of second embodiment of the invention circuit laminated plates.Shown in Fig. 5 A, metal level forms step S21 and forms metal level 20 at a preform substrate 100, preform substrate 100 has roughness and levels off to zero, the flat surfaces of roughness Ra＜0.35 μ m, Rz＜3 μ m for example, preform substrate 100 can be a polishing metal plate, for example copperplate, steel plate, aluminium sheet etc., or to have the insulated substrate of polishing metal film, for example have the FR4 substrate of polishing of copper film or have the BT substrate etc. of the aluminium film of polishing,, be not limited thereto only as example at this.Shown in Fig. 5 B, patterning step S23 utilizes traditional image transfer mode, and for example little shadow, wet etching or modes such as laser line, electric paste etching are patterned as circuit metal level 22 with metal level 20.
Shown in Fig. 5 C, nanometer coating layer formation step S25 is the outer surface formation one nanometer coating layer 40 at circuit metal level 22, thickness with 5～40nm, and after forming this nanometer coating layer 40, the roughness Ra of outer surface＜0.35 μ m, Rz＜3 μ m, its composition and manufacture method are identical with first embodiment.Shown in Fig. 5 D, pressing step S27 will be formed with preform substrate 100 and a substrate 10 pressings of circuit metal level 22 and nanometer coating layer 40, make circuit metal level 22 and nanometer coating layer 40 are embedded in the substrate 10 by edge, wherein the outer surface of the surface of preforming substrate 100, this circuit metal level 22 and this nanometer coating layer 40 are inspected in the section mode under 1000 times of light microscopes, can't judge roughness.
Shown in Fig. 5 E, remove step S29, be that preform substrate 100 is separated with substrate 10, thereby formation circuit metal level 22 and nanometer coating layer 40 edges are embedded in the substrate, and make circuit metal level 20 form the structure with smooth surface, four sides.
The manufacture method of the line construction of circuit laminated plates of the present invention, by the chemical bonded refractory power of nanometer coating layer 40 with cover layer 30 or substrate 10, and significantly improved the interface effect, and improved existing in order to improve the interface effect with circuit metal level 20 surface roughenings, carry out the side effect of dimension compensation and need to reserve line width, because the surfacing of the line construction of circuit laminated plates of the present invention, do not need to reserve line width and carry out dimension compensation, can increase line density, can be at the more intensive circuit of the making of same area.
The above person only is in order to explain preferred embodiment of the present invention, be not that attempt is done any pro forma restriction to the present invention according to this, therefore, all have in that identical invention spirit is following do relevant any modification of the present invention or change, all must be included in the category of claim of the present invention.
Claims (9)
1. the manufacture method of the line construction of a circuit laminated plates is characterized in that, the manufacture method of the line construction of this circuit laminated plates comprises:
One metal level forms step, forms a metal level at a substrate, and this substrate has a coarse upper surface;
One patterning step utilizes an image transfer mode that this metal layer pattern is turned to a circuit metal level;
One nanometer coating layer forms step, and at the outer surface formation one nanometer coating layer of this circuit metal level, this nanometer coating layer has the thickness of 5～40nm, and after forming this nanometer coating layer, the roughness of this outer surface is Ra＜0.35 μ m, Rz＜3 μ m; And
One cover layer forms step, forms a cover layer at this substrate, and this cover layer is to cohere glue or a welding resisting layer, so that this circuit metal level and this Nanoalloy coating layer are covered,
Wherein the outer surface of this circuit metal level and this nanometer coating layer are inspected in the section mode under one 1000 times of light microscopes, can't judge roughness.
2. the method for claim 1, it is characterized in that, this substrate is made by FR4 glass fibre or bismaleimides-cyanate resin, this metal level by copper, aluminium, silver, gold one of them is made at least, and this nanometer coating layer is made by copper, tin, aluminium, nickel, silver, gold at least two kinds.
3. the method for claim 1 is characterized in that, it is to form this nanometer coating layer with electroless plating, evaporation, sputter or ald that this nanometer coating layer forms step.
4. method as claimed in claim 3, it is characterized in that, when this nanometer coating layer formation step is made with electroless plating, be this circuit metal level to be soaked place a chemical replacement solution to carry out atomic substitutions and form, the composition of this chemical replacement solution comprises alkane diester diol (Alkyleneglycol) 30～35wt%, sulfuric acid 10～30wt%, thiocarbamide (Thiourea) 5～10wt%, tin compound 5wt% at least.
5. the manufacture method of the line construction of a circuit laminated plates is characterized in that, the manufacture method of the line construction of this circuit laminated plates comprises:
One metal level forms step, forms a metal level at a preform substrate, and this preform substrate has the flat surfaces of roughness Ra＜0.35 μ m, Rz＜3 μ m;
One patterning step utilizes an image transfer mode that this metal layer pattern is turned to a circuit metal level;
One nanometer coating layer forms step, and at the outer surface formation one nanometer coating layer of this circuit metal level, this nanometer coating layer has the thickness of 5～40nm, and after forming this nanometer coating layer, the roughness of this outer surface is Ra＜0.35 μ m, Rz＜3 μ m;
One pressing step is to be formed with this preform substrate and a substrate pressing of this circuit metal level and this nanometer coating layer, makes this circuit metal level and this nanometer coating layer are embedded in this substrate by edge; And
One removes step, is that this preform substrate is separated with this substrate,
Wherein the outer surface of this flat surfaces of this preform substrate, this circuit metal level and this nanometer coating layer are inspected in the section mode under one 1000 times of light microscopes, can't judge roughness.
6. as claim 5 a described method, it is characterized in that, this preform substrate is a polishing metal plate or the insulated substrate with a polishing metal film, wherein metallic plate can be copper coin, aluminium sheet or steel plate, this metallic film can be copper film or aluminium film, and this insulated substrate can be made by FR4 glass fibre or bismaleimides-cyanate resin.
7. as claim 5 a described method, it is characterized in that it is to form this nanometer coating layer with electroless plating, evaporation, sputter or ald that this nanometer coating layer forms step.
8. as claim 7 a described method, it is characterized in that, when this nanometer coating layer formation step is made with electroless plating, be this circuit metal level to be soaked place a chemical replacement solution to carry out atomic substitutions and form, the composition of this chemical replacement solution comprises alkane diester diol (Alkyleneglycol) 30～35wt%, sulfuric acid 10～30wt%, thiocarbamide (Thiourea) 5～10wt%, tin compound 5wt% at least.
9. as claim 5 a described method, it is characterized in that, this substrate is made by FR4 glass fibre or bismaleimides-cyanate resin, this metal level by copper, aluminium, silver, gold one of them is made at least, and this nanometer coating layer is made by copper, tin, aluminium, nickel, silver, gold at least two kinds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100259182A CN103249263A (en) | 2012-02-07 | 2012-02-07 | Manufacturing method of circuit structure for circuit laminated board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100259182A CN103249263A (en) | 2012-02-07 | 2012-02-07 | Manufacturing method of circuit structure for circuit laminated board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103249263A true CN103249263A (en) | 2013-08-14 |
Family
ID=48928394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100259182A Pending CN103249263A (en) | 2012-02-07 | 2012-02-07 | Manufacturing method of circuit structure for circuit laminated board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103249263A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929715A (en) * | 2005-09-05 | 2007-03-14 | 日东电工株式会社 | Wired circuit board |
| CN101404259A (en) * | 2007-10-05 | 2009-04-08 | 新光电气工业株式会社 | Wiring board, semiconductor apparatus and method of manufacturing them |
| WO2011160754A1 (en) * | 2010-06-24 | 2011-12-29 | Merck Patent Gmbh | Process for modifying electrodes in an organic electronic device |
-
2012
- 2012-02-07 CN CN2012100259182A patent/CN103249263A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929715A (en) * | 2005-09-05 | 2007-03-14 | 日东电工株式会社 | Wired circuit board |
| CN101404259A (en) * | 2007-10-05 | 2009-04-08 | 新光电气工业株式会社 | Wiring board, semiconductor apparatus and method of manufacturing them |
| WO2011160754A1 (en) * | 2010-06-24 | 2011-12-29 | Merck Patent Gmbh | Process for modifying electrodes in an organic electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103997862B (en) | Method for manufacturing low-stress low-warping-degree ultrathin odd-layer coreless plate | |
| CN203618240U (en) | Gasket for pressing stepped printed circuit board | |
| TWI498061B (en) | And a method of manufacturing a conductor line on an insulating substrate | |
| JP2012028735A5 (en) | ||
| CN103404243B (en) | Printed circuit board and method for manufacturing the same | |
| CN103327756B (en) | There is multilayer circuit board of local mixing structure and preparation method thereof | |
| CN102711385A (en) | Method for manufacturing circuit board by addition method | |
| CN104685980A (en) | Production method for multilayer printed wiring board, and base material | |
| TW201124024A (en) | Circuit board and process for fabricating the same | |
| CN102244980A (en) | Manufacturing method of metal substrate | |
| CN103781283A (en) | Circuit-board manufacturing method | |
| CN103249263A (en) | Manufacturing method of circuit structure for circuit laminated board | |
| KR101771740B1 (en) | Thin film type chip device and method for manufacturing the same | |
| CN103327754A (en) | Method for manufacturing multilayer circuit structure of circuit laminated board | |
| TWI441585B (en) | Line laminating circuit structure | |
| CN203984767U (en) | A kind of high capacity aluminum-based circuit board | |
| CN103025066B (en) | A kind of preparation method of metal base single-sided doubling plate | |
| CN106211568A (en) | A kind of extra thin copper foil material | |
| CN103249243A (en) | Circuit structure for circuit laminated board | |
| CN103717016B (en) | A kind of anti-hierarchical process of silver-plated circuit board of multilayer high-frequency electrical | |
| CN102510675A (en) | Method for electroplating surface of substrate | |
| CN103379726A (en) | Multiple layer line structure of line laminated board | |
| KR102126611B1 (en) | Method for manufacturing peelable copper foil, coreless substrate and coreless substrate obtained by this method | |
| US20130255858A1 (en) | Method of manufacturing a laminate circuit board | |
| TWI444122B (en) | Line structure of the circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130814 |