CN103226383A - 具有多个存储器管芯和控制器管芯的半导体存储装置 - Google Patents
具有多个存储器管芯和控制器管芯的半导体存储装置 Download PDFInfo
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- CN103226383A CN103226383A CN2013100675074A CN201310067507A CN103226383A CN 103226383 A CN103226383 A CN 103226383A CN 2013100675074 A CN2013100675074 A CN 2013100675074A CN 201310067507 A CN201310067507 A CN 201310067507A CN 103226383 A CN103226383 A CN 103226383A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G06F1/3275—Power saving in memory, e.g. RAM, cache
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- G—PHYSICS
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- G—PHYSICS
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- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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- H—ELECTRICITY
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
Claims (25)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US30804110P | 2010-02-25 | 2010-02-25 | |
US61/308,041 | 2010-02-25 | ||
US12/967,918 | 2010-12-14 | ||
US12/967,918 US8966208B2 (en) | 2010-02-25 | 2010-12-14 | Semiconductor memory device with plural memory die and controller die |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011800108222A Division CN102770920A (zh) | 2010-02-25 | 2011-02-07 | 具有多个存储器管芯和控制器管芯的半导体存储装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103226383A true CN103226383A (zh) | 2013-07-31 |
Family
ID=44477442
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2013100675074A Pending CN103226383A (zh) | 2010-02-25 | 2011-02-07 | 具有多个存储器管芯和控制器管芯的半导体存储装置 |
CN2011800108222A Pending CN102770920A (zh) | 2010-02-25 | 2011-02-07 | 具有多个存储器管芯和控制器管芯的半导体存储装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011800108222A Pending CN102770920A (zh) | 2010-02-25 | 2011-02-07 | 具有多个存储器管芯和控制器管芯的半导体存储装置 |
Country Status (7)
Country | Link |
---|---|
US (2) | US8966208B2 (zh) |
EP (1) | EP2539898A4 (zh) |
JP (1) | JP5728030B2 (zh) |
KR (1) | KR20120134104A (zh) |
CN (2) | CN103226383A (zh) |
TW (1) | TW201205577A (zh) |
WO (1) | WO2011103658A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106575133A (zh) * | 2014-07-18 | 2017-04-19 | 高通股份有限公司 | 用于管芯到管芯接口中的时钟分发的***和方法 |
CN107980126A (zh) * | 2015-06-05 | 2018-05-01 | 桑迪士克科技有限责任公司 | 多裸芯储存装置的调度方案 |
CN109753456A (zh) * | 2017-11-03 | 2019-05-14 | 三星电子株式会社 | 包括裸芯上终止电路的存储器器件 |
WO2021088933A1 (zh) * | 2019-11-07 | 2021-05-14 | 安徽寒武纪信息科技有限公司 | 存储器以及包括该存储器的设备 |
Families Citing this family (49)
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JP5627197B2 (ja) * | 2009-05-26 | 2014-11-19 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体記憶装置及びこれを備える情報処理システム並びにコントローラ |
US8966208B2 (en) | 2010-02-25 | 2015-02-24 | Conversant Ip Management Inc. | Semiconductor memory device with plural memory die and controller die |
US8582373B2 (en) | 2010-08-31 | 2013-11-12 | Micron Technology, Inc. | Buffer die in stacks of memory dies and methods |
CN103021465A (zh) * | 2011-09-22 | 2013-04-03 | 盛科网络(苏州)有限公司 | 分块设计的芯片存储器及运用所述芯片存储器的方法及*** |
US20130119542A1 (en) * | 2011-11-14 | 2013-05-16 | Mosaid Technologies Incorporated | Package having stacked memory dies with serially connected buffer dies |
US9627357B2 (en) * | 2011-12-02 | 2017-04-18 | Intel Corporation | Stacked memory allowing variance in device interconnects |
US8797799B2 (en) * | 2012-01-05 | 2014-08-05 | Conversant Intellectual Property Management Inc. | Device selection schemes in multi chip package NAND flash memory system |
US8561001B1 (en) * | 2012-07-11 | 2013-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for testing stacked dies |
US8966419B2 (en) * | 2012-07-11 | 2015-02-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for testing stacked dies |
US8737108B2 (en) * | 2012-09-25 | 2014-05-27 | Intel Corporation | 3D memory configurable for performance and power |
US9679615B2 (en) * | 2013-03-15 | 2017-06-13 | Micron Technology, Inc. | Flexible memory system with a controller and a stack of memory |
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US9780782B2 (en) * | 2014-07-23 | 2017-10-03 | Intel Corporation | On-die termination control without a dedicated pin in a multi-rank system |
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US9842633B2 (en) * | 2014-12-11 | 2017-12-12 | Micron Technology, Inc. | Tracking and correction of timing signals |
US9934179B2 (en) | 2015-02-17 | 2018-04-03 | Mediatek Inc. | Wafer-level package with at least one input/output port connected to at least one management bus |
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US9640236B2 (en) | 2015-03-12 | 2017-05-02 | Invensas Corporation | Reduced load memory module using wire bonds and a plurality of rank signals |
WO2016195736A1 (en) * | 2015-06-02 | 2016-12-08 | Cambou Bertrand F | Memory circuit using resistive random access memory arrays in a secure element |
KR20170025948A (ko) * | 2015-08-31 | 2017-03-08 | 에스케이하이닉스 주식회사 | 반도체 시스템 및 제어 방법 |
KR102275812B1 (ko) * | 2015-09-04 | 2021-07-14 | 삼성전자주식회사 | 센터 패드 타입의 스택드 칩 구조에서 신호 완결성 이슈를 개선할 수 있는 온다이 터미네이션 스키마를 갖는 반도체 메모리 장치 |
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KR102611266B1 (ko) * | 2016-09-02 | 2023-12-08 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
KR102665270B1 (ko) * | 2016-11-09 | 2024-05-13 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그것의 동작 방법 |
KR20180130417A (ko) * | 2017-05-29 | 2018-12-07 | 삼성전자주식회사 | 온-다이 터미네이션의 제어 방법 및 이를 수행하는 시스템 |
US10566038B2 (en) * | 2017-05-29 | 2020-02-18 | Samsung Electronics Co., Ltd. | Method of controlling on-die termination and system performing the same |
US10490245B2 (en) | 2017-10-02 | 2019-11-26 | Micron Technology, Inc. | Memory system that supports dual-mode modulation |
US10725913B2 (en) | 2017-10-02 | 2020-07-28 | Micron Technology, Inc. | Variable modulation scheme for memory device access or operation |
US10355893B2 (en) | 2017-10-02 | 2019-07-16 | Micron Technology, Inc. | Multiplexing distinct signals on a single pin of a memory device |
US11403241B2 (en) | 2017-10-02 | 2022-08-02 | Micron Technology, Inc. | Communicating data with stacked memory dies |
US10446198B2 (en) | 2017-10-02 | 2019-10-15 | Micron Technology, Inc. | Multiple concurrent modulation schemes in a memory system |
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US9348786B2 (en) | 2016-05-24 |
WO2011103658A1 (en) | 2011-09-01 |
US20110208906A1 (en) | 2011-08-25 |
KR20120134104A (ko) | 2012-12-11 |
EP2539898A4 (en) | 2016-03-30 |
US8966208B2 (en) | 2015-02-24 |
EP2539898A1 (en) | 2013-01-02 |
JP5728030B2 (ja) | 2015-06-03 |
CN102770920A (zh) | 2012-11-07 |
JP2013520732A (ja) | 2013-06-06 |
US20150161072A1 (en) | 2015-06-11 |
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