CN103187404A - 半导体芯片堆叠封装结构及其工艺 - Google Patents

半导体芯片堆叠封装结构及其工艺 Download PDF

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CN103187404A
CN103187404A CN2011104581912A CN201110458191A CN103187404A CN 103187404 A CN103187404 A CN 103187404A CN 2011104581912 A CN2011104581912 A CN 2011104581912A CN 201110458191 A CN201110458191 A CN 201110458191A CN 103187404 A CN103187404 A CN 103187404A
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semiconductor chip
packaging
base plate
pad
bonding wire
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刘胜
陈润
陈照辉
刘孝刚
李操
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刘胜
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Abstract

半导体芯片堆叠封装结构及其工艺，包括数个半导体芯片，封装基板、塑封材料，其特征在于按上下次序最底下的半导体芯片A有源表面朝下，通过焊球阵列将半导体芯片A连接到封装基板的电路层上，半导体芯片A下表面充填底部填充料，借助粘合层将半导体芯片B粘合在半导体芯片A背面，半导体芯片C、半导体芯片D以及以上的半导体芯片呈层状堆叠在半导体芯片B上方，通过焊线将半导体芯片B、半导体芯片C、半导体芯片D及以上的半导体芯片上的焊盘与封装基板上电路层相连，堆叠封装结构的封装芯片呈层状堆叠布置。本发明的优点是制作工艺简单，满足高封装密度的要求，降低封装成本，同时提高封装的可靠性。

Description

半导体芯片堆叠封装结构及其工艺
技术领域
本发明涉及一种半导体器件的结构及其制造方法，特别涉及一种半导体芯片堆叠封装结构及其工艺。
背景技术
半导体产品的集成度按摩尔定律每18个月翻一番。随着半导体产业的深入发展，摩尔定律受到越来越多的阻碍，要实现摩尔定律所付出的成本越来越高，然而人们对于半导体产品性能的要求却从未停止。目前，通过改变半导体产品封装形式的方向寻求提高产品性能的途径是一个新的方向，三维***级封装也随之产生。
三维堆叠封装可以在更小的空间内集成更多的半导体芯片，采用三维堆叠封装的产品拥有更高的性能、更高的可靠性，以及更低的价格。目前，采用三维堆叠封装的产品，例如存储器，能实现更大的存储量，并且已经实现工业化生产。
发明内容
本发明的目的是针对已有技术中存在的缺陷，提供一种半导体芯片堆叠封装结构及其工艺。
本发明包括数个半导体芯片，封装基板、塑封材料，其特征在于按上下次序最底下的半导体芯片A有源表面朝下，经焊球阵列将半导体芯片A连接到封装基板的电路层上，半导体芯片A下表面充填底部填充料，以提高焊球的可靠性，借助粘合层将半导体芯片B粘合在半导体芯片A背面，半导体芯片C、半导体芯片D以及以上的半导体芯片呈层状堆叠在半导体芯片B上方，经焊线将半导体芯片B、半导体芯片C、半导体芯片D及以上的半导体芯片上的焊盘与封装基板上电路层相连。
所述半导体芯片A采用倒装结构，半导体芯片B、半导体芯片C、半导体芯片D及以上的半导体芯片采用正装结构。半导体芯片A通过焊料球阵列与封装基板连接，焊球阵列的间距为0.050～0.500mm，焊球直径为0.050～0.500mm，焊球的成份为Pb/Sn，SnAgCu，SnAg，焊球阵列可以呈完全分布或部分分布。经塑封材料将所有半导体芯片以及焊线密封在封装基板上。
所述半导体芯片B的上方可以选择性的堆叠一层或者多层半导体芯片，半导体芯片之间采用粘合层与间隔层固定，通过间隔层预留出焊线的空间。
所有的半导体芯片表面的焊盘、焊线为金、铜、或铝等金属。粘合层可以采用有机高分子银胶，或者无机高分子银胶。封装基板采用硅基板，陶瓷基板，塑料基板。
半导体芯片堆叠封装结构的封装工艺，其特征在于依次包含以下步骤：
(1)制备封装用的封装基板；
(2)制备半导体芯片A下表面的凸点焊球，采用焊料焊接、热压焊接、或者热声焊接方式将半导体芯片A下表面凸点焊球焊接在封装基板上表面的焊盘上，半导体芯片A经焊料球阵列与封装基板上焊盘相连；
(3)在半导体芯片A下表面***注射底部填充料并完成固化；
(4)通过粘合层将半导体芯片B固定在半导体芯片A的上表面；
(5)通过粘合层和间隔层将半导体芯片C固定在半导体芯片B的上表面，并在间隔层为焊线预留空间；
(6)通过粘合层和间隔层将半导体芯片D固定在半导体芯片C的上表面，并在间隔层为焊线预留空间；
(7)通过粘合层和间隔层将半导体芯片E固定在半导体芯片D的上表面，并在间隔层为焊线预留空间；
(8)在半导体芯片B、半导体芯片C、半导体芯片D以及半导体芯片E上表面的焊盘和封装基板上焊盘之间采用超声键合、热压键合、或热超声键合工艺焊接焊线，实现电连接；
(9)通过塑封工艺将所有半导体芯片和焊线密封封装；
(10)在封装基板下表面的焊盘上通过丝网印刷工艺、电镀或者蒸镀工艺涂布，再通过回流制备焊球，通过封装基板内部电路与封装基板下表面的焊球连接。
本发明的优点是本发明的工艺流程简单、成本低，适合大规模工业化生产，同时本发明的半导体芯片三维堆叠封装结构具有可靠性高，能够满足高集成度对半导体产品性能的要求。
附图说明
图1本发明的半导体芯片堆叠封装结构的剖面示意图；
图2封装基板的结构示意图；
图3采用倒装芯片方式将半导体芯片A固定在封装基板上表面的结构示意图；
图4在半导体芯片A下表面填充底部填充料的结构示意图；
图5在半导体芯片A的上表面固定半导体芯片B的结构示意图；
图6在半导体芯片B的上表面上固半导体芯片C的结构示意图；
图7在半导体芯片C的上表面上固定半导体芯片D的结构示意图；
图8在半导体芯片D的上表面上固定半导体芯片E的结构示意图；
图9在半导体芯片和封装基板之间通过焊线实现电连接的结构示意图；
图10通过塑封工艺将半导体芯片以及焊线密封的结构示意图；
图11在封装基板下表面制作焊球阵列的示意图；
图12实施例二的结构示意图；
图13实施例三的结构示意图。
图中：1半导体芯片A、2半导体芯片B、3粘合层、4环氧模塑料、5填充料、6封装基板、6c互连电路、7封装基板上表面的焊盘、8芯片B的焊盘、9焊线、10封装基板上表面的焊盘、11封装基板下表面焊盘、12封装基板下表面的焊球阵列、13半导体芯片A下表面焊料球阵列、14封装基板上表面的焊盘、15焊线、16芯片C的焊盘、17粘合层、17a间隔层、18半导体芯片C、19粘合层、19a间隔层、20半导体芯片D、21粘合层、21a间隔层、22半导体芯片E、23焊线、24芯片D的焊盘、25焊线、26芯片E的焊盘。
具体实施方式
实施例一
下面结合附图进一步说明本实施例：
按上下次序最底下的半导体芯片A有源表面朝下，通过焊球阵列-13将半导体芯片A连接到封装基板6的电路层上。所述封装基板6采用硅基板，陶瓷基板，塑料基板。焊球阵列13的间距为0.050～0.500mm，焊球直径为0.050～0.500mm，焊球的成份为Pb/Sn，SnAgCu，SnAg，焊球阵列可以呈完全分布或部分分布。半导体芯片A下表面充填底部填充料5，以提高焊球13的可靠性。借助粘合层3将半导体芯片B粘合在半导体芯片A背面，半导体芯片C、半导体芯片D以及以上的半导体芯片呈层状堆叠在半导体芯片B上方，半导体芯片A采用倒装结构，半导体芯片B、半导体芯片C、半导体芯片D及半导体芯片E采用正装结构。通过焊线将半导体芯片B、半导体芯片C、半导体芯片D及半导体芯片E上的焊盘8、焊盘16、焊盘24、焊盘26与封装基板6上电路层上的焊盘7、焊盘10相连，堆叠封装结构的封装芯片呈层状堆叠布置。半导体芯片B以上可以选择性的堆叠一层或者多层半导体芯片，本实施例在半导体芯片B上堆叠三层半导体芯片。半导体芯片之间采用粘合层3、17、19、21与间隔层17a、19a、21a固定，粘合层3、17、19、21可以采用有机高分子银胶，或者无机高分子银胶。通过间隔层17a、19a、21a预留出焊线的空间。塑封材料将所有半导体芯片以及焊线密封在封装基板上。所有的半导体芯片表面的焊盘、焊线为金、铜或铝金属材料制作。
本实施例具体实现半导体芯片三维堆叠封装的工艺步骤如下：
(1)如图2所示，制备封装所用封装基板6，所用材料可以是硅基板、陶瓷基板、塑料基板如BT，FR4、复合材料如A1SiC、MCPCB，其中封装基板的上部表面6a以及封装基板的下表面6b包括起电连接作用的焊盘，封装基板内部包括内部多层互连电路6c。
(2)如图3所示，制备半导体芯片A下表面下凸点13，然后采用焊料焊接、热压焊接、或者热声焊接等方式将芯片下表面凸点焊接在封装基板6上表面6a的焊盘14上，半导体芯片A通过焊料球阵列13与封装基板6上焊盘相连，经由封装基板6内部电路6c与封装基板下表面焊盘11相连。
(3)如图4所示，充填底部填充料。在半导体芯片A下表面***注射填充料5，填充料5由热固性聚合物以及二氧化硅的填料组成。由于半导体芯片A下表面和封装基板6之间缝隙的毛细作用，填料被吸入半导体芯片A和封装基板6上表面之间的空隙。然后加热到130℃左右，保持3～4个小时完成固化。
(4)如图5所示，通过粘合层3将半导体芯片B固定在半导体芯片A的表面上方，粘合剂可以采用高分子贴片材料或者焊料。
(5)如图6所示，通过粘合层17和间隔层17a将半导体芯片C固定在半导体芯片B的上表面，间隔层17a为焊线预留空间。
(6)如图7所示，通过粘合层19和间隔层19a将芯片D固定在芯片C的上表面，间隔层19a为焊线预留空间。
(7)如图8通过粘合层21和间隔层21a将半导体芯片E固定在半导体芯片D的上表面，间隔层21a为焊线预留空间。
(8)如图9所示，在半导体芯片B、半导体芯片C、半导体芯片D及半导体芯片E上表面的焊盘8、16、24以及26和封装基板6上焊盘7、焊盘10之间焊接焊线9、15、23、25实现电连接。焊线材料可以采用金线、铝线或铜线，焊线工艺可以采用超声键合、热压键合、或热超声键合工艺。
(9)如图10所示，通过塑封工艺将所有半导体芯片和焊线密封起来，密封材料4可以选用环氧模塑料(EMC)等。
(10)如图11所示，在焊盘11上制备焊球阵列12，焊料可以采用铅锡焊料、金锡焊料、或者锡银铜无铅焊料。凸点制备工艺可以采用丝网印刷工艺、蒸镀或者电镀，然后回流工艺形成焊球阵列12。
实施例二
实施例二与实施例一相同，所不同的是本实施例采用了两层堆叠的封装形式，参见图12。
实施例三
实施例三与实施例一相同，所不同的是本实施例采用三层堆叠的封装形式，参见图13。

Claims (9)

1.一种半导体芯片堆叠封装结构，包括数个半导体芯片，封装基板、塑封材料，其特征在于按上下次序最底下的半导体芯片A有源表面朝下，经焊球阵列将半导体芯片A连接到封装基板的电路层上，半导体芯片A下表面充填底部填充料，借助粘合层将半导体芯片B粘合在半导体芯片A背面，半导体芯片C、半导体芯片D以及以上的半导体芯片呈层状堆叠在半导体芯片B上方，经焊线将半导体芯片B、半导体芯片C、半导体芯片D及以上的半导体芯片上的焊盘与封装基板上电路层相连，堆叠封装结构的封装芯片呈层状堆叠布置。
2.根据权利要求1所述的一种半导体芯片堆叠封装结构，其特征在于所述半导体芯片A为倒装结构，半导体芯片B、半导体芯片C、半导体芯片D及以上的半导体芯片为正装结构。
3.根据权利要求1所述的一种半导体芯片堆叠封装结构，其特征在于所述半导体芯片A通过焊料球阵列与封装基板连接，焊球阵列的间距为0.050～0.500mm，焊球直径为0.050～0.500mm，焊球的成份为Pb/Sn，SnAgCu，SnAg，焊球阵列可以呈完全分布或部分分布。
4.根据权利要求1所述的一种半导体芯片堆叠封装结构，其特征在于所述半导体芯片B的上方可以选择性的堆叠一层或者多层半导体芯片，半导体芯片之间经粘合层与间隔层固定，通过间隔层预留出焊线的空间。
5.根据权利要求1所述的一种半导体芯片堆叠封装结构，其特征在于所述塑封材料将所有半导体芯片以及焊线密封在封装基板上。
6.根据权利要求1所述的一种半导体芯片堆叠封装结构，其特征在于所述所有的半导体芯片表面的焊盘、焊线材料可采用金、铜或铝等金属。
7.根据权利要求1所述的一种半导体芯片堆叠封装结构，其特征在于所述粘合层采用有机高分子银胶，或者无机高分子银胶。
8.根据权利要求1所述的一种半导体芯片堆叠封装结构，其特征在于所述封装基板采用硅基板，陶瓷基板，塑料基板。
9.一种半导体芯片堆叠封装结构的封装工艺，其特征在于依次包含以下步骤：
(1)制备封装用的封装基板；
(2)制备半导体芯片A下表面的凸点焊球，采用焊料焊接、热压焊接，或者热声焊接方式将半导体芯片A下表面凸点焊球焊接在封装基板上表面的焊盘上，半导体芯片A经焊料球阵列与封装基板上焊盘相连；
(3)在半导体芯片A下表面***注射底部填充料并完成固化；
(4)通过粘合层将半导体芯片B固定在半导体芯片A的上表面；
(5)通过粘合层和间隔层将半导体芯片C固定在半导体芯片B的上表面，并在间隔层为焊线预留空间；
(6)通过粘合层和间隔层将半导体芯片D固定在半导体芯片C的上表面，并在间隔层为焊线预留空间；
(7)通过粘合层和间隔层将半导体芯片E固定在半导体芯片D的上表面，并在间隔层为焊线预留空间；
(8)在半导体芯片B、半导体芯片C、半导体芯片D以及半导体芯片E上表面的焊盘和封装基板上焊盘之间采用超声键合、热压键合，或热超声键合工艺焊接焊线，实现电连接；
(9)通过塑封工艺将所有半导体芯片和焊线密封封装；
(10)在封装基板下表面的焊盘上通过丝网印刷工艺、电镀或者蒸镀工艺涂布焊料，再通过回流制备焊球，通过封装基板内部电路与封装基板下表面的焊球连接。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538368A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种基于二次塑封技术的三维堆叠封装结构及其制备方法
CN105280562A (zh) * 2014-05-27 2016-01-27 爱思开海力士有限公司 具有翼部分的挠性堆叠封装件
CN109727913A (zh) * 2017-10-30 2019-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
CN110660891A (zh) * 2018-06-29 2020-01-07 合肥彩虹蓝光科技有限公司 一种倒装器件封装方法及结构
CN113629021A (zh) * 2021-08-09 2021-11-09 长江存储科技有限责任公司 半导体器件封装结构及其制造方法
WO2024016505A1 (zh) * 2022-07-22 2024-01-25 长鑫存储技术有限公司 半导体堆叠结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015803A1 (en) * 2001-07-20 2003-01-23 Optosys Technologies Gmbh High-density multichip module and method for manufacturing the same
CN1441469A (zh) * 2002-02-25 2003-09-10 精工爱普生株式会社 半导体晶片、半导体装置和它们的制造方法、电路板和仪器
CN1484308A (zh) * 2002-09-17 2004-03-24 ���˻�˹�����̩�˹ɷ����޹�˾ 开口式多芯片堆叠封装体
US20050009236A1 (en) * 1996-05-20 2005-01-13 Ball Michael B. Method of fabrication of stacked semiconductor devices
CN102185090A (zh) * 2011-03-29 2011-09-14 晶科电子（广州）有限公司 一种采用cob封装的发光器件及其制造方法
CN202434508U (zh) * 2011-12-31 2012-09-12 刘胜 半导体芯片堆叠封装结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050009236A1 (en) * 1996-05-20 2005-01-13 Ball Michael B. Method of fabrication of stacked semiconductor devices
US20030015803A1 (en) * 2001-07-20 2003-01-23 Optosys Technologies Gmbh High-density multichip module and method for manufacturing the same
CN1441469A (zh) * 2002-02-25 2003-09-10 精工爱普生株式会社 半导体晶片、半导体装置和它们的制造方法、电路板和仪器
CN1484308A (zh) * 2002-09-17 2004-03-24 ���˻�˹�����̩�˹ɷ����޹�˾ 开口式多芯片堆叠封装体
CN102185090A (zh) * 2011-03-29 2011-09-14 晶科电子（广州）有限公司 一种采用cob封装的发光器件及其制造方法
CN202434508U (zh) * 2011-12-31 2012-09-12 刘胜 半导体芯片堆叠封装结构

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105280562A (zh) * 2014-05-27 2016-01-27 爱思开海力士有限公司 具有翼部分的挠性堆叠封装件
CN105280562B (zh) * 2014-05-27 2019-09-13 爱思开海力士有限公司 具有翼部分的挠性堆叠封装件
CN104538368A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种基于二次塑封技术的三维堆叠封装结构及其制备方法
CN109727913A (zh) * 2017-10-30 2019-05-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
CN110660891A (zh) * 2018-06-29 2020-01-07 合肥彩虹蓝光科技有限公司 一种倒装器件封装方法及结构
CN113629021A (zh) * 2021-08-09 2021-11-09 长江存储科技有限责任公司 半导体器件封装结构及其制造方法
WO2024016505A1 (zh) * 2022-07-22 2024-01-25 长鑫存储技术有限公司 半导体堆叠结构

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