CN103187322A - 充分成型的扇出 - Google Patents

充分成型的扇出 Download PDF

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CN103187322A
CN103187322A CN201210311793XA CN201210311793A CN103187322A CN 103187322 A CN103187322 A CN 103187322A CN 201210311793X A CN201210311793X A CN 201210311793XA CN 201210311793 A CN201210311793 A CN 201210311793A CN 103187322 A CN103187322 A CN 103187322A
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core unit
moulding compound
fan
transistor core
rdl
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CN103187322B (zh
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克里斯多佛·斯坎伦
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Decca Technology Inc
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Cypress Semiconductor Corp
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Abstract

本发明涉及充分成型的扇出。一种用于制造设备封装件的方法可包括构建与半导体管芯单元的表面耦合的隔板元件，其中所述隔板元件被配置成在所述半导体管芯单元和载体的表面之间产生空隙；以及将所述半导体管芯单元包封在模塑料内，其中所述包封包括将所述模塑料引入所述空隙中。

Description

充分成型的扇出
技术领域
本公开涉及半导体设备的板式封装的领域。
背景
在工业中获得接受的板式封装的一般实现是扇出型晶片级封装（WLP），其中多个管芯单元面向下放置在临时胶带载体上。使用压缩成型工艺用模塑料使多个管芯单元和临时胶带载体包覆成型。在成型后，去除胶带载体，让多个管芯单元的有源表面暴露在通常称为重组晶片的结构中。随后，晶片级芯片尺寸封装（WLCSP）组合结构在重组晶片的顶部上形成。球栅阵列（BGA）球连接到重组晶片，并且然后重组晶片用锯分割以形成单独的封装件。
附图简述
在附图的图中，作为例子而不是作为限制示出了本公开。
图1A示出了重组晶片的一个实施方式。
图1B-1D根据实施方式示出了布置在重组晶片中的多个封装件或模块的俯视图。
图2是示出了用于制造半导体封装件的工艺的实施方式的流程图。
图3示出了设备晶片的实施方式，扇入型RDL结构和导电接线柱构建在所述设备晶片上。
图4示出了设备晶片的实施方式，扇入型RDL结构和导电接线柱构建在所述设备晶片上。
图5根据实施方式示出了安装在载体元件上的管芯单元。
图6根据实施方式示出了包封在模塑料中的管芯单元。
图7根据实施方式示出了被包封在模塑料中并贴有锡球的管芯单元。
图8根据实施方式示出了被分割的设备封装件。
图9示出了球栅阵列（BGA）半导体设备封装件的实施方式。
图10示出了四方扁平无引脚（QFN）半导体设备封装件的实施方式。
详细描述
下面的描述阐述了许多具体细节，例如具体的***、部件、方法等的实例，以便提供对本发明的几个实施方式的好的理解。然而对于本领域技术人员很明显，可在没有这些具体细节的情况下实践本发明的至少一些实施方式。在其他实例中，众所周知的部件或方法未被详细描述或者以简单的框图形式出现，以便避免不必要地使本发明难理解。因此，所阐述的具体细节仅是示例性的。具体实现可从这些示例性细节变化且仍然被设想在本发明的精神和范围之内。
如本文所用的术语“在…上方”、“在…之间”和“在…上”是指一层相对于其他层的相对位置。沉积或布置在另一层上方或下方的一层可直接与该另一层接触或可具有一个或多个中介层。沉积或布置在几层之间的一层可直接与这几层接触或可具有一个或多个中介层。相反，在第二层“上”的第一层与该第二层接触。
本文公开的实施方式包括可应用于板式封装例如扇出型WLCSP的方法和结构。在以下描述中，关于单个管芯应用描述了具体实施方式。本发明的实施方式在多管芯模块或管芯与无源部件（例如，电容器、电感器或电阻器）和/或模块内的其他部件（例如，光学元件、连接器或其他电子部件）的某种组合中也可能是有用的。
在一个实施方式中，用于封装半导体设备的方法可包括通过用模塑料包围管芯单元的所有侧面来将半导体管芯单元包封在模塑料内。在一个实施方式中，可包封半导体管芯单元，使得管芯单元的所有六个侧面被模塑料覆盖。
在一个实施方式中，该工艺可包括在管芯单元和载体例如胶带载体之间产生空隙以允许模塑料流入管芯单元和载体之间的空隙中。在一个实施方式中，可通过在管芯单元上构建隔板元件然后将管芯单元置于载体上以使隔板将管芯单元与载体表面隔开来产生空隙。
在一个实施方式中，隔板元件还可用来将管芯单元的一个或多个接合焊盘电连接到半导体封装件的外表面。例如，隔板元件可包括可由被镀在半导体管芯单元的接合焊盘上的材料例如铜构建的一个或多个导电接线柱。
在一个实施方式中，焊盘在本文可被称作“接合焊盘”，不论是否有任何电线粘合到所述焊盘上。因此接合焊盘可以是可进行电连接以给集成在管芯单元内的电路提供信号或接收来自集成在管芯单元内的电路的信号的任何点。
因此，在一个实施方式中，半导体管芯单元可实质上被模塑料包封，使得管芯单元的大部分被模塑料包围，可能除了任何导电通路例如管芯单元和封装件外部之间的导电接线柱以外。
在一个实施方式中，扇入型再分布层（RDL）结构可构建在管芯单元上，且隔板元件例如导电接线柱可构建在扇入型RDL结构上。在一个实施方式中，扇入型RDL可用于在X-Y平面中移动连接点，使得连接点在X-Y平面中较接近于彼此而间隔开。相反，扇出型RDL可用来在X-Y平面中使连接点移动得隔得更远。这两种类型的RDL都可以在远离可包括管芯单元的接合焊盘的原始连接点的Z方向上建立新的连接点。
在一个实施方式中，在切割以将晶片分成单独的管芯单元之前，扇入型RDL结构可应用于原生设备晶片。在一个实施方式中，扇入型RDL结构提供了路径选择灵活性并减轻了对精确的管芯布置的需要。
在一个实施方式中，在将管芯单元和任何扇入型RDL结构和导电接线柱包封在模塑料中之后，扇出型RDL结构可在模塑料的表面上被建造并可与导电接线柱电连接。在一个实施方式中，RDL可应用于成型晶片，其在单独的管芯单元的分割之前可包括被单体模塑料包封的多个管芯单元。
在一个实施方式中，用于制造完全成型的封装件的工艺被简化并通过消除可用在其他扇出型WLP工艺中的面板后处理而降低了用于组装扇出型半导体封装件的成本。
在一个实施方式中，完全成型的封装件在所述封装件的下表面上在半导体管芯单元的边缘处没有形态不连续性。这可简化用于在封装件的底部上构建扇出型RDL结构的工艺。
此外，该工艺可减少由模塑料的不均匀分布造成的翘曲效应，以便可消除用于控制翘曲的步骤，例如研磨面板的背面。
在实施方式中，可组装和模塑多个设备单元以产生面板或网状晶片。设备单元可以是有源设备单元例如管芯，且还可以是无源设备单元例如集成无源网络或分立的无源设备单元例如电容器、电阻器或电感器。设备单元可以被预封装，虽然预封装不是需要的。根据本发明的实施方式，预封装件可包含单个或多个设备单元和其他部件。
本文描述的实施方式可用在任何板式封装应用中，包括单管芯应用、多管芯模块、管芯与模块内的无源部件的某种组合或设备单元与模块内的另一部件的一种组合。
根据扇出型晶片级封装（WLP）的一种实现，多个管芯单元可面向下布置在临时胶带载体上。然后可使用压缩成型工艺用环氧模塑料使载体包覆成型。在成型后，可去除胶带载体，让管芯的有源表面暴露。
图LA示出了面板102的实施方式，面板102包括使用包封材料L06例如环氧树脂包覆成型的多个设备单元L04。虽然图1A示出了圆形面板102，可利用可选的面板形式例如矩形或正方形。如图1A中所示，多个设备单元104的有源表面104可实质上与包封材料106齐平。在实施方式中，面板102可以是在本领域中做为在WLP技术中形成的重组晶片已知的东西，其中多个设备单元面向下布置在临时胶带载体上，然后使用压缩成型工艺用环氧模塑料包覆成型，然后去除临时胶带载体，让多个管芯单元的有源表面暴露。
随后，可在图1A所示的结构的顶部上形成组合结构并可分割设备单元以形成封装件或模块。例如，如图1B所示，面板可被分割成多个单管芯封装件150，每个封装件包括单个半导体管芯单元152。参考图1C，多个管芯单元152、154可安装在成型的面板内并被分割以形成多管芯封装件或模块150。参考图1D，单个管芯单元152或多个管芯单元152、154可安装在成型的面板内（添加无源设备156（例如电容器、电感器或电阻器）和/或其他部件158（例如光学元件、连接器或其他电子部件））并被分割以形成包括有源设备和无源设备和/或其他部件158的封装件或模块150。根据本发明的实施方式，设想了有源设备和无源设备与任选地封装件或模块内的其他部件的多种组合。因此，图1B-1D中所示的特定结构意指是例证性而非限制性的。
该工艺的实现可导致具有与芯片背面接触的模塑料的封装件，但是没有材料覆盖芯片的正面。作为结果，可使用大规模的后处理来减轻面板翘曲。这可包括在后模具固化期间约束面板，或研磨以在成型后去除芯片背面的模塑料。根据一种实现，在首先从面板背面去除模塑料之后，可在面板的背面涂敷层压的环氧树脂膜。
以这种方式构建的封装件在芯片的边缘接触模塑料的地方也可能具有形态不连续性，这可能是由于管芯在成型以及模子溢料期间被压缩到胶带中所致。因此，用于构建再分布层（RDL）的工艺可能需要设计成适应这种形态不连续性。
在一个实施方式中，芯片封装工艺的实施方式可通过在面板的成型期间同时包封芯片的所有侧面来处理这些问题，导致在芯片之上和之下的模塑料的相似的厚度。这提供了具有减少的翘曲的平衡结构，使得晶片背面的随后研磨是不需要的。在一个实施方式中，扇入型RDL结构可构建在原生晶片上，允许更灵活的路径选择。
在一个实施方式中，用于构建芯片封装件的方法可包括构建与半导体管芯单元的表面连接的隔板元件，然后将管芯单元置于载体上，使得隔板元件在管芯单元和载体之间产生空隙。在一个实施方式中，载体可以是胶带载体。
在将管芯单元置于载体上以后，可使用压缩成型工艺来将模塑料引入由隔板元件在管芯单元和载体表面之间产生的空隙中。模塑料可因此包封管芯单元的所有侧面，因为存在用于对在管芯单元的所有侧面——包括管芯单元面对载体的侧面——上填充的空间。
实质上将管芯单元包封在模塑料内的半导体设备封装制造工艺可进一步将管芯单元有源表面处的接合焊盘连接到半导体设备封装件外部处的导电材料。例如，隔板元件本身可由导电材料例如铜构造，导电材料被电镀在接合焊盘上或电镀在与接合焊盘连接的扇出型RDL结构上以产生一个或多个导电接线柱。在一个实施方式中，导电接线柱可电连接到作为扇出型RDL结构或锡球的一部分的导电材料。
图2根据实施方式示出了用于将半导体管芯封装件包封在模塑料中以产生半导体芯片封装件的工艺。在一个实施方式中，封装工艺200可在原生设备晶片上执行，许多半导体设备在该原生设备晶片上被构造。
工艺200开始于块201。在块201处，扇入型RDL结构可贴到原生设备晶片。例如，扇入型RDL结构可贴到原生设备晶片的单独的管芯单元。
图3示出了包括多个管芯单元305A、305B和305C的原生设备晶片301的实施方式。扇入型RDL 302可用来将管芯单元305A的接合焊盘304A电耦合到待电镀到扇入型RDL 302上的一个或多个导电接线柱303。在一个实施方式中，扇入型RDL结构可包括多个层，可选地，该结构可包括单个层。在一个实施方式中，扇入型RDL结构可包括一层聚合物306；可选地，聚合物306可从某些实施方式省略。从块201，工艺200在块203继续。
在块203处，在根据块201构建的任何扇入型RDL结构302上方构建了一个或多个隔板元件303。可选地，如果扇入型RDL结构302被省略，则隔板元件303可直接构建在半导体管芯单元的接合焊盘例如接合焊盘304A上。在任一情况中，隔板元件可包括可直接地或通过扇入型RDL302与管芯单元305的接合焊盘电连接的导电接线柱303。
在一个实施方式中，隔板元件303被设计成维持管芯单元与支撑所述管芯单元的载体表面之间的空隙。在一个实施方式中，隔板元件303是被设计成当完成时将管芯单元305A的接合焊盘304A连接到半导体设备封装件的外表面处的导电材料的导电接线柱。
在一个实施方式中，通过将铜电镀在之前构建的扇入型RDL迹线302上方至少50微米高的高度，来构建用作隔板元件且用于与接合焊盘电连接的导电接线柱303。从块203，工艺200在块205继续。
在块205处，原生设备晶片在包封到模塑料中之前被薄化并被切割成单独的管芯单元。因此，每个管芯单元与组成晶片的每个其他设备单元隔开。
图4根据实施方式示出了已变薄至其最终厚度的设备晶片301和与其他管芯单元305A和305B隔开的管芯单元305C。从块205，工艺200在块207继续。
图5根据实施方式示出了置于载体501上的管芯单元305C、305B和305A。在块207处，可使用牺牲性双面泡棉胶带502将半导体管芯单元305C、305B和305A布置在载体501上，有源侧面向下（接合焊盘面向下）。在一个实施方式中，之前构建的隔板元件303可产生将半导体管芯单元305A与载体501和泡棉胶带502分开的空隙503。在一个实施方式中，隔板元件303包括与管芯单元305A的至少一个接合焊盘电连接的至少一个导电接线柱。从块207，工艺200在块209继续。
图6根据实施方式示出了安装了管芯单元305C、305B和350A的载体501，其中管芯单元305C-A被模塑料502包封。在工艺200的块209处，可执行成型工艺以将管芯单元包封在膜塑料601内。在一个实施方式中，成型工艺是使模塑料被引入到由隔板元件303产生的空隙503中的压缩成型工艺。在一个实施方式中，管芯单元305A实质上被模塑料包封，以使模塑料存在于管芯单元的每一个侧面上。在一个实施方式中，连续的单体管芯化合物601可包围管芯单元305A。
在一个实施方式中，通过压缩成型工艺涂敷的模塑料601可分布模塑料，使得半导体管芯单元305A的顶部上的模塑料厚度小于在管芯单元305A的底部有源侧面下存在的模塑料厚度的三倍。从块209，工艺200在块211继续。
在块211处，从载体中取出成型面板。从块211，工艺200在块213继续。在块213处，可从成型面板的有源表面去除材料以暴露导电接线柱。例如，可对成型面板清洁或抛光以暴露成型面板表面处的接线柱。该工艺可去除可能散布在导电接线柱和泡棉胶带之间的任何模塑料。从块213，工艺在块215继续。
图7根据实施方式示出了具有扇出型RDL结构702和锡球701的、包括管芯单元305A、305B和305C的成型面板700。在块215处，扇出型再分布层（RDL）702可构建在成型面板700的有源表面上，且可与在块213暴露的导电接线柱303电连接。在一个实施方式中，扇出型RDL结构702可包括多个层；可选地，该结构可包括单个层。在一个实施方式中，扇出型RDL结构702可包括一层聚合物703；可选地，聚合物703可从某些实施方式省略。从块215，工艺200在块217继续。
在块217处，锡球701可贴到扇出型RDL结构702。在可省略扇出型RDL结构702的可选的实施方式中，锡球701可直接贴到在块213暴露的导电接线柱303。当正被制造的设备封装件是球栅阵列（BGA）封装件时，可使用锡球701的这种贴附。从块217，工艺200在块219继续。
在块219处，可将成型面板分割成单独的设备封装件。图8根据实施方式示出了已被分割成多个设备封装件801A、801B和801C的成型面板800的一个实施方式。在一个实施方式中，可使用锯来切割成型面板，将每个包封的管芯单元与面板中每个其他的包封管芯单元分开。
图9根据实施方式示出了半导体设备封装件900。在一个实施方式中，可根据如图2中所示的工艺200制造封装件900。
在一个实施方式中，封装件900包括半导体管芯单元901和与管芯单元901的接合焊盘903电耦合的多个导电接线柱902。在一个实施方式中，导电接线柱902可通过扇入型RDL结构905电连接到焊盘903，所述扇入型RDL结构可包括支撑RDL结构905的迹线的聚合物层908。
封装件的外部由实质上包围半导体管芯单元901的所有侧面的模塑料904形成。在一个实施方式中，导电接线柱902可与暴露在模塑料904外部的导电材料电耦合。如图9中所示，暴露在模塑料904外部的导电材料可以是锡球907，其中设备封装件900是BGA封装件。
在一个实施方式中，导电接线柱902可通过扇出型RDL结构906与锡球907电连接。在一个实施方式中，扇出型RDL结构906可包括聚合物层909以支撑导电接线柱902和锡球907所连接到的扇出型RDL结构906的导电迹线。
图10根据实施方式示出了具有连接盘栅格阵列的包封的四方扁平无引脚（QFN）封装件1000。在一个实施方式中，封装件1000包括半导体管芯单元1001和与管芯单元1001的接合焊盘1003电耦合的多个导电接线柱1002。在一个实施方式中，导电接线柱1002可通过扇入型RDL结构1005电连接到接合焊盘1003，扇入型RDL结构可包括支撑RDL结构1005的迹线的聚合物层1008。
封装件的外部由实质上包围半导体管芯单元1001的所有侧面的模塑料1004形成。在一个实施方式中，导电接线柱1002与在模塑料1004表面处或外部暴露的导电材料电耦合。如图10中所示，在模塑料1004外部暴露的导电材料可以是QFN设备封装件1000的连接盘1007。
在一个实施方式中，导电接线柱1002可通过扇出型RDL结构1006与连接盘1007电连接。在一个实施方式中，扇出型RDL结构1006可包括聚合物层1009以支撑导电接线柱1002和连接盘1007所连接到的扇出型RDL结构1006的导电迹线。
本文描述的本发明的实施方式包括多种操作。这些操作可由硬件部件、软件、固件或其组合执行。如本文所使用的，术语“耦合到”可以指直接地或通过一个或多个中介部件间接耦合。通过本文所述的多种总线提供的任何信号可与其他信号一起被时分多路传输并通过一个或多个常用总线来提供。另外，电路部件或块之间的相互连接可显示为总线或单个信号线。每个总线可以可选地是一条或多条单独的信号线，且每个单独的信号线可以可选地是总线。
某些实施方式可以被实现为可包括存储在计算机可读介质上的指令的计算机程序产品。这些指令可用来对通用或专用处理器编程以执行所述操作。计算机可读介质包括用于存储或传送以机器（例如计算机）可读的形式（例如，软件、处理应用）的信息的任何机制。计算机可读存储介质可包括但不限于磁存储介质（例如，软盘）；光学存储介质（例如，CD-ROM）；磁-光存储介质；只读存储器（ROM）；随机存取存储器（RAM）；可擦可编程存储器（例如，EPROM和EEPROM）；闪存或适合于存储电子指令的另一类型的介质。
另外，一些实施方式可在分布式计算环境中实践，其中计算机可读介质储存在一个以上的计算机***中和/或由一个以上的计算机***执行。另外，在计算机***之间传输的信息可穿过连接计算机***的传输介质被拉出或推出。
尽管本文以特定的顺序示出并描述了方法的操作，每个方法的操作顺序可改变，使得某些操作可按相反的顺序执行或使得某个操作可至少部分地与其他操作同时执行。在另一个实施方式中，不同操作的指令或子操作可以用间歇和/或交替的方式。
在前述说明书中，本发明已参考其具体示例性的实施方式被描述。然而，显然，可对其进行各种修改和改变而不偏离如所附权利要求书中阐述的本发明的更广的精神和范围。因此应在例证性意义而非限制性意义上考虑说明书和附图。

Claims (20)

1.一种方法，包括：
构建与半导体管芯单元的表面耦合的隔板元件，其中所述隔板元件被配置成在所述半导体管芯单元和载体的表面之间产生空隙；以及
将所述半导体管芯单元包封在模塑料内，其中所述包封包括将所述模塑料引入所述空隙中。
2.根据权利要求1所述的方法，还包括在将所述模塑料引入所述空隙中之前将所述隔板元件附接到所述载体。
3.根据权利要求1所述的方法，还包括：
在包封所述半导体管芯单元之前，使半导体晶片变薄，所述半导体管芯单元构建在所述半导体晶片上；以及
切割所述半导体晶片以将所述半导体管芯单元与多个其他半导体管芯单元分隔开。
4.根据权利要求1所述的方法，其中将所述半导体管芯包封在所述模塑料内还包括执行压缩成型工艺。
5.根据权利要求1所述的方法，其中在所述半导体管芯单元的顶部上的所述模塑料的第一厚度小于在所述半导体管芯单元的底部下面的所述模塑料的第二厚度的三倍。
6.根据权利要求1所述的方法，其中所述隔板元件包括与所述半导体管芯单元的至少一个接合焊盘电耦合的至少一个导电接线柱。
7.根据权利要求6所述的方法，还包括在所述模塑料的外表面处暴露所述至少一个导电接线柱。
8.根据权利要求6所述的方法，还包括在将所述半导体管芯单元包封在所述模塑料中之前构建与所述半导体管芯单元的多个接合焊盘电耦合的扇入型再分布层（RDL）结构，其中所述至少一个导电接线柱被电镀到所述扇入型RDL结构上。
9.根据权利要求8所述的方法，还包括在所述模塑料的表面上构建扇出型再分布层（RDL）结构，其中所述扇出型RDL与所述至少一个导电接线柱电耦合。
10.根据权利要求6所述的方法，还包括将多个锡球贴到所述扇出型RDL结构以产生球栅阵列（BGA）封装件。
11.根据权利要求1所述的方法，还包括在将所述半导体管芯单元包封在所述模塑料中后，将所包封的半导体管芯单元与多个其他包封的半导体管芯单元分隔开。
12.一种半导体设备封装件，包括：
半导体管芯单元；
多个导电接线柱，其与所述半导体管芯单元的有源表面上的一个或多个接合焊盘电耦合；以及
模塑料，其实质上覆盖所述半导体管芯单元的有源表面，其中所述导电接线柱通过再分布层（RDL）与在所述模塑料外部暴露的导电材料电耦合。
13.根据权利要求12所述的半导体设备封装件，其中所述再分布层（RDL）结构是扇出型RDL并与所述多个导电接线柱电耦合。
14.根据权利要求12所述的半导体设备封装件，其中在所述模塑料外部暴露的所述导电材料包括与所述扇出型RDL结构电耦合的多个锡球，其中所述半导体设备封装件是球栅阵列（BGA）封装件。
15.根据权利要求12所述的半导体设备封装件，还包括将一个或多个接合焊盘连接到所述多个导电接线柱的扇入型再分布层（RDL）。
16.一种方法，包括：
通过将半导体管芯单元实质上包封在模塑料内来构建半导体设备封装件；以及
构建将所述半导体管芯单元的接合焊盘电连接到所述半导体设备封装件的外表面处的导电材料的再分布层（RDL）结构。
17.根据权利要求16所述的方法，其中将所述半导体管芯单元包封在所述模塑料内包括：
在所述半导体管芯单元和支撑所述半导体管芯单元的载体的表面之间产生空隙；以及
用所述模塑料填充所述空隙。
18.根据权利要求16所述的方法，还包括：
构建与所述半导体管芯单元的所述接合焊盘电耦合的多个导电接线柱；
将所述导电接线柱附接到载体的表面，其中所述多个导电接线柱被配置成维持所述半导体管芯单元和所述载体的所述表面之间的空隙。
19.根据权利要求18所述的方法，还包括在所述半导体管芯单元的表面上构建扇入型再分布层（RDL）结构，其中所述扇入型RDL被配置成将所述接合焊盘与所述多个导电接线柱电耦合。
20.根据权利要求18所述的方法，还包括在将所述半导体管芯单元实质上包封在所述模塑料中后，将所述RDL结构与所述多个导电接线柱电耦合，其中所述RDL结构是扇出型RDL结构。
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