US20230041760A1 - Semiconductor devices with package-level compartmental shielding and associated systems and methods - Google Patents
Semiconductor devices with package-level compartmental shielding and associated systems and methods Download PDFInfo
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- US20230041760A1 US20230041760A1 US17/969,620 US202217969620A US2023041760A1 US 20230041760 A1 US20230041760 A1 US 20230041760A1 US 202217969620 A US202217969620 A US 202217969620A US 2023041760 A1 US2023041760 A1 US 2023041760A1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
Definitions
- the present disclosure is generally directed to semiconductor devices, systems and methods, and in several embodiments to multifunctional semiconductor packages having package-level compartmental shielding.
- Microelectronic devices such as memory devices, microprocessors, and light emitting diodes, typically include one or more semiconductor dies mounted to a substrate and encased in a protective covering.
- the semiconductor dies are packaged to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines.
- Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).
- the semiconductor dies include functional features, such as memory cells, processor circuits, interconnecting circuitry, etc. that may require shielding from other components.
- multiple semiconductor components are packaged together in a multifunctional package, or a System in Package (SiP), which generally refers to a semiconductor package containing different types of semiconductor devices, such as differ types of dies with different functionality, or other components packaged with semiconductor dies.
- SiP System in Package
- certain components may require shielding from other components within the same package.
- one or more conductive shields are integrated within the protective covering to isolate components and compartmentalize the SiP.
- conventional SiP shielding arrangements multiple manufacturing process steps are required to integrate the shield.
- FIG. 1 is an enlarged cross-sectional view showing a semiconductor device configured in accordance with existing technology before packaging.
- FIGS. 2 A and 2 B are enlarged cross-sectional side views showing a process of molding a material on the semiconductor device of FIG. 1 .
- FIG. 3 is an enlarged cross-sectional view showing the semiconductor device of FIG. 1 after molding the material on the semiconductor device of FIG. 1 .
- FIGS. 4 A and 4 B are enlarged cross-sectional side views showing stages of forming a compartmental shield in the packaging material on the device of FIG. 1 .
- FIG. 5 an enlarged cross-sectional view showing the semiconductor device of FIG. 1 with a compartmental shield and a conformal shield.
- FIG. 6 is a schematic view of a system that includes a semiconductor device configured in accordance with embodiments of the present technology.
- semiconductor device generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, diodes, and other devices with semiconductor materials. Furthermore, the term “semiconductor device” can refer to a finished device or assembly, or other structures at various stages of processing before becoming a finished device. In some embodiments, an individual semiconductor device may be “packaged” and include a molding material encasing the components and electrical connections in the device. In some embodiments, multiple semiconductor components are packaged together in a multifunctional package, such as a System in Package (SiP). SiPs generally contain multiple semiconductor devices, such as multiple dies with the same or different functionality. SiPs can also include other components packaged with semiconductor dies, or any combination of components.
- SiP System in Package
- the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a wafer-level substrate or to a singulated, die-level substrate, or another die for die-stacking applications.
- a person having ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer-level or at the die level.
- structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
- certain components may require shielding from other components within the same multifunctional package.
- one or more shields are integrated within the protective covering between components to compartmentalize the SiP into shielded areas.
- multiple manufacturing steps are generally required to integrate the shield to the SiP.
- conventional SiP shielding integration involves: (a) mounting the semiconductor die package and other components to a substrate using surface-mount technology (SMT); (b) molding a molding material over the mounted components with a mold chase configured to form the shape of the package; (c) cutting a trench (e.g., with a laser) in the solid molding material to create a void for a shield; and (d) forming a shield made of conductive material in the trench to form the package-level shielded compartment.
- SMT surface-mount technology
- a multifunctional package may include a compartmental shield to prevent interference between semiconductor components within the multifunctional package.
- the compartmental shield may be arranged between the semiconductor components of an SiP in a trough or trench in the package molding.
- the package molding may be formed using a mold chase having a protrusion configured to form the trench during the molding process.
- the protrusion may be a trench plate or panel extending from a surface of the mold chase between the components of the SiP requiring shielding.
- the trench plate maintains a gap in the molding material for the shield.
- the package molding includes a trench between the molded structures that is formed by the trench plate.
- a shielding material e.g., a conductive paste
- a conformal shield is added over the package molding and the compartmental shield to further prevent interference with the components of the SiP.
- the conformal shield is formed using suitable processes, such as sputter deposition, plating, etc.
- FIG. 1 is a cross-sectional side view of a multifunctional semiconductor system in package 100 (“SiP 100 ”) before being packaged in accordance with embodiments of the present technology.
- the SiP 100 includes a first die 122 electrically coupled to the substrate 130 through interconnects 126 , a second die 124 electrically coupled to the substrate 130 through interconnects 128 , and first antenna and second antennas 132 and 134 electrically coupled to the substrate 130 .
- the SiP 100 may include several combinations of components mounted to a substrate 130 , and thus the configuration of the SiP 100 in FIG. 1 is exemplary and should not be construed as limiting the present technology to the illustrated configuration.
- the components of the SiP 100 are arranged such that shielding is desired between the first die 122 and the combination of the second die 124 , the first antenna 132 , and the second antenna 134 .
- the shielding may be placed between any component of the SiP, or multiple compartmental shields may be placed between components of the SiP as required by design.
- FIG. 1 also shows a mold chase 110 shaped to form molded structures that encase the components of the SiP 100 such that a compartmental shield can be formed in a trench between molded structures.
- the mold chase 110 is generally sized such that the packaging material adequately covers the components of the SiP 100 and provide a thickness needed for protection while being within dimension specifications of the SiP 100 .
- the mold chase 110 may include a top panel 112 , a sidewall 113 having first and second side panels 114 a and 114 b depending from the top panel 112 , and a trench plate 116 depending from the top panel 112 at a location between the first and second side panels 114 a and 114 b .
- the mold chase 110 has a first cavity 117 a defined by the first side panel 114 a , the trench plate 116 , and a portion of the top panel 112 .
- the mold chase 110 also has a second cavity 117 b defined by the second side panel 114 b , the trench plate 116 , and another portion of the top panel 112 .
- the mold chase 110 can further include one or more sprues 118 (identified individually as 118 a and 118 b ) through which molding material can be injected into or air can flow out from the first and/or second cavities 117 a and 117 b .
- the mold chase 110 can have one or more passageways 119 in the trench plate 116 through which the molding material can flow between the first and second cavities 117 a and 117 b.
- the mold chase 110 is configured to create a first molded structure in the first cavity 117 a , a second molded structure in the second cavity 117 b , and a trench between the molded structures after the molding material cures and the mold chase 110 is removed from the SiP 100 .
- the trench plate 116 may extend from a surface of the mold chase 110 to contact the substrate 130 when the mold chase 110 is in position for molding (see, e.g., FIG. 2 A ). When the trench plate 116 contacts the substrate 130 during molding, the molding material can flow between the first and second cavities 117 a and 117 b via the passageways 119 . In embodiments where the trench plate 116 extends only partially toward the substrate 130 , the passageways 119 may be omitted as the molding material can flow under the trench plate 116 .
- FIG. 2 A shows an intermediate stage of injecting a molding material 140 into the second cavity 117 b via sprue 118 b to cover the second die 124 , the interconnects 128 , and the first and second antennas 132 and 134 .
- the molding material 140 reaches the height of the passageways 119 in the trench plate 116 , the molding material 140 flows into the first cavity 117 a to cover the first die 122 and the interconnects 126 .
- Air in the molding chase 110 can flow out through sprue 118 b .
- the molding material 140 is generally injected into mold chase 110 until the first and second cavities 117 a and 11 b are full or at least nearly full.
- FIG. 2 B shows the SiP 100 with the first and second cavities 102 and 104 full of molding material 140 forming the molded structures over the semiconductor components.
- the molding material 140 may be a resin, epoxy resin, silicone-based material, polyimide, and/or any other suitable resin. Once deposited, the molding material 140 can be cured by UV light, chemical hardeners, heat, or other suitable curing methods. The molding material 140 can be shaped to expose one or more conductive pads, or a portion of the molding material can be removed with a tool (e.g., a grinder) to expose certain features of the SiP 100 . In general, the molding material 140 may encapsulate the components of the SiP 100 such the components are sealed within the molding material 140 after curing. The one or more sprues 118 may cause artifacts in the molding material 140 after curing.
- a molding chase 110 having a trench plate 116 it may be possible to identify whether aspects of the present technology (e.g., a molding chase 110 having a trench plate 116 ) were used to manufacture an SiP 100 , where the artifacts from the sprues 118 would be present in the molding material 140 on either side of the trench plate 116 after curing.
- FIG. 3 shows the process after at least partially curing the molding material 140 ( FIG. 2 B ) and the mold chase 110 has been removed from the SiP 100 to form a first molded structure 141 a , a second molded structure 141 b , and an open trench 142 between the first and second molded structures 141 a and 141 b that was created by the trench plate 116 .
- the open trench 142 is between components of the SiP 100 where compartmental shielding is desired.
- the trench plate 116 creates the open trench 142 and the first and second molded structures 141 a and 141 b without an additional step of cutting the molding material using a laser, cutting wheel, or other cutting tool.
- the compartmental shield is an electromagnetic interference (EMI) shield arranged between the semiconductor die and another component in the SiP, such as an antenna structure.
- the EMI shield can prevent interference from electromagnetic radiation generated by the antenna structure and/or shield at least the antenna structure from interface generated by the semiconductor die.
- the semiconductor device includes a package molding over at least a portion of the antenna, die, etc.
- a conformal shield may be placed over the package molding and the compartmental shield to isolate a package from other packages.
- FIGS. 4 A and 4 B show a process of forming of a compartmental shield 154 ( FIG. 4 B ) in the open trench 142 .
- a dispensing head 150 dispenses conductive material 152 into the open trench 142 .
- the conductive material 152 may be a conductive paste, a molten metal, or any other suitable material to shield interference between the components of the SiP 100 .
- the conductive material 152 may be dispensed until the open trench 142 is full and the compartmental shield 154 is formed, as shown in FIG. 4 B .
- the open trench 142 does not need to be filled completely with the conductive material 152 .
- the height of compartmental shield 154 should be sufficient to shield the components encased by the first molded structure 141 a from the components encased by the second molded structure 141 b .
- depth of the SiP 100 is not shown in the figures (i.e., the dimension perpendicular to the page), the compartmental shield 154 may extend the full depth of the package, or partially along the depth of the package. In other embodiments, the compartmental shield 154 is of any geometric or arcuate shape along the depth of the SiP 100 .
- FIG. 5 shows an embodiment in which the Sip 100 include an optional outer conformal shield 136 in addition to the compartmental shield 154 .
- the conformal shield 136 may be disposed on the molding material 140 to cover the first and second molded structures 141 a and 141 b to further shield the components of the package.
- the conformal shield 136 may be formed using any suitable method, such as sputter deposition, chemical vapor deposition, plating, etc.
- the conformal shield 136 may cover the entire package or only a portion of the package.
- FIG. 6 is a block diagram illustrating a system that incorporates a semiconductor device in accordance with embodiments of the present technology. Any one of the semiconductor devices having the features described above with reference to FIGS. 1 - 5 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 600 shown schematically in FIG. 6 .
- the system 600 can include a processor 602 , a memory 604 (e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices 606 , and/or other subsystems or components 608 .
- the semiconductor assemblies, devices, and device packages described above with reference to FIGS. 1 - 5 can be included in any of the elements shown in FIG. 6 .
- the resulting system 600 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions.
- representative examples of the system 600 include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers.
- Additional representative examples of the system 600 include lights, cameras, vehicles, etc.
- the system 600 can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network.
- the components of the system 600 can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.
- the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures.
- “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature.
- These terms should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, left/right, and distal/proximate can be interchanged depending on the orientation.
- identical reference numbers are used to identify similar or analogous components or features throughout this disclosure, but the use of the same reference number does not imply that the features should be construed to be identical. Indeed, in many examples described herein, identically numbered features have a plurality of embodiments that are distinct in structure and/or function from each other. Furthermore, the same shading may be used to indicate materials in cross section that can be compositionally similar, but the use of the same shading does not imply that the materials should be construed to be identical unless specifically noted herein.
- the foregoing disclosure may also reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the new technology. Also, in this regard, the present disclosure may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc.
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Abstract
A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.
Description
- This application is a division of U.S. patent application Ser. No. 16/681,214, filed Nov. 12, 2019, which is incorporated herein by reference in its entirety.
- The present disclosure is generally directed to semiconductor devices, systems and methods, and in several embodiments to multifunctional semiconductor packages having package-level compartmental shielding.
- Microelectronic devices, such as memory devices, microprocessors, and light emitting diodes, typically include one or more semiconductor dies mounted to a substrate and encased in a protective covering. The semiconductor dies are packaged to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines. Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact). The semiconductor dies include functional features, such as memory cells, processor circuits, interconnecting circuitry, etc. that may require shielding from other components.
- In some examples, multiple semiconductor components are packaged together in a multifunctional package, or a System in Package (SiP), which generally refers to a semiconductor package containing different types of semiconductor devices, such as differ types of dies with different functionality, or other components packaged with semiconductor dies. In SiP arrangements, certain components may require shielding from other components within the same package. In such package-level shielding, one or more conductive shields are integrated within the protective covering to isolate components and compartmentalize the SiP. In conventional SiP shielding arrangements, multiple manufacturing process steps are required to integrate the shield.
-
FIG. 1 is an enlarged cross-sectional view showing a semiconductor device configured in accordance with existing technology before packaging. -
FIGS. 2A and 2B are enlarged cross-sectional side views showing a process of molding a material on the semiconductor device ofFIG. 1 . -
FIG. 3 is an enlarged cross-sectional view showing the semiconductor device ofFIG. 1 after molding the material on the semiconductor device ofFIG. 1 . -
FIGS. 4A and 4B are enlarged cross-sectional side views showing stages of forming a compartmental shield in the packaging material on the device ofFIG. 1 . -
FIG. 5 an enlarged cross-sectional view showing the semiconductor device ofFIG. 1 with a compartmental shield and a conformal shield. -
FIG. 6 is a schematic view of a system that includes a semiconductor device configured in accordance with embodiments of the present technology. - The technology disclosed herein relates to semiconductor devices, systems with semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, diodes, and other devices with semiconductor materials. Furthermore, the term “semiconductor device” can refer to a finished device or assembly, or other structures at various stages of processing before becoming a finished device. In some embodiments, an individual semiconductor device may be “packaged” and include a molding material encasing the components and electrical connections in the device. In some embodiments, multiple semiconductor components are packaged together in a multifunctional package, such as a System in Package (SiP). SiPs generally contain multiple semiconductor devices, such as multiple dies with the same or different functionality. SiPs can also include other components packaged with semiconductor dies, or any combination of components.
- Depending upon the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a wafer-level substrate or to a singulated, die-level substrate, or another die for die-stacking applications. A person having ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer-level or at the die level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
- In SiP arrangements, certain components may require shielding from other components within the same multifunctional package. In such package-level shielding configurations, one or more shields are integrated within the protective covering between components to compartmentalize the SiP into shielded areas. In conventional SiP shielding processes, multiple manufacturing steps are generally required to integrate the shield to the SiP. For example, conventional SiP shielding integration involves: (a) mounting the semiconductor die package and other components to a substrate using surface-mount technology (SMT); (b) molding a molding material over the mounted components with a mold chase configured to form the shape of the package; (c) cutting a trench (e.g., with a laser) in the solid molding material to create a void for a shield; and (d) forming a shield made of conductive material in the trench to form the package-level shielded compartment.
- A multifunctional package may include a compartmental shield to prevent interference between semiconductor components within the multifunctional package. The compartmental shield may be arranged between the semiconductor components of an SiP in a trough or trench in the package molding. In embodiments of the present technology, the package molding may be formed using a mold chase having a protrusion configured to form the trench during the molding process. The protrusion may be a trench plate or panel extending from a surface of the mold chase between the components of the SiP requiring shielding. As the molding material fills the cavities in the mold chase and covers the components of the SiP, the trench plate maintains a gap in the molding material for the shield. When the mold chase is removed from the multifunctional package, the package molding includes a trench between the molded structures that is formed by the trench plate. A shielding material (e.g., a conductive paste) is the deposited in the trench to form a compartmental shield. In some embodiments, a conformal shield is added over the package molding and the compartmental shield to further prevent interference with the components of the SiP. The conformal shield is formed using suitable processes, such as sputter deposition, plating, etc.
-
FIG. 1 is a cross-sectional side view of a multifunctional semiconductor system in package 100 (“SiP 100”) before being packaged in accordance with embodiments of the present technology. In the illustrated embodiment, theSiP 100 includes afirst die 122 electrically coupled to thesubstrate 130 throughinterconnects 126, asecond die 124 electrically coupled to thesubstrate 130 throughinterconnects 128, and first antenna andsecond antennas substrate 130. The SiP 100 may include several combinations of components mounted to asubstrate 130, and thus the configuration of theSiP 100 inFIG. 1 is exemplary and should not be construed as limiting the present technology to the illustrated configuration. In this example, the components of theSiP 100 are arranged such that shielding is desired between thefirst die 122 and the combination of thesecond die 124, thefirst antenna 132, and thesecond antenna 134. In other embodiments, the shielding may be placed between any component of the SiP, or multiple compartmental shields may be placed between components of the SiP as required by design. -
FIG. 1 also shows amold chase 110 shaped to form molded structures that encase the components of theSiP 100 such that a compartmental shield can be formed in a trench between molded structures. Themold chase 110 is generally sized such that the packaging material adequately covers the components of theSiP 100 and provide a thickness needed for protection while being within dimension specifications of theSiP 100. Themold chase 110 may include atop panel 112, a sidewall 113 having first andsecond side panels top panel 112, and atrench plate 116 depending from thetop panel 112 at a location between the first andsecond side panels mold chase 110 has afirst cavity 117 a defined by thefirst side panel 114 a, thetrench plate 116, and a portion of thetop panel 112. Themold chase 110 also has asecond cavity 117 b defined by thesecond side panel 114 b, thetrench plate 116, and another portion of thetop panel 112. Themold chase 110 can further include one or more sprues 118 (identified individually as 118 a and 118 b) through which molding material can be injected into or air can flow out from the first and/orsecond cavities mold chase 110 can have one ormore passageways 119 in thetrench plate 116 through which the molding material can flow between the first andsecond cavities - The
mold chase 110 is configured to create a first molded structure in thefirst cavity 117 a, a second molded structure in thesecond cavity 117 b, and a trench between the molded structures after the molding material cures and themold chase 110 is removed from theSiP 100. Thetrench plate 116 may extend from a surface of themold chase 110 to contact thesubstrate 130 when themold chase 110 is in position for molding (see, e.g.,FIG. 2A ). When thetrench plate 116 contacts thesubstrate 130 during molding, the molding material can flow between the first andsecond cavities passageways 119. In embodiments where thetrench plate 116 extends only partially toward thesubstrate 130, thepassageways 119 may be omitted as the molding material can flow under thetrench plate 116. -
FIG. 2A shows an intermediate stage of injecting amolding material 140 into thesecond cavity 117 b viasprue 118 b to cover thesecond die 124, theinterconnects 128, and the first andsecond antennas molding material 140 reaches the height of thepassageways 119 in thetrench plate 116, themolding material 140 flows into thefirst cavity 117 a to cover thefirst die 122 and theinterconnects 126. Air in themolding chase 110 can flow out throughsprue 118 b. Themolding material 140 is generally injected intomold chase 110 until the first andsecond cavities 117 a and 11 b are full or at least nearly full.FIG. 2B shows theSiP 100 with the first and second cavities 102 and 104 full ofmolding material 140 forming the molded structures over the semiconductor components. - The
molding material 140 may be a resin, epoxy resin, silicone-based material, polyimide, and/or any other suitable resin. Once deposited, themolding material 140 can be cured by UV light, chemical hardeners, heat, or other suitable curing methods. Themolding material 140 can be shaped to expose one or more conductive pads, or a portion of the molding material can be removed with a tool (e.g., a grinder) to expose certain features of theSiP 100. In general, themolding material 140 may encapsulate the components of theSiP 100 such the components are sealed within themolding material 140 after curing. The one or more sprues 118 may cause artifacts in themolding material 140 after curing. As such, it may be possible to identify whether aspects of the present technology (e.g., amolding chase 110 having a trench plate 116) were used to manufacture anSiP 100, where the artifacts from the sprues 118 would be present in themolding material 140 on either side of thetrench plate 116 after curing. -
FIG. 3 shows the process after at least partially curing the molding material 140 (FIG. 2B ) and themold chase 110 has been removed from theSiP 100 to form a first moldedstructure 141 a, a second moldedstructure 141 b, and anopen trench 142 between the first and second moldedstructures trench plate 116. Theopen trench 142 is between components of theSiP 100 where compartmental shielding is desired. In contrast to compartmental shielding processes of conventional technology, thetrench plate 116 creates theopen trench 142 and the first and second moldedstructures - In some embodiments, the compartmental shield is an electromagnetic interference (EMI) shield arranged between the semiconductor die and another component in the SiP, such as an antenna structure. The EMI shield can prevent interference from electromagnetic radiation generated by the antenna structure and/or shield at least the antenna structure from interface generated by the semiconductor die. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, die, etc. A conformal shield may be placed over the package molding and the compartmental shield to isolate a package from other packages.
-
FIGS. 4A and 4B show a process of forming of a compartmental shield 154 (FIG. 4B ) in theopen trench 142. As shown inFIG. 4A , a dispensinghead 150 dispensesconductive material 152 into theopen trench 142. Theconductive material 152 may be a conductive paste, a molten metal, or any other suitable material to shield interference between the components of theSiP 100. Theconductive material 152 may be dispensed until theopen trench 142 is full and thecompartmental shield 154 is formed, as shown inFIG. 4B . Theopen trench 142 does not need to be filled completely with theconductive material 152. In general, the height ofcompartmental shield 154 should be sufficient to shield the components encased by the first moldedstructure 141 a from the components encased by the second moldedstructure 141 b. Although depth of theSiP 100 is not shown in the figures (i.e., the dimension perpendicular to the page), thecompartmental shield 154 may extend the full depth of the package, or partially along the depth of the package. In other embodiments, thecompartmental shield 154 is of any geometric or arcuate shape along the depth of theSiP 100. -
FIG. 5 shows an embodiment in which theSip 100 include an optional outerconformal shield 136 in addition to thecompartmental shield 154. Theconformal shield 136 may be disposed on themolding material 140 to cover the first and second moldedstructures conformal shield 136 may be formed using any suitable method, such as sputter deposition, chemical vapor deposition, plating, etc. Theconformal shield 136 may cover the entire package or only a portion of the package. -
FIG. 6 is a block diagram illustrating a system that incorporates a semiconductor device in accordance with embodiments of the present technology. Any one of the semiconductor devices having the features described above with reference toFIGS. 1-5 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which issystem 600 shown schematically inFIG. 6 . Thesystem 600 can include aprocessor 602, a memory 604 (e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices 606, and/or other subsystems orcomponents 608. The semiconductor assemblies, devices, and device packages described above with reference toFIGS. 1-5 can be included in any of the elements shown inFIG. 6 . The resultingsystem 600 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of thesystem 600 include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of thesystem 600 include lights, cameras, vehicles, etc. In these and other examples, thesystem 600 can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of thesystem 600 can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media. - Although many of the foregoing embodiments are described with respect to semiconductor devices, systems, and methods with compartmental shielding, other applications and other embodiments in addition to those described herein are within the scope of the present technology. Further, embodiments of the present technology can have different configurations, components, and/or procedures than those shown or described herein, and these and other embodiments can be used without several of the configurations, components, and/or procedures shown or described herein without deviating from the present technology.
- As used in the foregoing description, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, left/right, and distal/proximate can be interchanged depending on the orientation. Moreover, for ease of reference, identical reference numbers are used to identify similar or analogous components or features throughout this disclosure, but the use of the same reference number does not imply that the features should be construed to be identical. Indeed, in many examples described herein, identically numbered features have a plurality of embodiments that are distinct in structure and/or function from each other. Furthermore, the same shading may be used to indicate materials in cross section that can be compositionally similar, but the use of the same shading does not imply that the materials should be construed to be identical unless specifically noted herein.
- The foregoing disclosure may also reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the new technology. Also, in this regard, the present disclosure may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. For the purposes of the present disclosure, the phrase “at least one of A, B, and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed.
- From the foregoing, it will be appreciated that specific embodiments of the new technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the present disclosure. Accordingly, the invention is not limited except as by the appended claims. Furthermore, certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the present disclosure. Accordingly, the present disclosure and associated technology can encompass other embodiments not expressly shown or described herein.
Claims (6)
1. A mold chase for packaging a compartmentally shielded multifunctional semiconductor, the mold chase comprising:
a top panel having an inlet sprue through which a molding material can flow;
a sidewall depending from a perimeter of the top panel and configured to contact a substrate of the multifunctional semiconductor when the mold chase is in a molding position; and
a trench plate projecting from the top panel at a position inward of the side panel, the trench plate configured to at least partially extend toward the substrate between a first component and a second component of the multifunctional semiconductor when the mold chase is in a molding position,
wherein the top panel, the side panel, and the trench plate together form a first cavity and a second cavity configured to receive the molding material.
2. The mold chase of claim 1 , wherein the trench plate projects from the top panel to contact the substrate when the mold chase is in a molding position, the trench plate separating the first cavity from the second cavity.
3. The mold chase of claim 2 , wherein the trench plate has a passageway to fluidly couple the first cavity and the second cavity to flow the molding material therebetween.
4. The mold chase of claim 1 , wherein the trench plate creates an open trench when the mold chase is removed from cured molding material.
5. The mold chase of claim 4 , wherein the open trench is between the first and second components of the multifunctional semiconductor and configured to receive a compartmental shield therein.
6. The mold chase of claim 1 , wherein the molding material is selected from the group consisting of a resin, an epoxy resin, a silicone-based material, a polyimide, and combinations thereof.
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US10091918B2 (en) * | 2012-12-11 | 2018-10-02 | Qualcomm Incorporated | Methods and apparatus for conformal shielding |
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US20170118877A1 (en) * | 2015-10-22 | 2017-04-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Circuit package with bond wires to provide internal shielding between electronic components |
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US20170179041A1 (en) * | 2015-12-22 | 2017-06-22 | Intel Corporation | Semiconductor package with trenched molding-based electromagnetic interference shielding |
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