CN105633053A - 基板结构及其制法 - Google Patents

基板结构及其制法 Download PDF

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Publication number
CN105633053A
CN105633053A CN201410612179.6A CN201410612179A CN105633053A CN 105633053 A CN105633053 A CN 105633053A CN 201410612179 A CN201410612179 A CN 201410612179A CN 105633053 A CN105633053 A CN 105633053A
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insulating barrier
board structure
line layer
bearing part
wiring region
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CN105633053B (zh
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张辰安
孙崧桓
吴建宏
陈以婕
廖文楷
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种基板结构及其制法，基板结构，包括：定义有布线区的承载件、设于该布线区面上的第一绝缘层、设于该布线区上的该第一绝缘层上的一线路层、以及设于该布线区上的第二绝缘层，藉由缩小该第一与第二绝缘层的布设面积，以减少该承载件与该绝缘层间的接触面积及热膨胀系数差异，使该基板结构不易发生翘曲。

Description

基板结构及其制法
技术领域
本发明有关一种基板结构，尤指一种提升可靠度的基板结构及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于晶片封装领域的技术，例如晶片尺寸构装(ChipScalePackage,CSP)、晶片直接贴附封装(DirectChipAttached,DCA)或多晶片模组封装(Multi－ChipModule,MCM)等覆晶型态的封装模组、或将晶片立体堆迭化整合为三维积体电路(3DIC)晶片堆迭技术等。
目前现有3D晶片堆迭的半导体封装件，其提供一硅中介板(ThroughSiliconinterposer,TSI)，该硅中介板具有贯穿的多个导电硅穿孔(Through-siliconvia,TSV)，且该该板的一侧具有一线路重布层(Redistributionlayer，简称RDL)，以于该线路重布层上电性结合间距较小的半导体晶片的电极垫，再于该板的另一侧上电性结合间距较大的封装基板的焊垫。
如图1所示，现有硅中介板的基板结构1包括一承载件10、设于该承载件10全部表面上的第一绝缘层11、设于该第一绝缘层11上的一线路层13、设于该线路层13与该第一绝缘层11上并外露部分该线路层13的第二绝缘层12、以及设于该线路层13上的导电元件14。
图1A至图1E为图1的制法的上视示意图。
如图1及图1A所示，提供一如硅晶圆的承载件10，且于该承载件10上设有电性连接垫101。
如图1B所示，形成一第一绝缘层11于该承载件10的全部表面上，且该第一绝缘层11外露该电性连接垫101的部分表面。
如图1C所示，形成一如RDL的线路层13于该第一绝缘层11上，且该线路层13电性连接该电性连接垫101。
如图1D所示，形成一第二绝缘层12于该线路层13与该第一绝缘层11上，且该第二绝缘层12外露该线路层13的部分表面。
如图1E所示，先形成凸块底下金属层(Underbumpmetallurgy，简称UBM)15于该线路层13的外露表面上，再形成如焊锡凸块的导电元件14于该凸块底下金属层15上。
然而，现有基板结构1的制法中，该承载件10与该第一绝缘层11两者的接触面积极大，且两者的热膨胀系数(Coefficientofthermalexpansion，简称CTE)差异极大，所以于进行热处理制程期间(thermalcycle)，该基板结构1难以均匀释放热应力(thermalstress)，导致该基板结构1容易发生翘曲(warpage)的问题，且该导电元件14的应力可靠性(reliability)不佳，因而造成难以载运该基板结构1或无法进行后续制程。
因此，如何克服现有技术的种种缺失，实为一重要课题。
发明内容
为克服现有技术的种种缺失，本发明提供一种基板结构及其制法，使该基板结构不易发生翘曲。
本发明的基板结构，包括：一承载件，其定义有至少一布线区，其中，该布线区位于该承载件的部分表面，且该布线区包含接点处；第一绝缘层，其设于该布线区上；一线路层，其设于该布线区上的该第一绝缘层上；以及第二绝缘层，其设于该承载件上。
本发明还提供一种基板结构的制法，包括：形成第一绝缘层于一承载件的布线区上，其中，该布线区位于该承载件的部分表面，且该布线区包含接点处；形成一线路层于该布线区上的该第一绝缘层上；以及形成第二绝缘层于该承载件上。
前述的基板结构及其制法中，该承载件具有多个电性连接该线路层的电性连接垫。
前述的基板结构及其制法中，该承载件具有介电层，以令该第一绝缘层、线路层与第二绝缘层形成于该介电层上。
前述的基板结构及其制法中，该第一绝缘层仅设于该接点处上。
前述的基板结构及其制法中，该线路层对应该第一绝缘层之处呈现阶梯状。
前述的基板结构及其制法中，该第二绝缘层仅设于该布线区上。
前述的基板结构及其制法中，该第二绝缘层具有外露部分该线路层的开孔，且该开孔的位置位于该接点处上。复包括形成导电元件于该开孔中，以令该导电元件电性连接该线路层。
前述的基板结构及其制法中，该第二绝缘层覆盖该线路层。
由上可知，本发明的基板结构及其制法，藉由该第一与第二绝缘层仅形成于该承载件的部分表面上，所以相较于现有技术，本发明于进行热处理制程期间，该基板结构可有效释放热应力，因而该基板结构不易发生翘曲，且可提升该导电元件的应力可靠性。
附图说明
图1为现有基板结构的剖面示意图；
图1A至图1E为现有基板结构的制法的上视示意图；
图2A至图2E为本发明基板结构的制法的剖面示意图；其中，图2C’及图2E’为图2C及图2E的另一实施例；以及
图3A至图3E为对应图2A至图2E的上视示意图；其中，图3C’为图3C的另一实施例。
符号说明
1,2,2’基板结构
10,20承载件
101,201电性连接垫
11,21,21’第一绝缘层
12,22第二绝缘层
13,23线路层
14,24导电元件
15,25凸块底下金属层
200板体
202介电层
203开口
220开孔
230电性接触垫
A,A’布线区
a接点处
T阶梯状。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2E为本发明基板结构2的制法的剖面示意图，且图3A至图3E为对应图2A至图2E的上视示意图。于本实施例中，该基板结构2的制法可以晶圆级(waferlevel)制程进行。
如图2A及图3A所示，提供一承载件20，该承载件20具有一板体200、设于该板体200上的多个电性连接垫201、及设于该板体200与该些电性连接垫201上的介电层202，且该介电层202具有多个开口203，以令各该电性连接垫201对应外露于各该开口203。
于本实施例中，该板体200的种类繁多，例如，具硅穿孔(Through-siliconvia，简称TSV)的中介板、硅中介板(ThroughSiliconinterposer，简称TSI)或半导体晶片等半导体板材、或者该板体200的内部可包含另一介电层(图略)、与内部线路(图略)，且该内部线路可选择性地电性连接该电性连接垫201。因此，该板体200的构造并无特别限制。
此外，形成该介电层202的材质为氮化硅(SiNX)或氧化硅(SiO2)。
如图2B及图3B所示，形成一第一绝缘层21于该介电层202的部分表面上。
于本实施例中，该介电层202的表面上可定义有多个布线区A，且该布线区A的范围内包含一接点处a，以令该第一绝缘层21仅形成于该接点处a上，其中，该接点处a的范围不会包含该电性连接垫201。
此外，该布线区A指后续线路层的占用面积的形状区域，且该接点处a指该基板结构2用于外接其它电子装置(如晶片、电路板等)的接点处。
又，该第一绝缘层21为钝化层(passivationlayer)，且其材质为光阻介电材(photosensitivedielectricmaterial，简称PDM)、聚酰亚胺(polyimide，简称PI)、苯并环丁烯(Bis-Benzo-Cyclo-Butene，简称BCB)、聚对二唑苯(Polybenzoxazole，简称PBO)、环氧树脂(epoxy)、硅胶等聚合物(polymer)材质。例如，该第一绝缘层21的制程可先涂布光阻介电材于该介电层202的全部表面上，再以曝光显影方式移除多余的光阻介电材，使剩余的光阻介电材作为该第一绝缘层21。
如图2C及图3C所示，形成一线路层23于该介电层202上并延伸至该第一绝缘层21上，使该线路层23部分接触该第一绝缘层21而部分接触该介电层202，且该线路层23还形成于该开口203中以电性连接该电性连接垫201。
于本实施例中，该线路层23对应该第一绝缘层21之处呈现阶梯状T。
此外，该线路层23为线路重布层(Redistributionlayer，简称RDL)。例如，该线路层23的制作方式先溅镀(sputtering)晶种层(seedlayer)于该电性连接垫201、介电层202与该第一绝缘层21上，再利用黄光制程形成图案化阻层，之后于图案化阻层的开口区中电镀如铜材的金属层，最后移除该阻层及其下的晶种层，以令该金属层与剩余的晶种层作为该线路层23。其中，该黄光制程意指涂布光阻、曝光该光阻、该光阻显影、蚀刻移除该阻层等步骤。
于另一实施例中，如图2C’及图3C’所示，该第一绝缘层21’沿该布线区A’形成者，所以该线路层23仅接触形成于该第一绝缘层21’上而未接触该介电层202。具体地，该布线区A,A’的范围依线路层23的占用面积而改变，所以不同实施例的布线区A,A’的范围可不相同。
如图2D及图3D所示，形成一第二绝缘层22于该布线区A上，以令该第二绝缘层22覆盖该线路层23与该第一绝缘层21。
于本实施例中，该第二绝缘层22具有外露部分该线路层23的多个开孔220，且该开孔220中的线路层23作为电性接触垫230。
此外，该开孔220的位置位于该接点处a上。
又，该第二绝缘层22为钝化层，且其材质为光阻介电材(PDM)、聚酰亚胺(polyimide，简称PI)、苯并环丁烯(Bis-Benzo-Cyclo-Butene，简称BCB)、聚对二唑苯(Polybenzoxazole，简称PBO)、环氧树脂(epoxy)、硅胶等聚合物(polymer)材质。例如，该第二绝缘层22的制程可先涂布光阻介电材覆盖该介电层202的全部外露表面、该线路层23的全部外露表面与该第一绝缘层21的全部外露表面上，再以曝光显影方式移除多余的光阻介电材，使剩余的光阻介电材作为该第二绝缘层22。
另外，该第二绝缘层22的材质可相同或不同于该第一绝缘层21的材质。
如图2E及图3E所示，形成如焊锡材料的导电元件24于该开孔220中的电性接触垫230上，以令该导电元件24电性连接该线路层23。
于本实施例中，该接点处a也可表示为该导电元件24的约略形成位置。
此外，可选择性先形成凸块底下金属层(Underbumpmetallurgy，简称UBM)25于该电性接触垫230上，再形成该导电元件24于该凸块底下金属层上。
又，若接续图2C’的制程，将得到如图2E’所示的基板结构2’，其中，图2E’的上视图如图3E所示。
本发明的制法藉由以极小面积布设该第一与第二绝缘层21,22，即该第一绝缘层21仅设于该布线区A，且该第二绝缘层22仅沿该线路层23的形成区域(即该布线区A)作布设，以缩小绝缘层的布设面积，所以能大幅减少该承载件20与该绝缘层两者的接触面积，且大幅缩小两者的热膨胀系数(CTE)的差异，因而能将该基板结构2的翘曲幅度降至最小，并可提升该导电元件24的应力可靠性。
本发明还提供一种基板结构2,2’，包括：一承载件20、第一绝缘层21,21’、一线路层23以及第二绝缘层22。
所述的承载件20具有电性连接该线路层23的电性连接垫201，且该承载件20定义有至少一布线区A,A’，其中，该布线区A,A’位于该承载件20的部分表面，且该布线区A,A’包含接点处a。
所述的第一绝缘层21,21’仅设于该承载件20的布线区A,A’上。
所述的线路层23设于该布线区A,A’上的第一绝缘层21,21’上。
所述的第二绝缘层22仅设于该布线区A上(即沿该线路层23的形成区域作布设)，以令该第二绝缘层22覆盖该线路层23与该第一绝缘层21,21’。
于一实施例中，该承载件20具有一介电层202，以令该第一绝缘层21、线路层23与第二绝缘层22形成于该介电层202上。
于一实施例中，该第一绝缘层21仅设于该接点处a上，使该线路层23对应该第一绝缘层21之处呈现阶梯状T，例如，该电性接触垫230接触该第一绝缘层21上，而该线路层23的其它部分则接触该承载件20上。
于一实施例中，该第二绝缘层22具有外露部分该线路层23的开孔220，且该开孔220的位置位于该接点处a上，又该基板结构2,2’复包括设于该开孔220中并电性连接该线路层23的导电元件24。
综上所述，本发明的基板结构及其制法，主要藉由缩小该第一与第二绝缘层的布设面积，以减少该承载件与该绝缘层两者的接触面积及两者间的热膨胀系数差异，所以该基板结构不易发生翘曲，且能提升该导电元件的应力可靠性。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种基板结构，包括：
一承载件，其定义有至少一布线区，其中，该布线区位于该承载件的部分表面，且该布线区包含接点处；
第一绝缘层，其设于该布线区上；
一线路层，其设于该布线区上的该第一绝缘层上；以及
第二绝缘层，其设于该承载件上。
2.如权利要求1所述的基板结构，其特征为，该承载件具有多个电性连接该线路层的电性连接垫。
3.如权利要求1所述的基板结构，其特征为，该承载件具有介电层，以令该第一绝缘层、线路层与第二绝缘层形成于该介电层上。
4.如权利要求1所述的基板结构，其特征为，该第一绝缘层仅设于该接点处上。
5.如权利要求1所述的基板结构，其特征为，该线路层对应该第一绝缘层之处呈现阶梯状。
6.如权利要求1所述的基板结构，其特征为，该第二绝缘层仅设于该布线区上。
7.如权利要求1所述的基板结构，其特征为，该第二绝缘层具有外露部分该线路层的开孔，且该开孔的位置位于该接点处上。
8.如权利要求7所述的基板结构，其特征为，该结构还包括导电元件，其设于该开孔中并电性连接该线路层。
9.如权利要求1所述的基板结构，其特征为，该第二绝缘层覆盖该线路层。
10.一种基板结构的制法，其包括：
形成第一绝缘层于一承载件的布线区上，其中，该布线区位于该承载件的部分表面，且该布线区包含接点处；
形成一线路层于该布线区上的该第一绝缘层上；以及
形成第二绝缘层于该承载件上。
11.如权利要求10所述的基板结构的制法，其特征为，该承载件具有多个电性连接该线路层的电性连接垫。
12.如权利要求10所述的基板结构的制法，其特征为，该承载件具有介电层，以令该第一绝缘层、线路层与第二绝缘层形成于该介电层上。
13.如权利要求10所述的基板结构的制法，其特征为，该第一绝缘层仅设于该接点处上。
14.如权利要求10所述的基板结构的制法，其特征为，该线路层对应该第一绝缘层之处呈现阶梯状。
15.如权利要求10所述的基板结构的制法，其特征为，该第二绝缘层仅设于该布线区上。
16.如权利要求10所述的基板结构的制法，其特征为，该第二绝缘层具有外露部分该线路层的开孔，且该开孔的位置位于该接点处上。
17.如权利要求16所述的基板结构的制法，其特征为，该制法还包括形成导电元件于该开孔中，以令该导电元件电性连接该线路层。
18.如权利要求10所述的基板结构的制法，其特征为，该第二绝缘层覆盖该线路层。
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TW201613045A (en) 2016-04-01

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