CN102916667B - Broadband programmable gain amplifier with 2dB step length - Google Patents
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- CN102916667B CN102916667B CN201110220592.4A CN201110220592A CN102916667B CN 102916667 B CN102916667 B CN 102916667B CN 201110220592 A CN201110220592 A CN 201110220592A CN 102916667 B CN102916667 B CN 102916667B
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Abstract
The invention discloses a broadband programmable gain amplifier with 2dB step length. The amplifier includes: the amplifier comprises a variable gain amplifier adopting a source degeneration and current mode combined technology, a buffer stage adopting a fully differential source follower structure, and a 2dB resistance attenuator adopting a fully differential R-2R ladder resistance structure with a symmetrical structure; the input end of the variable gain amplifier is connected with the first differential input signal and the second differential input signal, and the output end of the variable gain amplifier is connected with the input end of the buffer stage; the output end of the buffer stage is connected with the input end of the 2dB resistance attenuator; the output end of the 2dB resistance attenuator is a differential signal output end, and the differential signal output end comprises: a first differential signal output terminal and a second differential signal output terminal. The 2dB step programmable gain amplifier provided by the scheme has higher linearity on the premise that the noise performance is not deteriorated, and can effectively reduce the distortion of signals.
Description
Technical field
The present invention relates to integrated circuit (IC) design technical field, particularly relate to a kind of broadband programmable gain amplifier of 2dB step-length.
Background technology
Along with developing rapidly of Communications Market, radio communication has entered the epoch of high speed data transfer, and wider frequency band effectively will improve message transmission rate, especially short-range wireless high-speed transmission.The Ultra-wideband Communication Technology being operated in 3.1-10.6GHz frequency range that FCC announced in 2002 is as a kind of unconventional, novel Radio Transmission Technology, adopt extremely wide bandwidth (being greater than 500MHz) to transmit information, there is the features such as transmission rate is high, spatial frequency spectrum efficiency is high, system is simple and easy, low in energy consumption.At present, Ultra-wideband Communication Technology is just being widely used in the short-distance wireless high-speed transfer fields such as enterprise intelligent office, digital home entertainment, medical treatment, In-vehicle networking.
Although super-broadband tech is compared to traditional narrowband systems, there is a lot of advantage, compared to traditional narrow wireless communication technology, occurred in super-broadband tech from the past different from theory to the challenge designed.These technological challenges comprise: the radio-frequency front-end in broadband, baseband circuit design at a high speed, the design of ultra broadband MIMO technology, ultra-wideband antenna, disturb and the reduction of noise and removal etc.In addition, ultra broadband and coexisting of various narrowband systems need the receiving system of ever-increasing dynamic range, and this is also technological difficulties.In conjunction with the 6-9GHz frequency range that China plans ultrabroad-band spectrum, from the angle that system realizes, adopt 0.18 μm of CMOS technology of current main-stream, the radio-frequency front-end design in broadband is especially rich in challenge.
Programmable gain amplifier is as the very important module of in radio-frequency front-end, and its performance of performance on whole radio-frequency front-end has vital impact.Especially, for ultra-wideband communication system, by utilizing the broadband programmable gain amplifier of high linearity to carry out adjustment gain, the distortion of signal can be effectively reduced.And along with the raising of the broadband programmable gain amplifier linearity, its noiseproof feature will improve.Therefore, how to ensure that the linearity improving broadband programmable gain amplifier is a study hotspot at noiseproof feature not by under the prerequisite that worsens.
Summary of the invention
Embodiments provide a kind of broadband programmable gain amplifier of 2dB step-length, at noiseproof feature not by under the prerequisite that worsens, it has the higher linearity, and can effectively reduce the distortion of signal, technical scheme is as follows:
A broadband programmable gain amplifier for 2dB step-length, comprising:
The variable gain amplifier of employing source degeneracy and current-mode combined technology, the 2dB resistance attenuator adopting the buffer stage of the source follower structure of fully differential, adopt the R-2R ladder shaped resistance structure of the fully differential form of symmetrical configuration;
The input of described variable gain amplifier is connected with the first differential input signal, the second differential input signal, and output is connected with the input of described buffer stage;
The output of described buffer stage is connected with the input of described 2dB resistance attenuator;
The output of described 2dB resistance attenuator is differential signal outputs, and described differential signal outputs comprises: the first differential signal outputs and the second differential signal outputs.
The programmable gain amplifier of the 2dB step-length that the embodiment of the present invention provides by the employing source degeneracy be connected successively and current-mode combined technology variable gain amplifier, adopt the buffer stage of the source follower structure of fully differential, adopt the 2dB resistance attenuator of the R-2R ladder shaped resistance structure of the fully differential form of symmetrical configuration to form.Variable gain amplifier is on the basis of common source degeneracy structure, have employed the technology that linearity enhancement mode source degeneracy structure combines with current amplifier, make the equivalent transconductance of the trsanscondutance amplifier of source degeneracy structure be similar to linear term, effectively can improve the linearity of whole programmable gain amplifier; Simultaneously cascade resistance attenuator after variable gain amplifier, makes resistance attenuator while fine adjustment gain, ensures that the noiseproof feature of overall amplifier is not worsened.Therefore, the programmable gain amplifier of the 2dB step-length that this programme provides, at noiseproof feature not by under the prerequisite that worsens, has the higher linearity, can effectively reduce the distortion of signal.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The electrical block diagram of a kind of broadband programmable gain amplifier that Fig. 1 provides for the embodiment of the present invention;
The electrical block diagram of the variable gain amplifier in a kind of broadband programmable gain amplifier that Fig. 2 provides for the embodiment of the present invention;
The electrical block diagram of the buffer stage in a kind of broadband programmable gain amplifier that Fig. 3 provides for the embodiment of the present invention;
The electrical block diagram of the 2dB resistance attenuator in a kind of broadband programmable gain amplifier that Fig. 4 provides for the embodiment of the present invention.
Embodiment
Embodiments provide a kind of broadband programmable gain amplifier of 2dB step-length, it not by under the prerequisite that worsens at noiseproof feature, has the higher linearity, is arranged on the receiving terminal of ultra-wideband communication system, can effectively reduce the distortion of signal.The broadband programmable gain amplifier of this 2dB step-length, comprising:
The variable gain amplifier of employing source degeneracy and current-mode combined technology, the 2dB resistance attenuator adopting the buffer stage of the source follower structure of fully differential, adopt the R-2R ladder shaped resistance structure of the fully differential form of symmetrical configuration;
The input of described variable gain amplifier is connected with the first differential input signal, the second differential input signal, and output is connected with the input of described buffer stage;
The output of described buffer stage is connected with the input of described 2dB resistance attenuator;
The output of described 2dB resistance attenuator is differential signal outputs, and described differential signal outputs comprises: the first differential signal outputs and the second differential signal outputs.
The programmable gain amplifier of the 2dB step-length that the embodiment of the present invention provides by the employing source degeneracy be connected successively and current-mode combined technology variable gain amplifier, adopt the buffer stage of the source follower structure of fully differential, adopt the 2dB resistance attenuator of the R-2R ladder shaped resistance structure of the fully differential form of symmetrical configuration to form.Variable gain amplifier is on the basis of common source degeneracy structure, have employed the technology that linearity enhancement mode source degeneracy structure combines with current amplifier, make the equivalent transconductance of the trsanscondutance amplifier of source degeneracy structure be similar to linear term, effectively can improve the linearity of whole programmable gain amplifier; Simultaneously cascade resistance attenuator after variable gain amplifier, makes resistance attenuator while fine adjustment gain, ensures that the noiseproof feature of overall amplifier is not worsened.Therefore, the programmable gain amplifier of the 2dB step-length that this programme provides, at noiseproof feature not by under the prerequisite that worsens, has the higher linearity, can effectively reduce the distortion of signal.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1, a kind of broadband programmable gain amplifier of 2dB step-length that the embodiment of the present invention provides comprises:
The variable gain amplifier 101 of employing source degeneracy and current-mode combined technology, the 2dB resistance attenuator 103 adopting the buffer stage 102 of the source follower structure of fully differential, adopt the R-2R ladder shaped resistance structure of the fully differential form of symmetrical configuration;
The input of variable gain amplifier 101 and the first differential input signal V
inp, the second differential input signal V
innbe connected, output is connected with the input of buffer stage 102;
The output of buffer stage 102 is connected with the input of described 2dB resistance attenuator 103;
The output of 2dB resistance attenuator 103 is differential signal outputs, and described differential signal outputs comprises: the first differential signal outputs V
outpwith the second differential signal outputs V
outn.
Fig. 2 is the electrical block diagram of variable gain amplifier 101.As shown in Figure 2, variable gain amplifier 101 comprises: the first differential input stage 201, source degeneracy switched resistor network 202, two buffered feedback levels: the first buffered feedback level 203 and the second buffered feedback level 204, two have the current amplifier stage of resistance feedback: the first current amplifier stage and the second current amplifier stage.
Wherein, the first differential input stage 201 comprises: the first nmos pass transistor M
11with the second nmos pass transistor M
12, by the 3rd nmos pass transistor M
31a, the 4th nmos pass transistor M
32a, the 5th nmos pass transistor M
31b, the 6th nmos pass transistor M
32bthe NMOS cascade current source current source formed, by the first PMOS transistor M
21a, the second PMOS transistor M
22a, the 3rd PMOS transistor M
21b, the 4th PMOS transistor M
22bthe PMOS cascade active load formed;
First nmos pass transistor M
11with the second nmos pass transistor M
12, its grid meets the first differential input signal V respectively
inp, the second differential input signal V
inn, its source electrode meets the 5th nmos pass transistor M respectively
31drain electrode
b, the 6th nmos pass transistor M
32bdrain electrode, its drain electrode meets the 3rd PMOS transistor M respectively
21bdrain electrode, the 4th PMOS transistor M
22bdrain electrode;
3rd nmos pass transistor M
31awith the 4th nmos pass transistor M
32a, its grid connects the first buffered feedback level 203 first nmos source respectively and follows pipe M
41with the source electrode of source follower in the second buffered feedback level 204, its drain electrode meets the 5th nmos pass transistor M respectively
31bsource electrode and the 6th NMOS crystal M
32bsource electrode, its source ground;
5th nmos pass transistor M
31bwith the 6th NMOS crystal M
32b, its grid connects, and with the first bias voltage V
bn1connect;
First PMOS transistor M
21awith the second PMOS transistor M
22a, its grid be connected, and with the 4th bias voltage V
bp2be connected, its drain electrode respectively with the 3rd PMOS transistor M
21bsource electrode, the 4th PMOS transistor M
22bsource electrode be connected, its source electrode connects supply voltage;
3rd PMOS transistor M
21bwith the 4th PMOS transistor M
22b, its grid be connected, and with the 3rd bias voltage V
bp1be connected.
Wherein, source degeneracy switched resistor network 202 comprises: the connection in series-parallel of many group resistance switchs is formed, and this resistance switch string comprises: the first resistance R
sn1, the first switch S
n, the second resistance R
sn2, wherein n=1,2,3,4 ...
Wherein, the first buffered feedback level 203 comprises: the first nmos source follows pipe M
41, the second nmos source follows pipe M
51, by the 7th nmos pass transistor M
41a, the 8th nmos pass transistor M
51a, the 9th nmos pass transistor M
41bwith the tenth nmos pass transistor M
51bthe NMOS cascade active load formed;
First nmos source follows pipe M
41pipe M is followed with the second nmos source
51, its grid is connected, and is connected to the first nmos pass transistor M in the first differential input stage
11drain electrode, its source electrode respectively with the 9th nmos pass transistor M
41bdrain electrode, the tenth nmos pass transistor M
51bdrain electrode be connected, its drain electrode connect supply voltage;
7th nmos pass transistor M
41awith the 8th nmos pass transistor M
51a, its grid be connected, and with the second bias voltage V
bn2be connected, its drain electrode respectively with the 9th nmos pass transistor M
41bsource electrode, the tenth nmos pass transistor M
51bsource electrode be connected, its source ground;
9th nmos pass transistor M
41bwith the tenth nmos pass transistor M
51b, its grid be connected, and with the first bias voltage V
bn1be connected, and the 9th nmos pass transistor M
41bdrain electrode and the first differential input stage in the 3rd nmos pass transistor M
31agrid be connected.
Wherein, as shown in Figure 2, described first nmos source in described second buffered feedback level 204 follows pipe M
41pipe M is followed with the second nmos source
51grid be connected to the second nmos pass transistor M in the first differential input stage 201
12drain electrode, described 9th nmos pass transistor M
41bdrain electrode and the first differential input stage 201 in the 4th nmos pass transistor M
32agrid be connected, remaining circuit annexation is identical with described first buffered feedback level; Do not repeat them here.
Wherein, the first current amplifier stage 205 comprises: by the 11 nmos pass transistor M
71awith the tenth bi-NMOS transistor M
71bthe NMOS cascade mirror current source formed, by the 5th PMOS transistor M
61awith the 6th PMOS transistor M
61bthe PMOS cascade active load formed and feedback resistance R
f1;
11 nmos pass transistor M
71a, the second nmos source in its grid and the first buffered feedback level follows pipe M
51source electrode be connected, its drain electrode with the tenth bi-NMOS transistor M
71bsource electrode be connected, its source ground;
Tenth bi-NMOS transistor M
71b, its grid meets the first bias voltage V
bn1, drain electrode meets the first differential signal outputs V
outp;
5th PMOS transistor M
61a, its grid meets the 4th bias voltage V
bP2, drain electrode meets the 6th PMOS transistor M
61bsource electrode, source electrode connects supply voltage;
6th PMOS transistor M
61b, its grid meets the 3rd bias voltage V
bP1, drain electrode meets the first differential signal outputs V
outp;
Feedback resistance R
f1be connected on the 11 nmos pass transistor M
71agrid and the first differential signal outputs V
outpbetween.
Wherein, as shown in Figure 2, the second current amplifier stage 206 forms identical with the first current amplifier stage 205 circuit, and the difference of connected mode is: the feedback resistance R in the second current amplifier stage 206
f1be connected on the 11 nmos pass transistor M in the second current amplifier stage 206
71agrid and the second differential signal outputs V
outnbetween.Therefore, for the second current amplifier stage 206 circuit composition and connected mode do not repeat them here.
Fig. 3 is the electrical block diagram of buffer stage 102.As shown in Figure 3, buffer stage 102 comprises:
By the 13 nmos pass transistor M
n1with the 14 nmos pass transistor M
n2the second differential input stage 301 formed, by the 15 nmos pass transistor M
n3, the 16 nmos pass transistor M
n4, the 17 nmos pass transistor M
n5with the 18 nmos pass transistor M
n6the cascade active load 302 formed;
13 nmos pass transistor M
n1with the 14 nmos pass transistor M
n2, its grid respectively with the first differential input signal V
inp, the second differential input signal V
innbe connected, its source electrode respectively with the second differential signal outputs V of buffer stage
outn, the first differential signal outputs V
outpbe connected, namely, its source electrode respectively with the 15 nmos pass transistor M
n3drain electrode, the 16 nmos pass transistor M
n4drain electrode be connected, its drain electrode connects with supply voltage;
15 nmos pass transistor M
n3with the 16 nmos pass transistor M
n4, its grid be connected, and with the first bias voltage V
bn1be connected;
17 nmos pass transistor M
n5with the 18 nmos pass transistor M
n6, its grid be connected, and with the second bias voltage V
bn2be connected, its drain electrode respectively with the 15 nmos pass transistor M
n3source electrode, the 16 nmos pass transistor M
n4source electrode is connected, its source ground.
Fig. 4 is the electrical block diagram of 2dB resistance attenuator 103.As shown in Figure 4,2dB resistance attenuator 103 comprises:
Second switch is to the 7th switch: S
01, S
11, S
21, S
02, S
12, S
22, identical the 3rd resistance of resistance is to the 6th resistance: R
11, R
21, R
12, R
22, the 7th resistance that resistance is different and the 8th resistance: R
1, R
2;
3rd resistance R
11with the 4th resistance R
21be connected in series, and the first differential input signal V
inpwith the 3rd resistance R
11one end be connected; Second switch S
01one end and the 3rd resistance R
11connect the first differential input signal V
inpone end be connected, the other end and the first differential signal outputs V
outpbe connected; 3rd switch S
11one end and the 4th resistance R
21connect the 3rd resistance R
11one end be connected, the other end and the first differential signal outputs V
outpbe connected; 4th switch one end and the 4th resistance R
21the other end be connected, the other end and the first differential signal outputs V
outpbe connected;
5th resistance R
12with the 6th resistance R
22be connected in series, and the second differential input signal V
innwith the 5th resistance R
12one end be connected; 5th switch S
02one end and the 5th resistance R
12connect the second differential input signal V
innone end be connected, the other end and the second differential signal outputs V
outnbe connected; 6th switch S
12one end and the 6th resistance R
22connect the 5th resistance R
12one end be connected, the other end and the second differential signal outputs V
outnbe connected; 7th switch S
22one end and the 6th resistance R
22the other end be connected, the other end and the second differential signal outputs V
outnbe connected;
7th resistance R
1one end and the 4th resistance R
21connect the 3rd resistance R
11one end be connected, the other end and the 6th resistance R
22connect the 5th resistance R
12one end be connected; 8th resistance R
2one end and the 4th resistance R
21connect the 4th switch S
21one end be connected, the other end and the 6th resistance R
22connect the 7th switch S
22one end be connected.
The operation principle of the broadband programmable gain amplifier of a kind of 2dB step-length that the embodiment of the present invention provides is: as shown in Figure 2, the buffered feedback level of the first differential input stage, source degeneracy switched resistor network and two symmetrical configuration constitutes linearity enhancement mode source degeneracy structure, this structure is improved on the basis of conventional source degeneracy structure, can effectively improve the linearity and bandwidth.Differential input voltage signal is by linearity enhancement mode source degeneracy circuit structure, and be approximately linearly converted to current signal, be namely equivalent to the trsanscondutance amplifier of an approximately linear, equivalent transconductance can approximate representation be:
Wherein R
sfor source degeneracy resistance.Current signal again through current amplifier stage amplify after, by feedback resistance R
f1constitute a closed loop trans-impedance amplifier, the equivalent resistance of this amplifier can approximate representation be:
R
m≈-R
F1
Couple together by the buffered feedback level of a source follower structure between first differential input stage and current amplifier stage, an effect of buffered feedback level makes the equivalent transconductance of differential input stage closer to linear term 1/R
s, namely obtain the better linearity, another effect carries out frequency compensation between two-stage, makes overall amplifier more stable.Therefore, the gain A of overall variable gain amplifier
vcan be expressed as:
Visible, the amplifier gain of this structure is only relevant with resistance ratio, and does not depend on the absolute value with resistance, therefore can obtain more accurate yield value, change any one resistance value, can reach the object changing gain.
In addition, owing to have employed current-mode, and introduce buffered feedback level, the dominant pole of overall variable gain amplifier is only determined by the electric capacity of feedback resistance and output node, suitable choose feedback resistance value amplifier and can realize wider bandwidth.In order to ensure to remain unchanged at adjustment gain Time Bandwidth, R should be made
f1remain unchanged, therefore, by resistance R
sbe designed to switch resistance array, by control switch, can control R
sresistance, thus the gain of control amplifier.
While guarantee high linearity index, in order to meet the demand of more accurate gain adjuster step in practical application, the mode of cascade 2dB resistance attenuator after variable gain amplifier is have employed in the present invention, as shown in Figure 1, accurate 2dB gain-adjusted is realized with 2dB resistance decrement network, and realize with variable gain amplifier the coarse tuning that 6dB regulates step-length, so both meet degree of regulation requirement, also ensure that the noise factor of overall amplifier simultaneously.
The circuit theory of 2dB resistance decrement network is the attenuator realizing any step-length derived by R-2R trapezoid resistance network, as shown in Figure 4, works as R
11, R
21with R
12, R
22all get identical resistance R
0time, R
2for 8R
0, R
1for 40R
0, the R-2R trapezoid resistance network revised like this can realize the decay of 2dB step-length.
Finally, the gain-adjusted of overall programmable gain amplifier is by digital switch control realization, attainable gain-adjusted scope is-4dB ~ 28dB, and gain adjuster step is 2dB, and it be 20dBm, NF is 23.7dB when maximum gain that-three dB bandwidth is greater than 300MHz, OIP3.
Therefore, the broadband programmable gain amplifier of the 2dB step-length that the embodiment of the present invention provides, when noiseproof feature is not worsened, meets specific bandwidth demand and has the higher linearity, be used in super broad band radio communication system application, the distortion of signal can be effectively reduced.
The above is only the specific embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (3)
1. a broadband programmable gain amplifier for 2dB step-length, is characterized in that, comprising:
The variable gain amplifier adopting linearity enhancement mode source degeneracy and current-mode combined technology, the 2dB resistance attenuator adopting the buffer stage of the source follower structure of fully differential, adopt the R-2R ladder shaped resistance structure of the fully differential form of symmetrical configuration;
The input of described variable gain amplifier is connected with the first differential input signal, the second differential input signal, and output is connected with the input of described buffer stage;
The output of described buffer stage is connected with the input of described 2dB resistance attenuator;
The output of described 2dB resistance attenuator is differential signal outputs, and described differential signal outputs comprises: the first differential signal outputs and the second differential signal outputs;
Described variable gain amplifier comprises: the first differential input stage, source degeneracy switched resistor network, two buffered feedback levels: the first buffered feedback level and the second buffered feedback level, two current amplifier stage with resistance feedback: the first current amplifier stage and the second current amplifier stage;
Wherein, described first differential input stage comprises: the first nmos pass transistor and the second nmos pass transistor, the NMOS cascade current source current source be made up of the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, the PMOS cascade active load be made up of the first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor, the 4th PMOS transistor;
Described first nmos pass transistor and the second nmos pass transistor, its grid connects the first differential input signal, the second differential input signal respectively, its source electrode connects the drain electrode of the 5th nmos pass transistor, the drain electrode of the 6th nmos pass transistor respectively, and its drain electrode connects the drain electrode of the 3rd PMOS transistor, the drain electrode of the 4th PMOS transistor respectively;
Described 3rd nmos pass transistor and the 4th nmos pass transistor, its grid connects the source electrode of source follower in buffered feedback level respectively, and its drain electrode connects the source electrode of the 5th nmos pass transistor, the source electrode of the 6th NMOS crystal, its source ground respectively;
Described 5th nmos pass transistor and the 6th NMOS crystal, its grid connects, and connects with the first bias voltage;
Described first PMOS transistor and the second PMOS transistor, its grid is connected, and is connected with the 4th bias voltage, and its drain electrode is connected with the source electrode of the 3rd PMOS transistor, the source electrode of the 4th PMOS transistor respectively, and its source electrode connects supply voltage;
Described 3rd PMOS transistor and the 4th PMOS transistor, its grid is connected, and is connected with the 3rd bias voltage;
Wherein, described source degeneracy switched resistor network forms by organizing resistance switch connection in series-parallel more, and described resistance switch string comprises: the first resistance, the first switch, the second resistance;
Wherein, described first buffered feedback level and the second buffered feedback level include: the first nmos source follows pipe, second nmos source follows pipe, the NMOS cascade active load be made up of the 7th nmos pass transistor, the 8th nmos pass transistor, the 9th nmos pass transistor and the tenth nmos pass transistor;
Described first nmos source follows pipe and the second nmos source follows pipe, its grid is connected, and be connected to the drain electrode of the first nmos pass transistor in the first differential input stage, its source electrode is connected with the drain electrode of the 9th nmos pass transistor, the drain electrode of the tenth nmos pass transistor respectively, and its drain electrode connects supply voltage;
Described 7th nmos pass transistor and the 8th nmos pass transistor, its grid is connected, and is connected with the second bias voltage, and its drain electrode is connected with the source electrode of the 9th nmos pass transistor, the source electrode of the tenth nmos pass transistor respectively, its source ground;
Described 9th nmos pass transistor and the tenth nmos pass transistor, its grid is connected, and is connected with the first bias voltage, and the drain electrode of the 9th nmos pass transistor is connected with the grid of the 3rd nmos pass transistor in the first differential input stage;
Described first nmos source in described second buffered feedback level follows the drain electrode that grid that pipe and the second nmos source follow pipe is connected to the second nmos pass transistor in the first differential input stage, the drain electrode of described 9th nmos pass transistor is connected with the grid of the 4th nmos pass transistor in the first differential input stage, and remaining circuit annexation is identical with described first buffered feedback level;
Wherein, described first current amplifier stage comprises: the NMOS cascade mirror current source be made up of the 11 nmos pass transistor and the tenth bi-NMOS transistor, the PMOS cascade active load be made up of the 5th PMOS transistor and the 6th PMOS transistor and feedback resistance;
Described 11 nmos pass transistor, the source electrode that its grid follows pipe with the second nmos source in buffered feedback level is connected, and its drain electrode is connected with the source electrode of the tenth bi-NMOS transistor, its source ground;
Described tenth bi-NMOS transistor, its grid connects the first bias voltage, and drain electrode connects the first differential signal outputs;
Described 5th PMOS transistor, its grid connects the 4th bias voltage, and drain electrode connects the source electrode of the 6th PMOS transistor, and source electrode connects supply voltage;
Described 6th PMOS transistor, its grid connects the 3rd bias voltage, and drain electrode connects the first differential signal outputs;
Between the grid that described feedback resistance is connected on the 11 nmos pass transistor and the first differential signal outputs;
Wherein, described second current amplifier stage forms identical with the first current amplifier stage circuit, between the grid that its feedback resistance is connected on the 11 nmos pass transistor in the second current amplifier stage and the second differential signal outputs.
2. amplifier according to claim 1, is characterized in that, described buffer stage comprises:
The second differential input stage be made up of the 13 nmos pass transistor and the 14 nmos pass transistor, the cascade active load be made up of the 15 nmos pass transistor, the 16 nmos pass transistor, the 17 nmos pass transistor, the 18 nmos pass transistor;
Described 13 nmos pass transistor and the 14 nmos pass transistor, its grid is connected with the first differential input signal, the second differential input signal respectively, its source electrode is connected with the drain electrode of the 15 nmos pass transistor, the drain electrode of the 16 nmos pass transistor respectively, and its drain electrode connects with supply voltage;
Described 15 nmos pass transistor and the 16 nmos pass transistor, its grid is connected, and is connected with the first bias voltage;
Described 17 nmos pass transistor and the 18 nmos pass transistor, its grid is connected, and is connected with the second bias voltage, and its drain electrode is connected with the 15 nmos pass transistor source electrode, the 16 nmos pass transistor source electrode respectively, its source ground.
3. programmable gain amplifier according to claim 2, it is characterized in that, described 2dB resistance attenuator comprises: six switches: second switch is to the 7th switch, four resistance that resistance is identical: the 3rd resistance is to the 6th resistance, two resistance that resistance is different: the 7th resistance and the 8th resistance;
3rd resistance and the 4th resistant series connect, and the first differential input signal is connected with one end of the 3rd resistance; Second switch one end is connected the first differential input signal one end with the 3rd resistance is connected, and the other end is connected with the first differential signal outputs; 3rd switch one end is connected the 3rd resistance one end with the 4th resistance is connected, and the other end is connected with the first differential signal outputs; 4th switch one end is connected with the other end of the 4th resistance, and the other end is connected with the first differential signal outputs;
5th resistance and the 6th resistant series connect, and the second differential input signal is connected with one end of the 5th resistance; 5th switch one end is connected the second differential input signal one end with the 5th resistance is connected, and the other end is connected with the second differential signal outputs; 6th switch one end is connected the 5th resistance one end with the 6th resistance is connected, and the other end is connected with the second differential signal outputs; 7th switch one end is connected with the other end of the 6th resistance, and the other end is connected with the second differential signal outputs;
One end that 7th resistance one end is connected the 3rd resistance with the 4th resistance is connected, and the other end is connected the 5th resistance one end with the 6th resistance is connected; One end that 8th resistance one end is connected the 4th switch with the 4th resistance is connected, and the other end is connected the 7th switch one end with the 6th resistance is connected.
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| CN109167583B (en) * | 2018-10-31 | 2024-07-16 | 上海海栎创科技股份有限公司 | Transconductance amplifier |
| CN111130551B (en) * | 2020-01-06 | 2023-08-08 | 西安电子科技大学 | Buffer based on inductance frequency expansion and sampling front-end circuit thereof |
| CN111884605B (en) * | 2020-08-10 | 2024-05-17 | 上海川土微电子有限公司 | Differential operational amplifier |
| CN112886934B (en) * | 2021-01-11 | 2024-03-19 | 新郦璞科技(上海)有限公司 | Programmable gain amplifier with adjustable input/output voltage |
| CN113114162A (en) * | 2021-03-24 | 2021-07-13 | 中国电子科技集团公司第三十八研究所 | Attenuator circuit for CMOS broadband amplitude-phase multifunctional chip |
| CN113472328B (en) * | 2021-09-06 | 2021-11-16 | 广东芯炽集成电路技术有限公司 | Power switch for burning OTP (one time programmable) of high-speed analog-to-digital converter |
| CN115426000B (en) * | 2022-08-31 | 2023-07-04 | 集益威半导体(上海)有限公司 | Analog receiving front-end circuit |
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