CN103000692A - Thin-film transistor structure and manufacturing method thereof - Google Patents
Thin-film transistor structure and manufacturing method thereof Download PDFInfo
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- CN103000692A CN103000692A CN2011102712295A CN201110271229A CN103000692A CN 103000692 A CN103000692 A CN 103000692A CN 2011102712295 A CN2011102712295 A CN 2011102712295A CN 201110271229 A CN201110271229 A CN 201110271229A CN 103000692 A CN103000692 A CN 103000692A
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Abstract
The invention provides a thin-film transistor which comprises a substrate, a channel layer formed on the substrate, a gate, a gate insulated layer formed between the gate and the channel layer, a source and a drain. The source and the drain are arranged on the left and right of the channel layer respectively and are communicated with the channel layer. The channel layer is made of nitride semiconductor material. As the channel layer is made of the nitride semiconductor, performance stability in the thin-film transistor can be improved and quality of the thin-film transistor is improved. The invention further provides a manufacturing method of the thin-film transistor.
Description
Technical field
The present invention relates to a kind of structure and manufacture method of semiconductor element, relate in particular to a kind of structure and manufacture method thereof of thin-film transistor.
Background technology
In recent years, because the progress of semiconductor process techniques, the manufacturing of thin-film transistor is healed and is become quick.Thin-film transistor is widely used in the electronic products such as computer chip, chip for cell phone or Thin Film Transistor-LCD (thin film transistor liquid crystal displayer, TFT LCD).Take Thin Film Transistor-LCD as example, thin-film transistor is namely as the switch of storage capacitors (storage capacity) charge or discharge.
Existing thin-film transistor can be divided into amorphous silicon film transistor (Amorphous Silicon Thin Film Transistor) and polycrystalline SiTFT (Polycrystalline Thin Film Transistor) according to the material of active layer.Yet in order to tackle market for the rush of demand of liquid crystal display, new thin-film transistor technologies research and development also have more input.Wherein, developed a kind of take such as the thin-film transistor of the transparent conductive metal oxides such as zinc oxide (ZnO) as active layer, its electric characteristics has been better than existing amorphous silicon film transistor, thereby can greatly improve the reaction speed of thin-film transistor, and in the performance of element, pretty good achievement arranged also.
Yet take zinc oxide as the thin-film transistor of active layer as example, in the technique of follow-up formation source electrode and drain electrode, the transparent conductive metal oxide is subject to such as plasma, etching solution and delusters causing the pollution of the materials such as resist liquid easily, and change the property of thin film of active layer, and then affect the element characteristic of thin-film transistor.
Summary of the invention
In view of this, be necessary to provide a kind of thin-film transistor structure and manufacture method thereof that has more stable characteristic and be beneficial to the techniques such as subsequent etch.
A kind of thin-film transistor, the source electrode and the drain electrode that comprise substrate, be formed at channel layer, grid on the substrate, be formed at the gate insulation layer between grid and the channel layer and lay respectively at channel layer the right and left and be conducted with channel layer, the material of described channel layer is nitride semi-conductor material.
A kind of manufacture method of thin-film transistor, its step comprises:
One substrate with upper surface is provided, and forms a depression downwards from the upper surface of substrate;
Form channel layer on substrate, make upper surface and the depression of this channel layer covered substrate, this channel layer materials is indium gallium nitride aluminium;
Remove the channel layer of the upper surface of covered substrate, and make the channel layer in the depression concordant with the upper surface of substrate;
On the upper surface of substrate and channel layer, form the source-drain electrode layer;
This source-drain electrode layer of etching forms source electrode and drain electrode;
Of heap of stone folding forms gate insulation layer and grid successively on the channel layer between source electrode and the drain electrode.
A kind of manufacture method of thin-film transistor, its step comprises:
One substrate with upper surface is provided, and forms a depression downwards from the upper surface of substrate;
One temporary base is provided, and this temporary base is provided with a decomposition layer;
Decomposition layer at this temporary base forms source-drain electrode layer and channel layer successively;
The channel layer etching is become the projection shape;
Substrate overturn is attached at the channel layer of projection shape in the depression;
Thereby decompose this decomposition layer and remove temporary base;
This source-drain electrode layer of etching forms source electrode and drain electrode;
Of heap of stone folding forms gate insulation layer and grid successively on the channel layer between source electrode and the drain electrode.
A kind of thin-film transistor comprises:
One substrate has a depressed part;
One channel layer is positioned at the depressed part of substrate;
One gate insulation layer is positioned on the channel layer and the cover part channel layer;
One grid is positioned on the gate insulation layer and the cover part gate insulation layer, and
Source electrode and drain electrode, it lays respectively at channel layer the right and left and is conducted with channel layer, and separately substrate and the channel layer of cover part;
It is characterized in that: the material of described channel layer is nitride semi-conductor material.
A kind of thin-film transistor comprises:
One substrate;
One adhesive linkage;
One grid is formed on the adhesive linkage and the cover part adhesive linkage;
One gate insulation layer is formed on the grid and cover gate and part adhesive linkage;
One channel layer is formed on the gate insulation layer and the cover part gate insulation layer, and
Source electrode and drain electrode, it lays respectively at channel layer the right and left and is conducted with channel layer;
It is characterized in that: the material of described channel layer is nitride semi-conductor material.
A kind of thin-film transistor comprises:
One substrate;
One adhesive linkage;
One grid is formed on the adhesive linkage and the cover part adhesive linkage;
One gate insulation layer is formed on the grid and cover gate and part adhesive linkage;
One channel layer is formed on the gate insulation layer and the covering gate insulating barrier;
One barrier layer is formed on the channel layer and the cover part channel layer; And
Source electrode and drain electrode, it lays respectively at channel layer the right and left and is conducted with channel layer;
It is characterized in that: the material of described channel layer is nitride semi-conductor material.
Thin-film transistor provided by the present invention, adopt nitride-based semiconductor as the material of channel layer, because its energy order range is wide, ability to anti-adverse environment is strong, as to ambient humidity, to radioresistance etc., and have the high electronics rate of vacillating, therefore be conducive to form and have high stability and high-quality thin-film transistor.
With reference to the accompanying drawings, the invention will be further described in conjunction with embodiment.
Description of drawings
Fig. 1 is the generalized section of the thin-film transistor of first embodiment of the invention.
Fig. 2 is the generalized section of the thin-film transistor of second embodiment of the invention.
Fig. 3 is the generalized section of the thin-film transistor of third embodiment of the invention.
Fig. 4 is the generalized section of the thin-film transistor of four embodiment of the invention.
Fig. 5 is the generalized section of the thin-film transistor of fifth embodiment of the invention.
Fig. 6 is the generalized section of the thin-film transistor of sixth embodiment of the invention.
Fig. 7 is the manufacture method flow chart of the thin-film transistor of second embodiment of the invention.
Fig. 8 is the generalized section of the thin-film transistor of each the step gained of manufacture method among Fig. 7.
Fig. 9 is another manufacture method flow chart of the thin-film transistor of second embodiment of the invention.
Figure 10 is the generalized section of the thin-film transistor of each the step gained of manufacture method among Fig. 9.
The main element symbol description
| Thin-film transistor | 100、200、300、400、500、600 |
| Substrate | 11、21、31、41、61 |
| Upper surface | 111、211、311、411 |
| Channel layer | 12、22、32、42、52、62 |
| Grid | 13、23、33、43、53 |
| Gate insulation layer | 14、24、34、44、54、64 |
| Source electrode | 15、25、35、45、55、65 |
| Drain electrode | 16、26、36、46、56、66 |
| The source electrode | 17、47 |
| Drain electrode | 18、48 |
| |
221 |
| |
212 |
| The source- |
27 |
| |
28 |
| |
29 |
| |
39、49 |
| The |
391 |
| |
421、521 |
| |
422 |
| The |
423、523 |
| |
441、641 |
| |
442、642 |
| The |
70 |
Following embodiment further specifies the present invention in connection with above-mentioned accompanying drawing.
Embodiment
As shown in Figure 1, thin-film transistor that embodiment of the present invention provides 100 is the top gate type structure, and it comprises substrate 11, be formed at channel layer 12, grid 13 on the substrate 11, be formed at the gate insulation layer 14 between grid 13 and the channel layer 12 and lay respectively at the right and left of channel layer 12 and the source electrode 15 that is conducted with channel layer 12 and drain 16.
Described substrate 11 can be the substrate of sapphire substrate, glass substrate, quartz base plate or other materials for example.This substrate 11 comprises a upper surface 111.Described channel layer 12 is close to this upper surface 111 and is formed on this substrate 11.
The material of this channel layer 12 is nitride semi-conductor material, and is concrete, take indium gallium nitride aluminium (InGaAlN) as good.This nitride-based semiconductor can order range wide, and because of the composition of doped chemical different its can rank greatly between 1.9 eV to 6.2 eV, its chemical formula is Al (1-x-y) InxGayN, wherein 0＜=x＜=1,0＜=y＜=1.This indium gallium nitride aluminium energy is so that the ability of the adverse circumstances such as thin-film transistor 100 Antagonistic Environment humidity, radiation is stronger, and has higher conductance.This indium gallium nitride aluminium is when film forms, because making the indium gallium nitride aluminum, employed raw material, gas or environment can comprise the elements such as hydrogen, carbon, oxygen or nitrogen, and can different the making become N-shaped, p-type or mixed type semiconductor form because of the kind of doped chemical, forming the P type semiconductor structure, or doped silicon etc. is to form the N type semiconductor structure such as magnesium-doped or zinc etc.Because indium gallium nitride aluminium can form N-shaped or p-type semiconductor form, therefore on the drive circuit of liquid crystal panel, can make N-type raceway groove (NMOS), P type raceway groove (PMOS), or the driven unit of complementary raceway groove (CMOS, Complementary MOS).This indium gallium nitride aluminium is because of different film formation conditions, as the temperature of growing up, growth pressure and growth atmosphere, can form amorphous layer, single crystalline layer or polycrystal layer structure, to satisfy different needs, it has the high electronics rate of vacillating, can improve the response speed of equipment such as display, satisfy the requirement of high definition, large capacity reality.
Described source electrode 15 and drain electrode 16 channel layer 12 both sides that are formed at respectively on the substrate 11, and be positioned at concordant with channel layer 12.This source electrode 15 and drain electrode 16 are located in channel layer 12 between the two.
Described gate insulation layer 14 and grid 13 be folded being formed on the channel layer 12 of heap of stone successively, and this gate insulation layer 14 and grid 13 are self-alignment structure, and namely the joining place of the edge source electrode 15 of this gate insulation layer 14 and grid 13, drain electrode 16 and channel layer 12 aligns with channel layer 12.Wherein, the material of this grid 13 can be selected for example aluminium, chromium, tantalum, molybdenum, copper, titanium, tungsten or other metal material, and adopts thin film deposition processes, photoetching process and etch process to form.The material of this gate insulation layer 14 can be selected dielectric material or the high dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride or tantalum oxide, and adopts chemical vapour deposition technique to form.
Also form respectively active electrode 17 and drain electrode 18 in the source electrode 15 of this thin-film transistor 100 and the drain electrode 16, to connect respectively external circuit, for this thin-film transistor 100 provides electric energy.Described source electrode 15, drain electrode 16 can also form respectively a light doping section (not shown) with the joining place of channel layer 12, thereby reduce leakage current when this thin-film transistor 100 work, thereby improve the stability of thin-film transistor 100 work.
In this first execution mode, because channel layer 12 adopts nitride semi-conductor material, not only have better stability, avoid in the technical processs such as subsequent etch, being affected, also have higher electron mobility, improve the response speed of equipment.
The thin-film transistor 100 that this first execution mode provides can adopt methods such as chemical vapour deposition technique (CVD), pulsed laser deposition (Pulse laser deposition), molecular beam epitaxy (MBE), physical vaporous deposition (PVD), sputter (Sputtering) to form successively described channel layer 12, source electrode 15, drain electrode 16 etc. at substrate 11, forms grid 13 and gate insulation layer 14 again.
See also Fig. 2, the thin-film transistor 200 that second embodiment of the invention provides is the top gate type structure, and its thin-film transistor 100 with the first execution mode is substantially identical, and difference is, channel layer 22, source electrode 25 and 26 the position of draining are different, and grid 23 is different with the structure of gate insulation layer 24.In this second execution mode, described substrate 21 comprises a upper surface 211, and this upper surface 211 forms a depression 212 downwards certainly, and described channel layer 22 is positioned at this depression 212, and the end face 221 of this channel layer 22 is close to concordant with the upper surface 211 of substrate 21.Described source electrode 25 and drain electrode 26 are formed at the upper surface 211 of substrate 21.Described gate insulation layer 24 and grid 23 be of heap of stone folding on the end face 221 of channel layer 22 successively, and at source electrode 25 with drain between 26 these gate insulation layer 24 local end faces 221 that cover channel layers 22.End face 221 edges of channel layer 22 are covered by this source electrode 25 and drain electrode 26 respectively.
See also Fig. 3, the thin-film transistor 300 that third embodiment of the invention provides is the top gate type structure, and its thin-film transistor 200 with the second execution mode is substantially identical, and difference is that substrate 31 is different from the syndeton of channel layer 32.In this 3rd execution mode, thin-film transistor 300 also comprises an adhesive linkage 39.Described substrate 31 comprises a upper surface 311, and this upper surface 311 is smooth planar structure.Described channel layer 32 is formed on the upper surface 311 of substrate 31, and the relative both sides of channel layer 32 are respectively arranged with an adhesive linkage 39.This adhesive linkage 39 is formed on the upper surface 311 of substrate, and the top is concordant with channel layer 32.Be coated with this adhesive linkage 39 around this channel layer 32, both are highly equal, so that the upper end 321 and these adhesive linkage 39 common planes 391 that form away from substrate of channel layer 32, described source electrode 35, drain electrode 36, gate insulation layer 34 is formed on this plane 391, and this substrate 31 and source electrode 35, draining 36 is connected with this adhesive linkage 39.
See also Fig. 4, the thin-film transistor 400 that four embodiment of the invention provides is the bottom gate type structure, it comprises substrate 41, adhesive linkage 49, grid 43, gate insulation layer 44, channel layer 42 successively by the end to top, and the source electrode on the channel layer 42 45, drain electrode 46, source electrode 47 and drain electrode 48.
Described substrate 41 comprises a upper surface 411, and described adhesive linkage 49 is attached on the upper surface 411 of this substrate 41.This adhesive linkage 49 can adopt the materials such as silica, silicon oxynitride, silicon nitride, glass, resin (Epoxy), SOG (Spin-on glass), silica gel (Silicone) or polymer (Polyimide) to make, or use other organic or inorganic glue material, or use the metals such as metal material such as nickel (Ni), titanium (Ti), aluminium (Al), gold (Au), silver (Ag), indium (In), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), palladium (Pd), platinum (Pt).
Described grid 43 is attached on this adhesive linkage 49, and described gate insulation layer 44 covers this grid 43 on adhesive linkage 49, and particularly, this gate insulation layer 44 comprises projection 441 and horizontal part 442.This projection 441 is the part of cover gate 43, and horizontal part 442 is tiled in part on the adhesive linkage 49 for all the other.
The projection 441 of described channel layer 42 covering gate insulating barriers 44, this channel layer 42 comprise protuberance 421, extension 422 and away from the upper surface 423 of substrate 41.This protuberance 421 is the part on the projection 441 that covers described grid 43, and this extension 422 is not for covering this projection 441 and being tiled in remainder on the horizontal part 442 of gate insulation layer 44.
Described source electrode 45 extends to the horizontal part 442 of gate insulation layer 44 from the upper surface 423 of channel layer 42 respectively with drain electrode 46 and contacts.Described source electrode 47 and drain electrode 48 are formed at respectively on source electrode 45 and the drain electrode 46.The segment thickness of upper surface 423 that this source electrode 45 and drain electrode 46 are covered in channel layer 42 is thicker, so it can protect channel layer 42 not suffer damage in the technical processs such as plasma etching.
In this 4th execution mode, substrate 41 is connected by an adhesive linkage 49 with grid 43, gate insulation layer 44, because in the manufacturing process of this thin-film transistor 400, first see Fig. 8 at a temporary base 28() formation channel layer 42, grid 43, source electrode 45 and drain 46 etc., this temporary base 28 is peeled off, the structure that will remove at last temporary base 28 adopts the mode of adhesive linkage 49 connections to be transplanted on the substrate 41 again.
Certainly, the adhesive linkage 49 in this 4th execution mode is not necessary, and this thin-film transistor 400 can also directly deposit successively on substrate 41 according to order from bottom to top and form, and does not adopt the mode of transplanting to make.
See also Fig. 5, the thin-film transistor 500 that fifth embodiment of the invention provides is the bottom gate type structure, and its thin-film transistor 400 with the 4th execution mode is substantially identical, and difference is that thin-film transistor 500 also comprises a barrier layer 70.This barrier layer 70 is formed between the upper surface 523 of described channel layer 52 and source electrode 55, the drain electrode 56.This barrier layer 70 is attached at the area of upper surface 523 of channel layer 52 less than the area of protuberance 521.This barrier layer 70 can avoid channel layer 52 to be exposed in plasma, etching solution or the materials such as causing anti-corrosion liquid that delusters and undermined, and its material can be general dielectric insulation material, such as silica, silicon nitride etc.
See also Fig. 6, the thin-film transistor 600 that sixth embodiment of the invention provides is the bottom gate type structure, and its thin-film transistor 500 with the 5th execution mode is substantially identical, and difference is, described channel layer 62 is only on the projection 641 of covering gate insulating barrier 64, and aligns with the side on barrier layer 70.This channel layer 62 is attached at gate insulation layer 64 and the local projection 641 that covers.Described source electrode 65 and drain electrode 66 are extended towards the direction near substrate 61 on barrier layer 70 respectively, and contact with the side of barrier layer 70 and channel layer 62, the projection 641 of gate insulation layer 64 and the horizontal part 642 of gate insulation layer 64 successively.
In the 5th execution mode and the 4th execution mode, form channel layer 52,42 and barrier layer 70 adopt respectively two mask (not shown) to form successively, so channel layer 52,42 and barrier layer 70 and needn't aliging in side.And in the 6th execution mode, described channel layer 62 and barrier layer 70 in etch process jointly by a mask (not shown), thereby alignd at side in channel layer 62 and barrier layer 70.
Shown in Fig. 7 and 8, the present invention also provides the manufacture method of described thin-film transistor 200, below, in connection with other accompanying drawings this manufacture method is elaborated.
One substrate 21 with upper surface 211 is provided, and forms a depression 212 downwards from the upper surface 211 of substrate 21;
Remove the channel layer 22 of the upper surface 211 of covered substrate 21, and make the channel layer 22 in the depression 212 mutually concordant with the upper surface 211 of substrate 21;
On the upper surface 211 of substrate 21 and channel layer 22, form source-drain electrode layer 27;
This source-drain electrode layer 27 of etching forms source electrode 25 and drain electrode 26;
In source electrode 25 and drain between 26, folded gate insulation layer 24 and the grid 23 of forming of heap of stone successively on the channel layer 22.
In the step of this manufacture method, can adopt methods such as chemical vapour deposition technique (CVD), pulsed laser deposition (Pulse laser deposition), molecular beam epitaxy (MBE), physical vaporous deposition (PVD), sputter (Sputtering) on substrate 21, directly to form channel layer 22 etc.Because offer depression 212 on the substrate 21, channel layer 22 is formed in the depression 212, thereby makes channel layer 22 have stable film characteristics, and then promotes the element characteristic of this thin-film transistor 200.
As shown in Figures 9 and 10, the present invention also provides another manufacture method of described thin-film transistor 200.
One substrate 21 with upper surface 211 is provided, and forms a depression 212 downwards from the upper surface 211 of substrate 21;
One temporary base 28 is provided, and this temporary base 28 is provided with a decomposition layer 29;
The channel layer 22 of projection shape is embedded in the depression 212 of substrate 21;
Thereby decompose this decomposition layer 29 and remove temporary base 28;
This source-drain electrode layer 27 of etching forms source electrode 25 and drain electrode 26;
In source electrode 25 and drain between 26, folded gate insulation layer 24 and the grid 23 of forming of heap of stone successively on the channel layer 22.
In this manufacture method the second to the 4th step in the upper manufacture method is replaced, adopt first on the temporary base 28 with on the opposite order of a manufacture method successively sedimentary origin drain electrode layer 27 and channel layer 22, again channel layer 22 combinations are connected on the substrate 21, at last temporary base 28 are removed.
Described temporary base 28 can adopt sapphire or carbofrax material to make, substrate 21 can adopt glass material to make, be formed on the temporary base 28 thereby source-drain electrode layer 27 and channel layer 22 can at high temperature be deposited, be connected and fixed by the modes such as wafer combination and substrate 21 again.Certainly, substrate 21 also can adopt metal material, plastics or flexible base plate (flexible substrate), also can be that organic material or inorganic material are made.The step of peeling off temporary base 28 can adopt the technology such as laser lift-off, illumination assisted etch are peeled off, chemical etching, cmp.Remove the step of behind the temporary base 28 desired structure being transplanted on the substrate 41 and also can adopt the technology such as wafer combination.This manufacture method can reduce condition required in the manufacturing process, reduces the difficulty of growth, can also make the performance of final thin-film transistor 200 more stable and good.The the 3rd to the 6th execution mode all can adopt the mode that forms desired structure at temporary base 28 first to form among the present invention.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change the protection range that all should belong to claim of the present invention with distortion.
Claims (19)
1. thin-film transistor, comprise substrate, be formed at channel layer, grid on the substrate, be formed at the gate insulation layer between grid and the channel layer and lay respectively at channel layer the right and left and with source electrode and drain electrode that channel layer is conducted, it is characterized in that: the material of described channel layer is nitride semi-conductor material.
2. thin-film transistor as claimed in claim 1, it is characterized in that: described nitride semi-conductor material is indium gallium nitride aluminium, its chemical composition is Al (1-x-y) InxGayN, wherein 0＜=x＜=1,0＜=y＜=1.
3. thin-film transistor as claimed in claim 2, it is characterized in that: described nitride semi-conductor material includes hydrogen, carbon, oxygen, nitrogen, silicon, magnesium, or in the zinc one or more.
4. thin-film transistor as claimed in claim 2, it is characterized in that: described nitride semi-conductor material is amorphous layer, single crystalline layer or polycrystal layer structure.
5. thin-film transistor as claimed in claim 2, it is characterized in that: described channel layer is close to substrate, and gate insulation layer and grid are of heap of stone successively foldedly to be formed on the channel layer and between source electrode and drain electrode.
6. thin-film transistor as claimed in claim 5, it is characterized in that: described source electrode is concordant with channel layer with drain electrode and be positioned at the channel layer both sides, and described gate insulation layer and grid align with channel layer with the joining place of channel layer from source electrode and drain electrode.
7. thin-film transistor as claimed in claim 5, it is characterized in that: described substrate has upper surface, this substrate is formed with a depression downwards from upper surface, described channel layer is formed in this depression, and concordant with the upper surface of substrate, described source electrode is formed at respectively on the upper surface of substrate and with channel layer with drain electrode and contacts, and the area that described gate insulation layer contacts with channel layer is less than the channel layer area concordant with the upper surface of substrate.
8. thin-film transistor as claimed in claim 5, it is characterized in that: also comprise an adhesive linkage, described channel layer is sticked and is formed on the substrate, and this adhesive linkage is positioned at the peripheral and concordant with channel layer of channel layer, and described source electrode lays respectively on the adhesive linkage and with channel layer with drain electrode and contacts.
9. such as claim 7 or 8 described thin-film transistors, it is characterized in that: described gate insulation layer and grid are on the channel layer, between source electrode and the drain electrode.
10. thin-film transistor as claimed in claim 1, it is characterized in that: also comprise an adhesive linkage, described grid, gate insulation layer, channel layer be of heap of stone folding on adhesive linkage successively, described gate insulation layer cover gate is on adhesive linkage, the part of gate insulation layer cover gate forms a projection, remainder is tiled in and forms horizontal part on the adhesive linkage, and described source electrode extends to the horizontal part of gate insulation layer away from the top of substrate from channel layer respectively with drain electrode and contacts.
11. thin-film transistor as claimed in claim 10 is characterized in that: described channel layer is formed on the projection, and the setting of aliging with grid.
12. thin-film transistor as claimed in claim 11 is characterized in that: described channel layer is away from also being formed with a barrier layer, the justified margin of this barrier layer and channel layer between the end face of substrate and source electrode, the drain electrode.
13. thin-film transistor as claimed in claim 10, it is characterized in that: described channel layer is formed on the gate insulation layer, this channel layer covers this projection, and the part that wherein covers this projection forms protuberance, and the part that does not cover this projection is tiled on the horizontal part of gate insulation layer and forms extension.
14. thin-film transistor as claimed in claim 13 is characterized in that: described channel layer is away from also being formed with a barrier layer between the end face of substrate and source electrode, the drain electrode, and this barrier layer is formed on the protuberance, and the area on this barrier layer is less than the area of protuberance.
15. the manufacture method of a thin-film transistor, its step comprises:
One substrate with upper surface is provided, and forms a depression downwards from the upper surface of substrate;
Form channel layer on substrate, make upper surface and the depression of this channel layer covered substrate, this channel layer materials is indium gallium nitride aluminium;
Remove the channel layer of the upper surface of covered substrate, and make the channel layer in the depression concordant with the upper surface of substrate;
On the upper surface of substrate and channel layer, form the source-drain electrode layer;
This source-drain electrode layer of etching forms source electrode and drain electrode;
Of heap of stone folding forms gate insulation layer and grid successively on the channel layer between source electrode and the drain electrode.
16. the manufacture method of a thin-film transistor, its step comprises:
One substrate with upper surface is provided, and forms a depression downwards from the upper surface of substrate;
One temporary base is provided, and this temporary base is provided with a decomposition layer;
Decomposition layer at this temporary base forms source-drain electrode layer and channel layer successively;
The channel layer etching is become the projection shape;
Substrate overturn is attached at the channel layer of projection shape in the depression;
Thereby decompose this decomposition layer and remove temporary base;
This source-drain electrode layer of etching forms source electrode and drain electrode;
Of heap of stone folding forms gate insulation layer and grid successively on the channel layer between source electrode and the drain electrode.
17. a thin-film transistor comprises:
One substrate has a depressed part;
One channel layer is positioned at the depressed part of substrate;
One gate insulation layer is positioned on the channel layer and the cover part channel layer;
One grid is positioned on the gate insulation layer and the cover part gate insulation layer, and
Source electrode and drain electrode, it lays respectively at channel layer the right and left and is conducted with channel layer, and separately substrate and the channel layer of cover part;
It is characterized in that: the material of described channel layer is nitride semi-conductor material.
18. a thin-film transistor comprises:
One substrate;
One adhesive linkage;
One grid is formed on the adhesive linkage and the cover part adhesive linkage;
One gate insulation layer is formed on the grid and cover gate and part adhesive linkage;
One channel layer is formed on the gate insulation layer and the cover part gate insulation layer, and
Source electrode and drain electrode, it lays respectively at channel layer the right and left and is conducted with channel layer;
It is characterized in that: the material of described channel layer is nitride semi-conductor material.
19. a thin-film transistor comprises:
One substrate;
One adhesive linkage;
One grid is formed on the adhesive linkage and the cover part adhesive linkage;
One gate insulation layer is formed on the grid and cover gate and part adhesive linkage;
One channel layer is formed on the gate insulation layer and the covering gate insulating barrier;
One barrier layer is formed on the channel layer and the cover part channel layer; And
Source electrode and drain electrode, it lays respectively at channel layer the right and left and is conducted with channel layer;
It is characterized in that: the material of described channel layer is nitride semi-conductor material.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103779424A (en) * | 2014-01-21 | 2014-05-07 | 江苏大学 | Amorphous state gallium nitride or indium nitride thin film transistor and preparation method thereof |
| CN104409510A (en) * | 2014-10-28 | 2015-03-11 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method, array substrate and preparation method, and display apparatus |
| WO2017128555A1 (en) * | 2016-01-28 | 2017-08-03 | 深圳市华星光电技术有限公司 | Thin film transistor substrate and manufacturing method therefor |
| WO2020143335A1 (en) * | 2019-01-09 | 2020-07-16 | 京东方科技集团股份有限公司 | Thin film transistor and method for manufacturing same, and display device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0531550A1 (en) * | 1991-03-28 | 1993-03-17 | Asahi Kasei Kogyo Kabushiki Kaisha | Field effect transistor |
| CN1505172A (en) * | 2002-12-03 | 2004-06-16 | 精工爱普生株式会社 | Transistor, integrated circuit, photoelectric device, electronic device and manufacturing method thereof |
| US20040178412A1 (en) * | 2003-03-14 | 2004-09-16 | Chien-Ting Lai | Thin film transistor and method of manufacturing the same and display apparatus using the transistor |
| CN1941299A (en) * | 2005-09-29 | 2007-04-04 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN1998085A (en) * | 2004-05-20 | 2007-07-11 | 克里公司 | Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions |
| CN101506985A (en) * | 2006-09-22 | 2009-08-12 | 国产大学法人东北大学 | Semiconductor device and semiconductor device manufacturing method |
| US20090302321A1 (en) * | 2008-06-04 | 2009-12-10 | Samsung Electronics Co., Ltd | Thin Film Transistor Substrate and Method of Manufacturing the Same |
| US20110057232A1 (en) * | 2008-05-09 | 2011-03-10 | Cree, Inc. | Semiconductor devices including shallow implanted regions and methods of forming the same |
| US7928427B1 (en) * | 2009-11-27 | 2011-04-19 | National Chiao Tung University | Semiconductor device with group III-V channel and group IV source-drain and method for manufacturing the same |
-
2011
- 2011-09-14 CN CN2011102712295A patent/CN103000692A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0531550A1 (en) * | 1991-03-28 | 1993-03-17 | Asahi Kasei Kogyo Kabushiki Kaisha | Field effect transistor |
| CN1505172A (en) * | 2002-12-03 | 2004-06-16 | 精工爱普生株式会社 | Transistor, integrated circuit, photoelectric device, electronic device and manufacturing method thereof |
| US20040178412A1 (en) * | 2003-03-14 | 2004-09-16 | Chien-Ting Lai | Thin film transistor and method of manufacturing the same and display apparatus using the transistor |
| CN1998085A (en) * | 2004-05-20 | 2007-07-11 | 克里公司 | Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions |
| CN1941299A (en) * | 2005-09-29 | 2007-04-04 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN101506985A (en) * | 2006-09-22 | 2009-08-12 | 国产大学法人东北大学 | Semiconductor device and semiconductor device manufacturing method |
| US20110057232A1 (en) * | 2008-05-09 | 2011-03-10 | Cree, Inc. | Semiconductor devices including shallow implanted regions and methods of forming the same |
| US20090302321A1 (en) * | 2008-06-04 | 2009-12-10 | Samsung Electronics Co., Ltd | Thin Film Transistor Substrate and Method of Manufacturing the Same |
| US7928427B1 (en) * | 2009-11-27 | 2011-04-19 | National Chiao Tung University | Semiconductor device with group III-V channel and group IV source-drain and method for manufacturing the same |
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| CN103779424A (en) * | 2014-01-21 | 2014-05-07 | 江苏大学 | Amorphous state gallium nitride or indium nitride thin film transistor and preparation method thereof |
| CN103779424B (en) * | 2014-01-21 | 2017-09-29 | 江苏大学 | A kind of amorphous state gallium nitride or indium nitride film transistor and preparation method thereof |
| CN104409510A (en) * | 2014-10-28 | 2015-03-11 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method, array substrate and preparation method, and display apparatus |
| WO2017128555A1 (en) * | 2016-01-28 | 2017-08-03 | 深圳市华星光电技术有限公司 | Thin film transistor substrate and manufacturing method therefor |
| WO2020143335A1 (en) * | 2019-01-09 | 2020-07-16 | 京东方科技集团股份有限公司 | Thin film transistor and method for manufacturing same, and display device |
| US11257954B2 (en) | 2019-01-09 | 2022-02-22 | Boe Technology Group Co., Ltd. | Thin film transistor and manufacturing method thereof, and display apparatus |
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