CN103779424A - Amorphous state gallium nitride or indium nitride thin film transistor and preparation method thereof - Google Patents
Amorphous state gallium nitride or indium nitride thin film transistor and preparation method thereof Download PDFInfo
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- CN103779424A CN103779424A CN201410026623.6A CN201410026623A CN103779424A CN 103779424 A CN103779424 A CN 103779424A CN 201410026623 A CN201410026623 A CN 201410026623A CN 103779424 A CN103779424 A CN 103779424A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 68
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 60
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 title claims abstract description 60
- 238000002360 preparation method Methods 0.000 title claims abstract description 40
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000006243 chemical reaction Methods 0.000 claims abstract description 33
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000005516 engineering process Methods 0.000 claims abstract description 27
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000002019 doping agent Substances 0.000 claims abstract description 22
- 229910000077 silane Inorganic materials 0.000 claims abstract description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 16
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052749 magnesium Inorganic materials 0.000 claims abstract description 11
- 239000011777 magnesium Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000001257 hydrogen Substances 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 92
- 239000010408 film Substances 0.000 claims description 77
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 229910021529 ammonia Inorganic materials 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 claims description 6
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical group C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 claims description 5
- 239000012159 carrier gas Substances 0.000 claims description 4
- 239000002346 layers by function Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract description 18
- 239000007789 gas Substances 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 238000010924 continuous production Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 10
- 239000013077 target material Substances 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000004062 sedimentation Methods 0.000 description 4
- 238000003980 solgel method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000004064 recycling Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000001338 self-assembly Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 229910052984 zinc sulfide Inorganic materials 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 230000036244 malformation Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 239000002562 thickening agent Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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Abstract
The invention relates to the field of functional thin film preparation methods and application, in particular to an amorphous state gallium nitride or indium nitride thin film transistor and a preparation method thereof. The plasma-enhanced chemical vapor deposition technology is adopted, an organic source and ammonia gas are used as reaction sources, hydrogen or nitrogen is used as an organic source gas carrier source, silane and trimethyl magnesium are used as dopants, and n-type amorphous state gallium nitride or indium nitride and p-type amorphous state gallium nitride or indium nitride are prepared on a substrate respectively. The n-type amorphous state gallium nitride or indium nitride thin film and the p-type amorphous state gallium nitride or indium nitride thin film are used as channel layers of the thin film transistor, amorphous state gallium nitride or indium nitride thin films and amorphous state gallium nitride or indium nitride thin film transistors prepared through the method are obtained on low-cost substrates, and therefore manufacturing cost is lowered greatly. The amorphous state gallium nitride or indium nitride thin film transistor is high in material uniformity degree, low in impurity content, large in adhesive force of components and a substrate and the like. In addition, the method has the advantages of being simple in operation, suitable for large area continuous production and the like.
Description
Technical field
The present invention relates to a kind of function film preparation method and application, refer in particular to a kind of amorphous state gallium nitride or indium nitride film transistor and preparation method thereof.
Background technology
By InN, GaN, the III group-III nitride semiconductor of AlN and alloy composition thereof is a current most important class wide bandgap semiconductor, its thermodynamically metastable fixed structure is wurtzite structure, the wurtzite structure crystal of III group-III nitride is take tetrahedral structure as basis, there are six side's symmetry, that diatomic layer by Hexagonal array is regularly by ABAB ... sequence stack form (<0111> direction), these characteristics that have due to III group-III nitride, its main application fields comprises semiconductor lighting, the optical storage of DVD, detector (number of patent application: 200810019832.2, 200810019835.6) and high temperature, high frequency, High-Power Microwave device, for example, the nearly safe people's (number of patent application: 0212445.5) a kind of compound semiconductor of 3 ~ 5 families is provided, and has been applied to light-emitting diode that waits of family, in addition people's (number of patent application: 200910060799.2) utilize the growth of semiconductor epitaxial layers also to realize the research and development of GaN based light-emitting diode such as Zhao Yanli, Kang Xiang rather waits people's (number of patent application: 200510073285.2,200610167605.5) proposed a kind of high-luminance chip of luminescent tube in GaN base and preparation method thereof and reduced the method for stress between GaN single crystal film and heterogeneous substrate.
The preparation method of III group-III nitride comprises molecular beam epitaxy, organic molecule vapour phase epitaxy, pyrolyzing synthesis dusty material and sol-gel process (number of patent application: 03110867.9) etc.; Except sol-gel process, III group-III nitride normally heteroepitaxy in the c surface sapphire substrate, and lattice and thermal mismatching between c surface sapphire substrate and c face III group-III nitride is all larger, cause like this in epitaxial process, producing a large amount of dislocations and defect, and cause epitaxial crystal malformation, thereby produce piezoelectric polarization fields, piezoelectric polarization fields can change crystal equally can be with distribution, the distribution in electronics and hole is staggered, and effective energy gap is reduced, excite Dependent Red Shift; Sol-gel process is prepared III group-III nitride need to mix some macromolecule material thickeners, and therefore impurity content is many; In recent years, the people such as Zhao Guijuan (number of patent application: 201210313725.7) at Grown non polarity A side InGaN flexible layer, then growing GaN resilient coating on non polarity A side InGaN flexible layer, non polarity A side InGaN flexible layer and non polarity A side GaN resilient coating are carried out to annealing in process, form self assembly horizontal extension template, and in self assembly horizontal extension template growing nonpolar A face GaN film; The equal people of state Du (number of patent application: the advantage of 201010554940.7) utilizing SiC substrate lattice and GaN to match, on SiC substrate, make a kind of vertical structure light-emitting pipe, meanwhile, also can utilize multilayer III group-III nitride on diamond thick-film substrate, to prepare SAW (Surface Acoustic Wave) device (number of patent application: 201110062224.1).
As can be seen here, aspect prepared by amorphous state gallium nitride or indium nitride material and device, research staff has carried out a large amount of work, but no matter is to utilize new substrate and new technology, and production cost is still higher at present, and technique is more lengthy and jumbled; The invention provides a kind of in general substrate, for example, on glass, pi flexiplast or monocrystalline silicon piece, utilize chemical vapour deposition technique to prepare the preparation method of amorphous state gallium nitride or indium nitride film and amorphous state gallium nitride or indium nitride film semiconductor device, the material uniformity coefficient made by the method is high, impurity content is low, device and the advantage such as substrate adhesive force is large; This manufacture method has easy and simple to handlely in addition, is suitable for large area quantity-produced advantage.
Summary of the invention
The object of the invention is to provide the preparation method of a kind of amorphous state gallium nitride and amorphous state indium nitride film and amorphous state gallium nitride and amorphous state indium nitride film semiconductor device, using plasma chemical vapour deposition technique, utilizes organic source, ammonia as reaction source; Utilize hydrogen or nitrogen as organic source carrier gas source, utilize silane, trimethyl magnesium as dopant, on substrate (as silicon chip, glass or plastics), prepare respectively N-shaped, p-type amorphous state gallium nitride or indium nitride; And channel layer using N-shaped, p-type amorphous state gallium nitride or indium nitride film as thin-film transistor, its thin-film transistor structure as depicted in figs. 1 and 2, the amorphous state gallium nitride of making by the method or indium nitride film and amorphous state gallium nitride or indium nitride film transistor are to obtain on cheap substrate, therefore greatly reduce manufacturing cost; Material uniformity coefficient of the present invention is high, impurity content is low, device and the advantage such as substrate adhesive force is large; In addition the inventive method have easy and simple to handle, be suitable for the continuously advantage such as production of large area.
The technical solution adopted for the present invention to solve the technical problems is: using plasma chemical vapour deposition technique, utilizes organic source, ammonia as reaction source; Utilize hydrogen or nitrogen as organic source carrier gas source, utilize silane, trimethyl magnesium as dopant, on substrate, prepare respectively N-shaped, p-type amorphous state gallium nitride or amorphous state indium nitride film; Using N-shaped, p-type amorphous state gallium nitride or amorphous state indium nitride as thin film transistor channel layer, prepare top-grate structure thin film transistor and bottom grating structure thin-film transistor.
As preferably, described plasma chemical vapor deposition technique is prepared in amorphous state gallium nitride or amorphous state indium nitride film process, its technological parameter is: organic source and ammonia mass flow ratio are 1:2 ~ 1:1, and radio-frequency power is 50 ~ 350 W, and reaction pressure is 20 ~ 200 Pa; Described underlayer temperature is room temperature to 350 ℃.
Described dopant is N-shaped dopant or p-type dopant; Wherein, dopant and organic source quality flow mixed proportion are 1% ~ 20%, and organic source and ammonia mass flow mixed proportion are 1:2 ~ 1:1; Wherein said N-shaped dopant, p-type dopant can be selected respectively trimethyl magnesium and silane, and described organic source is trimethyl gallium, triethyl-gallium or trimethyl indium.
Described top-grate structure thin film transistor is made up of substrate, barrier layer, channel layer, source electrode, gate dielectric layer, gate electrode and drain electrode, substrate top is barrier layer, barrier layer top is channel layer, both sides, channel layer top are respectively source-drain electrode, channel layer is gate dielectric layer in the middle of top, gate dielectric layer top is gate electrode, transistor completes the stack growth of each functional layer in conjunction with mask process by chemical vapour deposition (CVD) and magnetron sputtering, as shown in Figure 1, manufacturing process is shown in embodiment to concrete structure.
Described bottom grating structure thin-film transistor by substrate, gate electrode, gate dielectric layer, channel layer, source electrode and drain electrode, form, substrate top is gate electrode, gate electrode top is gate dielectric layer, gate dielectric layer top is channel layer, both sides, channel layer top are respectively source electrode and drain electrode, transistor completes the stack growth of each functional layer in conjunction with mask process by chemical vapour deposition (CVD) and magnetron sputtering, as shown in Figure 2, manufacturing process is shown in embodiment to concrete structure.
Described top-grate structure thin film transistor is by substrate, barrier layer, channel layer, source electrode, gate dielectric layer, gate electrode and drain electrode composition, every layer film relies on the rete of self to form and be connected with other films, first on the substrate through cleaning, prepare barrier layer, utilize PECVD method to prepare channel layer on barrier layer surface, then utilize magnetically controlled sputter method in conjunction with mask process at channel layer surface preparation source electrode and drain electrode, recycling PECVD method is prepared gate dielectric layer in conjunction with mask process on channel layer surface, finally utilize magnetron sputtering to prepare gate electrode on gate dielectric layer surface, concrete structure as shown in Figure 1, manufacturing process is shown in embodiment.
Described bottom grating structure thin-film transistor is made up of substrate, gate electrode, gate dielectric layer, channel layer, source electrode and drain electrode, every layer film relies on the rete of self to form and be connected with other films, first on the substrate through cleaning, utilize magnetron sputtering to prepare gate electrode, then utilize PECVD method to prepare gate dielectric layer at surface gate electrode, then utilize PECVD to prepare channel layer on gate dielectric layer surface, recycling mask plate technique in conjunction with magnetron sputtering at channel layer surface preparation source electrode and drain electrode.
Described substrate is glass, pi flexiplast or monocrystalline silicon piece.
As preferably, described top-grate structure thin film transistor, adopts silicon dioxide or silicon nitride film as barrier layer, and thickness is 100 ~ 2000nm.
As preferably, in described amorphous state gallium nitride or indium nitride film transistor, gate dielectric layer is selected silicon dioxide or silicon nitride, and thickness is 200 ~ 5000 nm; Its silicon dioxide preparation technology parameter is: pass into the oxygen that flow is 30 ~ 90 sccm, flow is the silane of 5 ~ 20 sccm; Controlling reaction chamber pressure is 10 ~ 200 Pa; Adjustment radio-frequency power is 30 ~ 200W; Underlayer temperature is 20 ~ 200 ℃; Its silicon nitride preparation technology parameter is: pass into the nitrogen that flow is 30 ~ 90 sccm, flow is the silane of 5 ~ 20 sccm; Controlling reaction chamber pressure is 10 ~ 200 Pa; Adjustment radio-frequency power is 30 ~ 200W; Underlayer temperature is 200 ~ 400 ℃.
As preferably, in described amorphous state gallium nitride or indium nitride film transistor, gate electrode, source electrode, drain electrode are selected the metal oxide materials of metal and conduction, and thickness is 50 ~ 500nm; Wherein, the transistorized source of bottom grating structure electrode, drain electrode length are 800 ~ 1200 μ m, and wide is 100 ~ 150 μ m, and between source electrode, drain electrode, spacing is 50 ~ 100 μ m, and gate electrode length is 800 ~ 1200 μ m, and wide is 250 ~ 400 μ m; The transistorized source of top gate structure electrode, drain electrode length are 800 ~ 1200 μ m, and wide is 100 ~ 150 μ m, and between source electrode, drain electrode, spacing is 50 ~ 100 μ m, and gate electrode length is 800 ~ 1200 μ m, and wide is 50 ~ 90 μ m.
As preferably, in described amorphous state gallium nitride or indium nitride film transistor, channel layer is selected amorphous state gallium nitride or the indium nitride film of n or p-type doping, and thickness is 10 ~ 1000 nm.
Compared with amorphous state gallium nitride or indium nitride semiconductor device, amorphous state gallium nitride of the present invention or indium nitride film and amorphous state gallium nitride or indium nitride film semiconductor device have following advantage:
The preparation method of amorphous state gallium nitride of the present invention or indium nitride film and amorphous state gallium nitride or indium nitride film semiconductor device is simple, make that raw material source is abundant, low price, can cheap material be matrix preparation; The preparation technology of amorphous state gallium nitride of the present invention or indium nitride film and amorphous state gallium nitride or indium nitride film semiconductor device and microelectronic processing technology compatibility, do not need to change other existing equipmenies, and repeatability and uniformity are high, are suitable for large area and produce continuously; Semiconductor device of the present invention can be used widely in fields such as Display Technique, signal switch technology, sensing technologies.
Accompanying drawing explanation
Fig. 1 is top gate structure amorphous state gallium nitride (indium) thin-film transistor schematic cross-section prepared by the present invention;
1, substrate; 2, channel layer; 3, source electrode; 4, gate dielectric layer; 5, gate electrode; 6, drain electrode; 7, barrier layer.
Fig. 2 is bottom grating structure amorphous state gallium nitride (indium) thin-film transistor schematic cross-section prepared by the present invention;
1, substrate; 2, channel layer; 3, source electrode; 4, gate dielectric layer; 5, gate electrode; 6, drain electrode.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, is not violating under purport of the present invention, the present invention should be not limited to example laboratory and specifically express content.
Raw materials is as follows:
Silane: purity is 99.9%; Hydrogen: purity is 99.9%; Trimethyl gallium, triethyl-gallium, trimethyl indium, trimethyl magnesium etc., purity is 99.99%; Oxygen: purity is 99.95%; Nitrogen: purity is 99.95%.
Amorphous state gallium nitride of the present invention, indium nitride film transistor preparation method comprise the steps:
1. substrate is prepared: wherein substrate is selected silicon chip, glass or flexible sub-polyamide.
2. prepared by gate electrode, source electrode, drain electrode, selects the metal oxide materials of metal and conduction.
3. gate dielectric layer preparation, wherein gate dielectric layer is selected silicon dioxide or silicon nitride.
4. channel layer preparation, wherein channel layer is selected N-shaped or p-type amorphous state gallium nitride or amorphous state indium nitride film.
5. adopt silicon dioxide or silicon nitride film as barrier layer.
Embodiment 1: the transistorized preparation of top gate structure amorphous state gallium nitride film
1. pair glass substrate is cleaned.
2. utilizing PECVD technology growth thickness is the silicon nitride film of 300 nm, as device barrier layer; Pass into the ammonia that flow is 40 sccm, flow is the silane of 20 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is 250 ℃
3. utilizing PECVD technology growth thickness is that the N-shaped amorphous state gallium nitride film of 100 nm is as channel layer; Pass into the trimethyl gallium that flow is 30 sccm, flow is the ammonia of 40 sccm, and the trimethyl magnesium that flow is 5sccm is as N-shaped dopant; Reaction pressure is 100 Pa, and adjusting radio-frequency power is 150 W, 200 ℃ of underlayer temperatures.
4. utilizing magnetron sputtering technique growth thickness is IZO source electrode and the drain electrode of 150 nm; When source electrode, drain electrode growth, adopt mask technique pattern generation, mask plate width is 150 mm, and length is 1000 mm, and electrode spacing is 80mm; In sputter procedure, employing Ar is protective gas, and flow is 14sccm, the IZO film that utilized IZO preparation of target materials, and wherein reaction pressure is 0.5 Pa, radio-frequency power is 100W, sputtering sedimentation 15 min.
5. utilize PECVD technology to adopt self-registered technology, between source electrode and drain electrode, growth length is 1000mm, and width is 70mm, and thickness is the silicon dioxide of 800 nm, as gate dielectric layer; Pass into the oxygen that flow is 40 sccm, flow is the silane of 10 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is 25 ℃ of room temperatures.
6. utilizing magnetron sputtering technique growth thickness is that 200 nm, length are 1000 mm, and width is the ITO gate electrode of 70 mm; In sputter procedure, employing Ar is protective gas, and flow is 14sccm, the ITO film that utilized ITO preparation of target materials, and wherein reaction pressure is 0.5 Pa, radio-frequency power is 100W, sputtering sedimentation 20 min.
Embodiment 2: the transistorized preparation of bottom grating structure amorphous state indium nitride film
1. utilizing magnetron sputtering technique growth thickness is the ITO gate electrode of 100 nm, and in sputter procedure, employing Ar is protective gas; flow is 14sccm, utilizes ITO preparation of target materials ITO film, and wherein reaction pressure is 0.5 Pa; radio-frequency power is 100W, sputtering sedimentation 10 min.
2. utilizing PECVD technology is 1000mm in conjunction with mask process at surface gate electrode growth length, and width is 360mm, and thickness is the silicon dioxide of 800 nm, as gate dielectric layer, passes into the oxygen that flow is 40 sccm, and flow is the silane of 10 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is 25 ℃ of room temperatures.
3. utilizing PECVD technology is 1000mm in conjunction with mask process in gate dielectric layer superficial growth length, width is that 360mm thickness is that the p-type amorphous state indium nitride film of 80 nm is as channel layer, pass into the trimethyl indium that flow is 30 sccm, flow is the ammonia of 40 sccm, and the silane that flow is 3sccm is as p-type dopant; Adjusting radio-frequency power is 150 W, 200 ℃ of underlayer temperatures, and reaction pressure is 50 Pa.
4. utilizing magnetron sputtering technique growth thickness is IZO source electrode and the drain electrode of 200 nm, when electrode growth, adopts mask technique pattern generation, and length is 1000 mm, and width is 150 mm, and electrode spacing is 60 mm; In sputter procedure, employing Ar is protective gas, and flow is 14sccm, the IZO film that utilized IZO preparation of target materials, and wherein reaction pressure is 0.5 Pa, and radio-frequency power is 100W, and sputtering time is 20min.
Embodiment 3: the transistorized preparation of top gate structure amorphous state gallium nitride film
1. pair glass substrate is strictly cleaned.
2. utilize the PECVD technology silicon dioxide that growth thickness is 800nm in glass substrate as barrier layer, pass into the oxygen that flow is 40 sccm, flow is the silane of 10 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is 50 ℃.
3. utilizing PECVD technology growth thickness is that the N-shaped amorphous state gallium nitride film of 40 nm is as channel layer; Pass into the trimethyl gallium that flow is 30 sccm, flow is the ammonia of 40 sccm, and the trimethyl magnesium that flow is 5sccm is as N-shaped dopant; Adjusting radio-frequency power is 150 W, 200 ℃ of underlayer temperatures; Reaction pressure is 150 Pa.
4. utilizing magnetron sputtering technique growth thickness is IZO source electrode and the drain electrode of 100 nm, when electrode growth, adopts mask technique pattern generation, and length is 1200 mm, and width is 150 mm, and spacing is 100mm; In sputter procedure, employing Ar is protective gas, and flow is 14sccm, the IZO film that utilized IZO preparation of target materials, and wherein reaction pressure is 0.5 Pa, radio-frequency power is 100W.
5. utilize PECVD technology to adopt self-registered technology, between source electrode and drain electrode, growth length is 1000mm, and width is 90mm, growth thickness is the silicon dioxide of 800 nm, as gate dielectric layer, pass into the oxygen that flow is 40 sccm, flow is the silane of 10 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is 100 ℃.
6. utilizing magnetron sputtering technique growth thickness is 200 nm, and length is 1000mm, the ITO gate electrode that width is 90mm; In sputter procedure, employing Ar is protective gas, and flow is 14sccm, the ITO film that utilized ITO preparation of target materials, and wherein reaction pressure is 0.5 Pa, radio-frequency power is 100W.
Embodiment 4: the transistorized preparation of top gate structure amorphous state indium nitride film
1. pair glass substrate is strictly cleaned.
2. utilize the PECVD technology silicon dioxide that growth thickness is 1000nm in glass substrate as barrier layer, pass into the oxygen that flow is 40 sccm, flow is the silane of 10 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is 50 ℃.
3. utilizing PECVD technology growth thickness is that the N-shaped amorphous state indium nitride film of 50 nm is as channel layer; Pass into the trimethyl indium that flow is 30 sccm, flow is the ammonia of 40 sccm, and the trimethyl magnesium that flow is 5sccm is as N-shaped dopant; Adjusting radio-frequency power is 150 W, 200 ℃ of underlayer temperatures; Reaction pressure is 200 Pa.
4. utilizing magnetron sputtering technique growth thickness is IZO source electrode and the drain electrode of 150 nm; when electrode growth, adopt mask technique pattern generation, length is 1000 mm; width is 120 mm; electrode spacing is 80 mm, and in sputter procedure, employing Ar is protective gas; flow is 14sccm; the IZO film that utilized IZO preparation of target materials, wherein reaction pressure is 0.5 Pa, radio-frequency power is 100W.
5. utilize PECVD technology to adopt self-registered technology, between source electrode and drain electrode, growth length is 1000mm, and width is 70mm, growth thickness is the silicon dioxide of 1000 nm, as gate dielectric layer, pass into the oxygen that flow is 40 sccm, flow is the silane of 10 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is 100 ℃ of room temperatures.
6. utilizing magnetron sputtering technique growth thickness is that 100 nm, length are 1000mm; width is the ITO gate electrode of 70mm; in sputter procedure; employing Ar is protective gas; flow is 14sccm, the ITO film that utilized ITO preparation of target materials, and wherein reaction pressure is 0.5 Pa; radio-frequency power is 100W, sputtering sedimentation 10min.
Embodiment 5: the transistorized preparation of bottom grating structure amorphous state indium nitride film
1. utilizing magnetron sputtering technique growth thickness is the ITO gate electrode of 100 nm, and in sputter procedure, employing Ar is protective gas, and flow is 14sccm, the ITO film that utilized ITO preparation of target materials, and wherein reaction pressure is 0.5 Pa, radio-frequency power is 100W.
2. utilizing PECVD technology is 1000mm in conjunction with mask process at surface gate electrode growth length, and width is 260mm, and thickness is the silicon dioxide of 800 nm, as gate dielectric layer, passes into the oxygen that flow is 40 sccm, and flow is the silane of 10 sccm; Controlling reaction chamber pressure is 35 Pa; Adjusting radio-frequency power is 100 W; Underlayer temperature is room temperature.
3. utilizing PECVD technology is 1000mm in conjunction with mask process in gate dielectric layer superficial growth length, width is that 260mm thickness is that the p-type amorphous state indium nitride film of 30 nm is as channel layer, pass into the trimethyl indium that flow is 30 sccm, flow is the ammonia of 40 sccm, and flow is that the silane of 10 sccm is as p-type dopant; Adjusting radio-frequency power is 150 W, 200 ℃ of underlayer temperatures.
4. utilizing magnetron sputtering technique growth thickness is IZO source electrode and the drain electrode of 200 nm, when electrode growth, adopts mask technique pattern generation, and length is 1000 mm, and width is 100 mm, and electrode spacing is 60mm; In sputter procedure, employing Ar is protective gas, and flow is 14sccm, the IZO film that utilized IZO preparation of target materials, and wherein reaction pressure is 0.5 Pa, radio-frequency power is 100W.
Claims (10)
1. an amorphous state gallium nitride or indium nitride film transistor, adopt top gate structure, by substrate, barrier layer, channel layer, source electrode, gate dielectric layer, gate electrode and drain electrode composition, substrate top is barrier layer, barrier layer top is channel layer, both sides, channel layer top are respectively source-drain electrode, channel layer is gate dielectric layer in the middle of top, gate dielectric layer top is gate electrode, transistor completes the stack growth of each functional layer in conjunction with mask process by chemical vapour deposition (CVD) and magnetron sputtering, it is characterized in that: with the amorphous state gallium nitride film of N-shaped or p-type or using the amorphous state indium nitride film of N-shaped or p-type as thin film transistor channel layer.
2. an amorphous state gallium nitride or indium nitride film transistor, adopt bottom grating structure, by substrate, gate electrode, gate dielectric layer, channel layer, source electrode and drain electrode, composition, substrate top is gate electrode, gate electrode top is gate dielectric layer, gate dielectric layer top is channel layer, both sides, channel layer top are respectively source electrode and drain electrode, transistor completes the stack growth of each functional layer in conjunction with mask process by chemical vapour deposition (CVD) and magnetron sputtering, it is characterized in that: with the amorphous state gallium nitride film of N-shaped or p-type or using the amorphous state indium nitride film of N-shaped or p-type as thin film transistor channel layer.
3. a kind of amorphous state gallium nitride as claimed in claim 1 or 2 or indium nitride film transistor, is characterized in that: described substrate is glass, pi flexiplast or monocrystalline silicon piece.
4. a kind of amorphous state gallium nitride as claimed in claim 1 or indium nitride film transistor, is characterized in that: described top-grate structure thin film transistor, and adopt silicon dioxide or silicon nitride film as barrier layer, thickness is 100 ~ 2000nm.
5. a kind of amorphous state gallium nitride as claimed in claim 1 or 2 or indium nitride film transistor, is characterized in that: in described amorphous state gallium nitride or indium nitride film transistor, gate dielectric layer is selected silicon dioxide or silicon nitride, and thickness is 200 ~ 5000 nm; Its silicon dioxide preparation technology parameter is: pass into the oxygen that flow is 30 ~ 90 sccm, flow is the silane of 5 ~ 20 sccm; Controlling reaction chamber pressure is 10 ~ 200 Pa; Adjustment radio-frequency power is 30 ~ 200W; Underlayer temperature is 20 ~ 200 ℃; Its silicon nitride preparation technology parameter is: pass into the nitrogen that flow is 30 ~ 90 sccm, flow is the silane of 5 ~ 20 sccm; Controlling reaction chamber pressure is 10 ~ 200 Pa; Adjustment radio-frequency power is 30 ~ 200W; Underlayer temperature is 200 ~ 400 ℃.
6. a kind of amorphous state gallium nitride as claimed in claim 1 or 2 or indium nitride film transistor, is characterized in that: described gate electrode, source electrode, drain electrode are selected the metal oxide materials of metal and conduction, thickness is 50 ~ 500nm; Wherein, the transistorized source of bottom grating structure electrode, drain electrode length are 800 ~ 1200 μ m, and wide is 100 ~ 150 μ m, and between source electrode, drain electrode, spacing is 50 ~ 100 μ m, and gate electrode length is 800 ~ 1200 μ m, and wide is 250 ~ 400 μ m; The transistorized source of top gate structure electrode, drain electrode length are 800 ~ 1200 μ m, and wide is 100 ~ 150 μ m, and between source electrode, drain electrode, spacing is 50 ~ 100 μ m, and gate electrode length is 800 ~ 1200 μ m, and wide is 50 ~ 90 μ m.
7. a kind of amorphous state gallium nitride as claimed in claim 1 or 2 or indium nitride film transistor, is characterized in that: channel layer thickness is 10 ~ 1000 nm.
8. a kind of amorphous state gallium nitride as claimed in claim 1 or the transistorized preparation method of indium nitride film, is characterized in that: using plasma chemical vapour deposition technique, utilizes organic source, ammonia as reaction source; Utilize hydrogen or nitrogen as organic source carrier gas source, utilize silane, trimethyl magnesium as dopant, prepare N-shaped or p-type amorphous state gallium nitride or amorphous state indium nitride film; With the amorphous state gallium nitride film of N-shaped or p-type or using the amorphous state indium nitride film of N-shaped or p-type as thin film transistor channel layer, prepare top-grate structure thin film transistor.
9. a kind of amorphous state gallium nitride as claimed in claim 2 or the transistorized preparation method of indium nitride film, is characterized in that: using plasma chemical vapour deposition technique, utilizes organic source, ammonia as reaction source; Utilize hydrogen or nitrogen as organic source carrier gas source, utilize silane, trimethyl magnesium as dopant, prepare N-shaped or p-type amorphous state gallium nitride or amorphous state indium nitride film; With the amorphous state gallium nitride film of N-shaped or p-type or using the amorphous state indium nitride film of N-shaped or p-type as thin film transistor channel layer, prepare bottom grating structure thin-film transistor.
10. a kind of amorphous state gallium nitride as described in claim 3 or 4 or the transistorized preparation method of indium nitride film, it is characterized in that: described plasma chemical vapor deposition technique is prepared in amorphous state gallium nitride or amorphous state indium nitride film process, its technological parameter is: organic source and ammonia mass flow ratio are 1:2 ~ 1:1, radio-frequency power is 50 ~ 350 W, and reaction pressure is 20 ~ 200 Pa; Described underlayer temperature is room temperature to 350 ℃; Described dopant is N-shaped dopant or p-type dopant; Wherein, dopant and organic source quality flow mixed proportion are 1% ~ 20%, and organic source and ammonia mass flow mixed proportion are 1:2 ~ 1:1; Wherein said N-shaped dopant, p-type dopant are selected respectively trimethyl magnesium and silane, and described organic source is trimethyl gallium, triethyl-gallium or trimethyl indium.
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| CN105304717A (en) * | 2015-10-08 | 2016-02-03 | 安阳工学院 | InN-based field effect transistor and manufacturing method thereof |
| EP3043389A4 (en) * | 2013-08-30 | 2017-04-26 | Japan Science and Technology Agency | Ingaaln-based semiconductor element |
| CN107464851A (en) * | 2017-08-10 | 2017-12-12 | 华南理工大学 | A kind of gallium nitride film transistor and its manufacture method |
| CN109056070A (en) * | 2018-07-10 | 2018-12-21 | 南昌大学 | A kind of preparation method of polycrystalline indium nitride |
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| US20130001646A1 (en) * | 2011-06-29 | 2013-01-03 | Hrl Laboratories, Llc | ALGaN/GaN HYBRID MOS-HFET |
| CN103000692A (en) * | 2011-09-14 | 2013-03-27 | 鸿富锦精密工业（深圳）有限公司 | Thin-film transistor structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20130001646A1 (en) * | 2011-06-29 | 2013-01-03 | Hrl Laboratories, Llc | ALGaN/GaN HYBRID MOS-HFET |
| CN103000692A (en) * | 2011-09-14 | 2013-03-27 | 鸿富锦精密工业（深圳）有限公司 | Thin-film transistor structure and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP3043389A4 (en) * | 2013-08-30 | 2017-04-26 | Japan Science and Technology Agency | Ingaaln-based semiconductor element |
| CN105304717A (en) * | 2015-10-08 | 2016-02-03 | 安阳工学院 | InN-based field effect transistor and manufacturing method thereof |
| CN107464851A (en) * | 2017-08-10 | 2017-12-12 | 华南理工大学 | A kind of gallium nitride film transistor and its manufacture method |
| CN109056070A (en) * | 2018-07-10 | 2018-12-21 | 南昌大学 | A kind of preparation method of polycrystalline indium nitride |
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