CN101506985A - Semiconductor device and semiconductor device manufacturing method - Google Patents
Semiconductor device and semiconductor device manufacturing method Download PDFInfo
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- CN101506985A CN101506985A CNA2007800310951A CN200780031095A CN101506985A CN 101506985 A CN101506985 A CN 101506985A CN A2007800310951 A CNA2007800310951 A CN A2007800310951A CN 200780031095 A CN200780031095 A CN 200780031095A CN 101506985 A CN101506985 A CN 101506985A
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Abstract
In a semiconductor device, a trench is arranged on an insulating layer on a substrate, and a gate electrode is formed in the trench so that the surface of the gate electrode is substantially flat with the surface of the insulating layer. On the gate electrode, a semiconductor layer is arranged through a gate insulating film, and at least a source electrode or a drain electrode is electrically connected to the semiconductor layer. Especially the gate insulating layer includes an insulating coat film arranged on the gate electrode and an insulating CVD film formed on the insulating coat film.
Description
Technical field
The present invention relates to semiconductor device, particularly relate to thin-film transistor (TFT) and manufacture method thereof.
Background technology
Usually, display unit such as liquid crystal indicator, organic El device, inorganic EL device are the conductive pattern of wiring graph, electrode pattern etc. film forming and form by forming figure in turn on the substrate with a smooth interarea.Then on the element that constitutes electrode film, display unit film forming in turn such as necessary various films, and make display unit by forming figure.
In recent years, maximize for the strong request of this kind display unit.Then need on substrate, high accuracy form more display element in order to form large-scale display unit, and these elements are electrically connected with wiring graph.At this moment, except wiring graph, also forming the state formation with multiple stratification such as dielectric film, TFT (thin-film transistor) element, light-emitting component on the substrate.Its result obtains step-like ladder on substrate, wiring graph is crossed these ladders and come distribution.
And then when display unit was maximized, wiring graph self was just elongated, therefore needed to reduce the resistance of this wiring graph.Eliminate the ladder of wiring graph and the method for resistance step-down, for example disclosed by patent documentation 1, patent documentation 2 and patent documentation 3.Patent documentation 1～3 discloses: in order to form the such flat-panel screens distribution of LCD, then form distribution and be that the transparent insulation material and the wiring graph of equal height joins with it at transparent substrate surface.Also disclose in patent documentation 3: utilization adds drop stamping and CMP (Chemical Mechanical Polishing cmp) makes the more method of planarization of distribution.
Patent documentation 1:WO2004/110117 number
Patent documentation 2: special hope 2005-173050 communique
Patent documentation 3: the spy opens the 2005-210081 communique
Patent documentation 4: the spy opens the 2002-296780 communique
Patent documentation 5: the spy opens the 2001-188343 communique
Disclose in the patent documentation 1: by in the groove that forms by the resin figure, burying distribution underground and carrying out the characteristic that thick-membrane distribution just can improve display unit.And as distribution formation method methods such as ink-jet method, stencil printing are disclosed.
But recognize that disclosed method has problem on the being adjacent to property to substrate.
Also recognize on the other hand, when as patent documentation 1 is put down in writing, distribution being formed by conductive ink and screen printing etc., the rough surface of distribution, and the flatness such as insulating barrier that form on the distribution are bad.When by conductive ink, when the formed distribution of screen printing uses as gate electrode, owing to making the charge carrier spreading rate by passage, the distribution rough surface worsens, be observed the phenomenon that becomes the high speed motion obstacle.But also recognize in conductive ink, screen printing etc. if distribution is fine, then be difficult to obtain desirable shape.Even for example want to form with said method the gate electrode of width 20 μ m, length 50 μ m, electrode material can not arrive whole, recognizes in practicality to form the figure of wishing.
Patent documentation 2 is in order to address these problems, in order to improve the being adjacent to property to substrate, the manufacture method of institute's motion comprises at least: form the operation of resin molding in the operation of carrying out finishing on the insulated substrate, on this insulated substrate, by this resin molding being formed operation that figure forms the recess of accommodating electrode or distribution, paying the operation of catalyst, operation that this resin molding is heating and curing, utilize coating process to form the operation of conductive material at this recess to this recess.The conductive metal layer of gate electrode etc. for example forms the Cu layer by the electroless plating method, utilize selectable CVD (Chemical VaporDeposition) method thereon and form the W layer and suppress layer as the diffusion of Cu or utilize the electroless plating method and form the Ni layer, be used as gate electrode like this.
According to this method, gate electrode is enhanced the being adjacent to property of substrate, even and the gate electrode of width 20 μ m, length 50 μ m, also can irrespectively form the figure of hope with size.Even but the surface of recognizing this method gate electrode is also coarse, the gate insulator flatness that forms on the gate electrode is also bad.For example the flatness of the Cu laminar surface that is formed by the electroless plating method is that Ra is that 17.74nm, peak-valley also reach 193.92nm, and it is that Ra is that 8.58nm, peak-valley are 68.7nm that the Ni laminar surface that forms on it also becomes flatness.Because this rough surface, so the silicon nitride surface that forms as gate insulating film and by the CVD method is promptly also coarse with the interface of the passage area of semiconductor layer, the result who recognizes diffusion into the surface is the degree of excursion deterioration of charge carrier.Prevent the interfacial diffusion of charge carrier in order in the interface of gate insulating film and passage area, to keep flatness, the surface flatness that just need make gate electrode be Ra below the 1nm, peak-valley is below 20nm.
In the patent documentation 3 be as the method motion that solves distribution surface problem of rough: utilize punch components to push dielectric film and imbed distribution add that drop stamping is handled or the operation that CMP handles.But the substrate size along with mother glass (マ ザ-ガ ラ ス) maximizes in recent years, and particularly in the glass substrate of the above size of the 5th generation 1100mm * 1300mm, these make the method for distribution planarization become unrealistic.The small glass deformation that adds the drop stamping processing can be caused breakage, and the large-size glass substrate of CMP evenly grinds very difficulty, the increase that brings cost comprehensively.
And also be observed at coating and the phenomenon that produces the gap on every side between the resin molding.High temperature when reason is thought the coating processing expands resin, and coating forms the cause of after-contraction.If there is a this gap, then gate insulating film occurs that electric field is concentrated and to produce insulation destroyed, gate electrode and passage area short circuit.
Summary of the invention
The object of the present invention is to provide a kind of good thin-film transistor (TFT) and manufacture method thereof of flatness of gate insulating film.
Other purposes of the present invention be to provide a kind of solved the gate electrode surface roughness and with the semiconductor device and the manufacture method thereof of the clearance issues of insulating barrier on every side.
Other purposes again of the present invention are to provide a kind of display unit and manufacture method thereof with the good thin-film transistor of interface flatness.
Below put down in writing form of the present invention.
(first form)
The semiconductor device of first form then has according to the present invention: substrate, be arranged on this substrate and have groove insulator layer, be arranged in this groove and make its surface and the surperficial general planar of described insulator layer conductor layer, be arranged on dielectric film on this conductor layer, above at least a portion of this conductor layer and the semiconductor layer that on this dielectric film, is provided with, wherein, described dielectric film has the insulator coating film.
(second form)
In the semiconductor device of described first form, described dielectric film only is made of described insulator coating film.
(the 3rd form)
In the semiconductor device of described first form, described dielectric film also can have other insulator film.
(the 4th form)
In the semiconductor device of described the 3rd form, described other insulator film insulator cvd film preferably.
(the 5th form)
In the semiconductor device of described the 3rd form, described other insulator film is arranged between described insulator coating film and the described semiconductor layer.
(the 6th form)
In the semiconductor device of described the 3rd form, described other insulator film also can be arranged between described insulator coating film and the described conductor layer.
(the 7th form)
In the semiconductor device of described first form, the part of described conductor layer is a gate electrode, and the described dielectric film on this gate electrode is a gate insulating film, and described semiconductor layer is arranged on the described gate insulating film.
(the 8th form)
In the semiconductor device of described the 7th form, at least one of source electrode and drain electrode is electrically connected with described semiconductor layer.
(the 9th form)
The semiconductor device of the 9th form according to the present invention, insulator layer on the substrate is provided with groove, in this groove, form gate electrode so that the surperficial general planar of its surface and described insulator layer as conductor layer, on this gate electrode via gate insulating film the configuring semiconductor layer, at least one of source electrode and drain electrode is electrically connected with this semiconductor layer, wherein, has the insulator cvd film that described gate insulating film is arranged on the insulator coating film on the described gate electrode and forms thereon.
(the tenth form)
The described the 7th or the semiconductor device of the 9th form in, its surperficial flatness of described insulator coating film is that Ra is below the 1nm, peak-valley is below the 20nm.
(the 11 form)
The described the 7th or the semiconductor device of the 9th form in, its surperficial flatness of described gate electrode is that Ra is more than the 3nm, peak-valley is more than the 30nm.
(the 12 form)
Described first or the semiconductor device of the 9th form in, described substrate comes down to transparent insulator substrate, described insulator layer comes down to transparent resin bed.
(the 13 form)
In the semiconductor device of described the 12 form, described resin bed is formed by the photosensitive resin composition that contains alkali-soluble alicyclic olefin resinoid and sense ray composition.
(the 14 form)
In the semiconductor device of described the 12 form, described resin bed has more than one the resin of selecting from the group who is constituted by propylene resin, silicon resinoid, fluorine-type resin, polyimide based resin, polyolefin resin, ester ring type olefine kind resin and epoxylite.
(the 15 form)
The described the 7th or the semiconductor device of the 9th form in, described gate electrode has substrate at least and is adjacent to layer, conductive metal layer, conducting metal diffusion and suppresses layer.
(the 16 form)
Described first or the semiconductor device of the 9th form in, described insulator coating film is the gap landfill between described conductor layer and the described insulator layer and extend on the surface of described insulator layer.
(the 17 form)
The described the 7th or the semiconductor device of the 9th form in, described insulator coating film comes down to transparent, the gap landfill between described gate electrode and the described insulator layer and extend on the surface of described insulator layer.
(the 18 form)
The described the 4th or the semiconductor device of the 9th form in, described insulator cvd film comes down to transparent, and extends on the described insulator coating film that extends on the surface of described insulator layer.
(the 19 form)
Described first or the semiconductor device of the 9th form in, described insulator coating film is the liquid coated film drying that makes at least a compound that contains metallo-organic compound and metal inorganic compound and solvent, fire and the film that obtains.
(the 20 form)
Described first or the semiconductor device of the 9th form in, described insulator layer comes down to transparent resin bed, and described insulator coating film is to make the film that the liquid coated film of at least one and the solvent that contain metallo-organic compound and metal inorganic compound is dry and obtain firing below 300 ℃.
(the 21 form)
Described first or the semiconductor device of the 9th form in, the dielectric constant of described insulator coating film is preferred more than 2.6.
(the 22 form)
The described the 4th or the semiconductor device of the 9th form in, the dielectric constant of described insulator cvd film is preferred more than 4.
(the 23 form)
The described the 7th or the semiconductor device of the 9th form in, the thickness of described gate insulating film press EOT (silicon dioxide conversion) preferably 95nm to 200nm.
(the 24 form)
The described the 4th or the semiconductor device of the 9th form in, the thickness of described insulator cvd film press EOT (silicon dioxide conversion) preferably 80nm to 185nm.
(the 25 form)
Described first or the semiconductor device of the 9th form in, the thickness of described insulator coating film press EOT (silicon dioxide conversion) preferably 15nm to 120nm.
(the 26 form)
In the semiconductor device of described the 15 form, described conductive metal layer has at least one of Cu, Ag, and described conducting metal diffusion suppresses layer to have from the metal of any selection of Ni, W, Ta, Nb, Ti.
(the 27 form)
According to the present invention, can access the display unit of the semiconductor device manufacturing of using the described first or the 9th form.
(the 28 form)
In the display unit of described the 27 form, described display unit is liquid crystal indicator or organic EL display.
(the 29 form)
The manufacture method of the semiconductor device of the 29 form according to the present invention, wherein, comprising: form conductor layer in the operation that the insulator layer with groove is set on the substrate, in this groove so that the operation of its surface and the surperficial general planar of described insulator layer, forming the operation of insulator coating film on this conductor layer, at least a portion of described insulator coating film, forming the operation of semiconductor layer.
(the 30 form)
In the manufacture method of described the 29 form, before or after the operation that forms described insulator coating film, also can have the operation that forms other insulator films.
(the 31 form)
In the manufacture method of described the 29 form, preferably form described other insulator film by CVD.
(the 32 form)
In the manufacture method of described the 29 form, also can be the part of described conductor layer as gate electrode, the at least a portion of the described insulator coating film on this gate electrode, described semiconductor layer is arranged on the described gate insulating film as gate insulating film.
(the 33 form)
In the manufacture method of described the 29 form, also has at least one the operation that described semiconductor layer forms source electrode and drain electrode.
(the 34 form)
In the manufacture method of the semiconductor device of the present invention's the 34 form, wherein, comprising: form gate electrode in the operation that the insulator layer with groove is set on the substrate, in this groove so that the operation of its surface and the surperficial general planar of described insulator layer, the operation that forms the insulator coating film on this gate electrode, utilize CVD on described insulator coating film, form the operation of dielectric film, on described dielectric film the formation semiconductor layer operation, at least one operation that is electrically connected with this semiconductor layer of source electrode and drain electrode.
(the 35 form)
In the manufacture method of the present invention the 32 or the 34 form, the operation that forms described insulator coating film has: the operation of the operation that the liquid material of at least a compound that contains metallo-organic compound and metal inorganic compound and solvent is coated with on described gate electrode, the film drying that makes coating, the operation that dry film is fired.
(the 36 form)
In the manufacture method of the present invention the 32 or the 34 form, the operation that forms described gate electrode has the operation of utilizing coating process, print process, ink-jet method or splash method to form conductive metal layer.
(the 37 form)
In the manufacture method of the present invention's the 35 form, the operation that forms described insulator coating film has makes described liquid material the gap landfill between described gate electrode and the described insulator layer, and extends the operation of coating on the surface of described insulator layer.
(the 38 form)
In the manufacture method of the present invention the 29 or the 34 form, have: on described substrate, form the operation of resin molding, by this resin molding being formed the operation that figure is formed for accommodating the groove of described gate electrode in the operation that the insulator layer with groove is set on the described substrate.
(the 39 form)
In the manufacture method of the present invention's the 35 form, fired in inert gas environment or atmospheric environment is carried out described.
(the 40 form)
Can also obtain the manufacture method of liquid crystal indicator or organic EL display according to the present invention, it has the operation that the manufacture method of using the present invention the 29 or the 34 form forms semiconductor device.
According to the present invention, can make its surperficial flatness by on shaggy gate electrode the insulator coating film being set be that Ra is, peak-valley is below the 20nm below the 1nm.Consequently can be the flattening surface of gate insulating film, flatten smooth with the interface of passage area and prevent the interfacial diffusion of charge carrier, reach high charge carrier degree of excursion.And the gap landfill between the insulating barrier around gate electrode and its, provide from gate electrode to reach flat surfaces on the surface of insulating layer, can prevent the destroyed of gate insulating film.
Description of drawings
Fig. 1 is the profile of expression first embodiment of the invention thin-film transistor structure one example;
Fig. 2 amplifies the profile of expression to gate electrode bilge construction one example of thin-film transistor shown in Figure 1;
Fig. 3 is used for the profile of method for fabricating thin film transistor shown in Figure 1 one example by the process sequence explanation;
Fig. 4 is used for the profile of method for fabricating thin film transistor shown in Figure 1 one example by the process sequence explanation;
Fig. 5 is used for the profile of method for fabricating thin film transistor shown in Figure 1 one example by the process sequence explanation;
Fig. 6 is used for the profile of method for fabricating thin film transistor shown in Figure 1 one example by the process sequence explanation;
Fig. 7 is used for the profile of method for fabricating thin film transistor shown in Figure 1 one example by the process sequence explanation;
Fig. 8 is the figure of the photo of outer coating film FIB section in the expression first embodiment of the invention thin-film transistor;
Fig. 9 is the profile of expression second embodiment of the invention thin-film transistor structure one example;
Figure 10 amplifies the profile of expression to gate electrode bilge construction one example of thin-film transistor shown in Figure 9;
Figure 11 is used for the profile of method for fabricating thin film transistor shown in Figure 9 one example by the process sequence explanation;
Figure 12 is used for the profile of method for fabricating thin film transistor shown in Figure 9 one example by the process sequence explanation;
Figure 13 is used for the profile of method for fabricating thin film transistor shown in Figure 9 one example by the process sequence explanation;
Figure 14 is used for the profile of method for fabricating thin film transistor shown in Figure 9 one example by the process sequence explanation;
Figure 15 is used for the profile of method for fabricating thin film transistor shown in Figure 9 one example by the process sequence explanation;
Figure 16 is the profile of expression third embodiment of the invention thin-film transistor structure one example;
Figure 17 is the figure of the photo of outer coating film FIB section in the expression second embodiment of the invention thin-film transistor.
Embodiment
Use figure illustrates the first embodiment of the present invention.
[first embodiment]
Fig. 1 is suitable for liquid crystal indicator, is the profile of expression thin-film transistor of the present invention (TFT:Thin FilmTransistor) structure one example.With reference to Fig. 1, thin-film transistor has: the transparent resin film (insulator layer) 11, the transparent resin film 11 that are made of transparent photoresist that forms on glass substrate (insulated substrate) 10 forms reaches glass substrate 10 and is formed into and transparent resin film 11 gate electrode of sustained height (conductor layer) 12 roughly.Thin-film transistor also has: the gate insulating film 13 by insulator coating film (outer coating film) 131 and 132 formations of CVD dielectric film (insulator cvd film) thereon that forms on whole transparent resin film 11 and gate electrode 12, the semiconductor layer 14, the source electrode 15 that is connected with semiconductor layer 14 and the drain electrode 16 that form on gate electrode 12 via gate insulating film 13.
Fig. 2 is the profile that the gate electrode bilge construction of the first embodiment thin-film transistor is amplified expression.Illustrated gate electrode 12 is embedded in the smooth transparent resin film 11 formed grooves, and begin to include to semiconductor layer side (promptly from figure below beginning order) from glass substrate 10 sides: substrate is adjacent to layer 121, catalyst layer 122, conductive metal layer 123 and conducting metal diffusion and suppresses layer 124.As shown in the figure, the surface of the surface of gate electrode 12 and transparent resin film 11 being formed roughly is that same plane earth is embedded in the groove of transparent resin film 11.Therefore, the flatness of gate electrode 12 superstructures guaranteed, but microcosmic when seeing then flatness problem is arranged.Promptly, the flatness on the conductive metal layer 123 of electroless plating (Cu layer) surface was that Ra is that 17.74nm, peak-paddy (P-V) value also reach 193.92nm in the past, and the surface flatness that the conducting metal diffusion that forms thereon suppresses layer 124 (electroless plating Ni layers) is that 8.58nm, peak-valley are 68.7nm for Ra also.
The present invention forms the insulator coating film 131 of thickness 40nm on gate electrode 12 and transparent resin film 11.This insulator coating film 131 is gap 112 landfills between gate electrode 12 and the transparent resin film 11, and the Ra that does not reflect gate electrode 12 concave-convex surfaces is provided is that 0.24nm, peak-valley are the flat surfaces of 2.16nm.Even the flatness on gate electrode surface is Ra is that 3nm is above, peak-valley is more than the 30nm, and it is that 1nm is following, peak-valley is the following value of 20nm that these values also fully satisfy the desired Ra of insulator coating film.
Fig. 8 utilizes FIB processing to the structure that forms insulator coating film (outer coating film) on gate electrode of coating distribution, and the electron micrograph of section situation is observed in expression.As shown in Figure 8, recognize that formation does not rely on the flat surfaces of substrate roughness degree.
Consequently, utilizing the surface energy of the silicon nitride dielectric film (CVD dielectric film) 132 of thickness 150～160nm that the CVD method forms on insulator coating film (outer coating film) 131 to access Ra is that 0.70nm, peak-valley are the flatness (Fig. 2) of 7.54nm.This result becomes thin-film transistor (TFT) owing to can make the semiconductor layer that forms not produce the sag and swell that is caused by gate electrode on gate insulating film 13, so can increase substantially the degree of excursion of charge carrier.
Can use SOG (spin-on glasses method ス ピ Application オ Application ガ ラ ス) as insulator coating film (outer coating film) 131.Sog film can wait according to the silicone component that becomes film with as the alcoholic content of solvent and adjust.Being coated with on this soln using rotary coating normal direction substrate, make evaporations such as solution by heat treatment, when solidifying, film just forms the SOG dielectric film.Said SOG is the general name of the film of these solvents and formation.SOG is classified as according to the structure of siloxanes: quartz glass, alkyl siloxane polymer, alkyl silsesquioxane polymer (MSQ), hydrogen silsesquioxanes polymer (HSQ), hydrogenation alkyl silsesquioxane polymer (HOSQ).If according to the coating material classification, then silex glass is the inorganic SOG of the first generation, alkyl siloxane polymer is the organic SOG of the first generation, and HSQ is the inorganic SOG of the second generation, and MSQ and HOSQ are the organic SOG of the second generation.Explanation about coated film is that how these are firing more than 500 ℃, owing to can not set high temperature for, are below 300 ℃ so use firing temperature when using any transparent resin layer.Replace above such Si organic compound, Si inorganic compound, also can use at least one to be dissolved as (particularly firing temperature is below 300 ℃) of organic solvent other organo-metallic compounds, metal inorganic compound.Can exemplify Ti, Ta, Al, Sn, Zr etc. as other metals.
At this, if the thickness of the gate insulating film 13 that is made of insulator coating film 131 and the CVD dielectric film 132 on it is blocked up, then transistorized driving force worsens, and, the grid capacity causes signal delay owing to increasing, so under the situation of silicon nitride dielectric film about preferred 350～360nm below, EOT is below the 200nm.So-called EOT uses the dielectric constant of the average dielectric constant of film divided by silicon dioxide, and its merchant be multiply by the resulting silicon dioxide conversion membrane of film thickness thickness.If the thickness of gate insulating film 13 is thin excessively, and then leakage current increases, because if common liquid crystal indicator then is added between the grid and source electrode of TFT with the voltage of maximum 15V, so more than the preferred withstand voltage 15V, therefore preferred EOT is more than the 95nm.
The thickness of insulator coating film 131 is for the flat surfaces that obtains not relying on the substrate roughness degree (when the surface roughness of substrate is that peak-valley is when being the 30nm left and right sides), then its physics film thickness subsistence level 40nm.The dielectric constant of this film has difference, but when considering that the dielectric constant maximum is 10 left and right sides, preferably EOT is more than the 15nm.And preferably the highest film thickness be about 120nm below.
The thickness of CVD dielectric film 132, withstand voltage be main to consider that when introducing in this film, then preferred EOT is more than the 80nm, its upper limit is preferably set to 200nm-15nm=185nm.The 3rd embodiment is not formed in CVD dielectric film 132 on the insulator coating film 131 like that and is formed in downside as described later yet, and also second embodiment omits like that as described later.
The dielectric constant of preferred insulator coating film 131 is more than 2.6, and the dielectric constant of CVD dielectric film 132 is more than 4.0.
Below use figure the formation method of the above-mentioned first embodiment thin-film transistor is described.
Fig. 3～Fig. 7 is the ideograph that the first embodiment method of manufacturing thin film transistor is represented by process sequence.At first, prepare glass substrate 10 as substrate with reference to Fig. 3.As this glass substrate also can be in order to form the large substrate of large-scale picture more than 30 inches.This glass substrate was carried out for 10 seconds with the hydrofluoric acid aqueous solution of 0.5% volume handle, wash the pollution on surface cleaned with pure water and remove.Then, by adding NaOH pH is controlled at that the concentration dissolving silane coupling agent with 0.1% volume is the aminopropyl Ethoxysilane in 10 the aqueous solution to pure water, glass substrate 10 is handled with such silane coupling agent solution, promptly, make glass baseplate surface absorption silane coupling agent at room temperature with this silane coupling agent solution impregnation 30 minutes.On heating plate, handled 60 minutes then, make silane coupling agent and glass baseplate surface chemical bond, become substrate and be adjacent to layer (thickness 10nm) 121 with 110 ℃.Be adjacent to layer 121 by such formation substrate, come down in glass substrate 10 surface configuration amino, the structure that can make the easy coordination of metal complex.Because silane coupling agent is normally transparent, so even be formed on whole of glass substrate 10 and also can access effect of the present invention, and be preferred according to the viewpoint that obtains transparent the being adjacent to property of photoresist that glass substrate 10 and back operation use.
After forming substrate and being adjacent to layer 121, use circulator the basad surface coated that is adjacent to layer 121 of positive photosensitive liquid, by on heating plate with 100 ℃ of heating preliminary drying heat treatments of carrying out for 120 seconds, formation has the photonasty transparent resin film 11 of 2 μ m thickness.Above-mentioned positive photosensitive liquid use patent documentation 4 (spy opens the 2002-296780 communique) record to contain the alkali-soluble alicyclic olefin resinoid.As the organic material that forms hyaline membrane, can use the transparent resin of from the group who constitutes by propylene resin, silicon resinoid, fluorine-type resin, polyimide based resin, polyolefin resin, ester ring type olefine kind resin and epoxylite, selecting.But, later operation is easy to viewpoint according to being become, is to be fit to as hyaline membrane with the photonasty transparent resin film that contains alkali-soluble alicyclic olefin resinoid and sense ray composition, particularly as patent documentation 4 or patent documentation 5 (spy opens the 2001-188343 communique) describe in detail, preferred usability photosensitiveness transparent resin constituent.
With reference to Fig. 4, form photonasty transparent resin film 11 after, utilize the mask alignment device and via mask pattern the mixed light of g, h, i line selectively to 11 irradiations of photonasty transparent resin film.Then, use the tetramethyl ammonium hydroxide aqueous solution of 0.3% weight to carry out 90 seconds development, the flushing of carrying out 60 seconds with pure water is afterwards handled, and forms the groove with compulsory figure on glass substrate 10.In nitrogen environment, carry out 230 ℃, 60 minutes heat treatment then, photonasty transparent resin film 11 is solidified.Then it was flooded 3 minutes with room temperature in palladium bichloride-aqueous hydrochloric acid solution (palladium bichloride 0.005% volume, hydrochloric acid 0.01% volume), use reducing agent (going up village's industry (strain) system reducing agent MAB-2) to handle washing again, in the groove that forms, pay palladium catalyst (catalyst layer: thickness 10～50nm) 122 selectively.
With reference to Fig. 5, the substrate of having been paid palladium catalyst 122 is immersed in the copper electroless plating liquid (going up village's industry (strain) system PGT), in described groove, form copper layer 123 (conductive metal layer: thickness 1.9 μ m) selectively.Copper layer 123 only is preferably the amount with the anti-diffusion film that continues (the conducting metal diffusion suppresses layer) 124 film thicknesses, and intact in the position lower than the apparent height of photonasty transparent resin film 11
Handle.Then, be immersed in the nickel electroless plating liquid, on copper layer 123, form the anti-diffusion film 124 (thickness 0.1 μ m) of nickel.At this, preferred conductive metal layer 123 has at least one of Cu and Ag, and anti-diffusion film (the conducting metal diffusion suppresses layer) 124 has the metal of selecting from any of Ni, W, Ta, Nb, Ti.Conductive metal layer also can form by print process, ink-jet method or splash method except coating process.For example, under the situation of splash method, metal outside Cu and Ag with A1 for being fit to, can omit anti-diffusion film (the conducting metal diffusion suppresses layer) in that the situation of using A1 is next.
With reference to Fig. 6, then, extend to photonasty transparent resin film 11 from gate electrode 12 surfaces and form insulator coating film 131 outwardly.Insulator coating film 131 is following obtaining: coating is the Si organic compound that organosiloxane is dissolved in the liquid in the organic solvent (propylene glycol monomethyl ether), keep making in 90 seconds drying with 120 ℃ in atmosphere, then (also can in nitrogen) carries out firing in 1 hour with 180 ℃ in atmosphere.In microwave-excitation RLSA plasma treatment appts, make Si then
3N
4Film (silicon nitride dielectric film) 132 carries out the CVD growth, makes gate insulating film 13.Utilize known PECVD (Plasma Enhanced Chemical Vapor Deposition) method to pile up amorphous silicon film 141, n+ type amorphous silicon film 142 continuously then, utilize photoetching process and known RIE (Reactive IonEtching) method on the gate electrode 12 and periphery remove, the part of amorphous silicon film is removed.
With reference to Fig. 7, then utilize known splash method etc. to carry out film forming with as source electrode and drain electrode by the order of Ti, Al, Ti, utilize photoetching process to form figure, form source electrode 15 and drain electrode 16.Then, source electrode 15 that forms and drain electrode 16 are utilized known method corrosion n+ type amorphous silicon film 142 as mask, the source region is separated with the drain region.Then utilize the silicon nitride film (not shown) of known PECVD method formation, finish the thin-film transistor of first embodiment as diaphragm.
[second embodiment]
Use figure illustrates the second embodiment of the present invention.
Fig. 9 is suitable for liquid crystal indicator, is the profile of expression second embodiment of the invention thin-film transistor (TFT) structure.Thin-film transistor has: the transparent resin film 11 that is made of transparent photoresist that forms on glass substrate (insulated substrate) 10, what form on transparent resin film 11 reaches glass substrate 10 and is formed into and transparent resin film 11 gate electrode 12 of sustained height roughly, the gate insulating film 133 that constitutes by the insulator coating film that on whole transparent resin film 11 and gate electrode 12, forms, the semiconductor layer 14 that on gate electrode 12, forms via gate insulating film 133, source electrode 15 that is connected with semiconductor layer 14 and drain electrode 16.
Figure 10 is the profile that the gate electrode bilge construction of the second embodiment thin-film transistor is amplified expression.Illustrated gate electrode 12 begins to include to semiconductor layer side (promptly from figure below beginning order) from glass substrate 10 sides: substrate is adjacent to layer 121, catalyst layer 122, conductive metal layer 123 and conducting metal diffusion and suppresses layer 124.Gate electrode 12 is embedded in the smooth transparent resin film 11 formed grooves.As shown in the figure, the surface of the surface of gate electrode 12 and transparent resin film 11 being formed roughly is that same plane earth is embedded in the groove of transparent resin film 11.Therefore, though the flatness of gate electrode 12 superstructures guaranteed, when microcosmic is seen then flatness problem is arranged.Promptly, the flatness on the conductive metal layer 123 that is formed by electroless plating (Cu layer) surface was that Ra is that 17.74nm, peak-valley also reach 193.92nm in the past, and the surface flatness that the conducting metal diffusion that forms thereon suppresses layer 124 (electroless plating Ni layers) is that 8.58nm, peak-valley are 68.7nm for Ra also.
The present invention suppresses to form on the layer 124 the insulator coating film (gate insulating film) 133 of thickness 250nm in the conducting metal diffusion.Utilize this insulator coating film 133 gap 112 landfills between gate electrode 12 and the transparent resin film 11, and the Ra that has that does not reflect gate electrode 12 concave-convex surfaces can be provided is that 0.30nm, peak-valley are the gate insulating films of 3.55nm flat surfaces.Figure 17 is the structure that forms the gate insulating film of insulator coating film on this gate electrode, and the electron micrograph of section situation is observed in expression.As shown in figure 17, recognize that formation does not rely on the flat surfaces of substrate roughness degree.
Consequently, can make the semiconductor layer that on gate insulating film, forms not produce the sag and swell that causes by gate electrode 12 and become thin-film transistor (TFT).Thus, can increase substantially the degree of excursion of charge carrier, and in the film formation process of gate insulating film, omit the CVD operation that is used to form the CVD dielectric film, carry out film forming, can realize the simplification of operation with easy painting process.
Below use figure the formation method of the above-mentioned second embodiment thin-film transistor is described.
Figure 11～Figure 15 is the ideograph that the second embodiment method of manufacturing thin film transistor is represented by process sequence.At first, prepare glass substrate 10 as substrate with reference to Figure 11.As this glass substrate also can be in order to form the large substrate of large-scale picture more than 30 inches.This glass substrate is carried out the hydrofluoric acid aqueous solution of 0.5% volume and handle for 10 seconds, wash a pollution on surface to clean with pure water and remove.Then, by adding NaOH pH is controlled at that the concentration dissolving silane coupling agent with 0.1% volume is the aminopropyl Ethoxysilane in 10 the aqueous solution to pure water, glass substrate 10 is handled with such silane coupling agent solution, promptly, make glass substrate 10 surface adsorption silane coupling agents at room temperature with silane coupling agent solution impregnation 30 minutes.On heating plate, handled 60 minutes then, silane coupling agent is combined with glass substrate 10 surface chemistries, become substrate and be adjacent to layer (thickness 10nm) 121 with 110 ℃.Be adjacent to layer 121 by such formation substrate, come down to have disposed amino, can make the structure of the easy coordination of metal complex at substrate surface.Because silane coupling agent is normally transparent, so even be formed on whole of glass substrate 10 and also can access effect of the present invention, and according to the viewpoint that obtains transparent the being adjacent to property of photoresist that glass substrate 10 and back operation use, preferred.
After the formation substrate is adjacent to layer 121, use circulator the basad surface coated that is adjacent to layer 121 of positive photosensitive liquid, by handling with 100 ℃ of heating preliminary dryings that carried out for 120 seconds on heating plate, formation has the photonasty transparent resin film 11 of 2 μ m thickness.Above-mentioned positive photosensitive liquid use patent documentation 4 records to contain the alkali-soluble alicyclic olefin resinoid.As the organic material that forms hyaline membrane, can use the transparent resin of from the group who constitutes by propylene resin, silicon resinoid, fluorine-type resin, polyimide based resin, polyolefin resin, ester ring type olefine kind resin and epoxylite, selecting.But according to later operation being become be easy to viewpoint, as hyaline membrane with the photonasty transparent resin film for being fit to, particularly as patent documentation 4 or patent documentation 5 describes in detail, preferred usability photosensitiveness transparent resin constituent.
With reference to Figure 12, form photonasty transparent resin film 11 after, utilize the mask alignment device and via mask pattern the mixed light of g, h, i line selectively to 11 irradiations of photonasty transparent resin film.Then, use the tetramethyl ammonium hydroxide aqueous solution of 0.3% weight to carry out 90 seconds development, the flushing of carrying out 60 seconds with pure water is afterwards handled, and forms the groove with compulsory figure on glass substrate 10.In nitrogen environment, carry out 230 ℃, 60 minutes heat treatment then, photonasty transparent resin film 11 is solidified.Then it was flooded 3 minutes with room temperature in palladium bichloride aqueous hydrochloric acid solution (palladium bichloride 0.005% volume, hydrochloric acid 0.01% volume), use reducing agent (going up village's industry (strain) system reducing agent MAB-2) to handle washing again, in the groove that forms, pay palladium catalyst (catalyst layer: thickness 10～50nm) 122 selectively.
With reference to Figure 13, the glass substrate 10 of having been paid palladium catalyst 122 is immersed in the copper electroless plating liquid (going up village's industry (strain) system PGT), in described groove, selectively copper layer 123 (thickness 1.9 μ m) is formed as conductive metal layer.Copper layer 123 only is preferably the amount with the anti-diffusion film that continues (the conducting metal diffusion suppresses layer) 124 film thicknesses, and finishes processing in the position lower than the apparent height of photonasty transparent resin film 11.Then, be immersed in the nickel electroless plating liquid, on copper layer 123, form the anti-diffusion film 124 (thickness 0.1 μ m) that forms by nickel.
With reference to Figure 14, then, extend to photonasty transparent resin film 11 from gate electrode 12 surfaces and be coated with insulator film outwardly to form gate insulating film 133.This gate insulating film 133 is following obtaining: coating is the Si organic compound that organosiloxane is dissolved in the liquid in the organic solvent (propylene glycol monomethyl ether), keep making in 90 seconds drying with 120 ℃ in atmosphere, then (also can in nitrogen) carries out firing in 1 hour with 180 ℃ in atmosphere.Utilize known PECVD method to pile up amorphous silicon film 141, n+ type amorphous silicon film 142 continuously then, utilize photoetching process and known RIE method on the gate electrode 12 and periphery remove, the part of amorphous silicon film is removed.
With reference to Figure 15, then utilize known splash method etc. to carry out film forming with as source electrode and drain electrode by the order of Ti, Al, Ti, utilize photoetching process to form figure, form source electrode 15 and drain electrode 16.Then, source electrode 15 that forms and drain electrode 16 are utilized known method corrosion n+ type amorphous silicon film 142 as mask, the source region is separated with the drain region.Then utilize the silicon nitride film (not shown) of known PECVD method formation, finish the thin-film transistor of second embodiment as diaphragm.
[the 3rd embodiment]
Use Figure 16 that the formation method of the 3rd embodiment thin-film transistor that is suitable for liquid crystal indicator is described.
In the method for manufacturing thin film transistor of second embodiment explanation, on copper layer 123, form the anti-diffusion film 124 (thickness 0.1 μ m) of nickel, after forming gate electrode 12, reach ground, whole zone, transparent resin film 11 surfaces from gate electrode 12 surfaces and microwave-excitation RLSA plasma treatment appts, make Si
3N
4Film (silicon nitride dielectric film) 132 carries out the CVD growth, forms dielectric film.Then at Si
3N
4Film is coated with on the whole and forms insulator coating film 131, forms gate insulating film 13.This insulator coating film 131 is following obtaining: coating is the Si organic compound that organosiloxane is dissolved in the liquid in the organic solvent (propylene glycol monomethyl ether), keep making in 90 seconds drying with 120 ℃ in atmosphere, then (also can in nitrogen) carries out firing in 1 hour with 180 ℃ in atmosphere.Can reduce and make on the big gate electrode 12 of the surface roughness under it dielectric film (Si that produces by the CVD growth by forming 131 of this insulator coating films
3N
4Film 132) Biao Mian surface roughness, can reduce channel layer is gate insulating film and semiconductor layer rough interface degree.Figure 16 is the profile of thin-film transistor at this moment.
The foregoing description only is illustrated the situation that is fit to liquid crystal indicator, but the present invention can be suitable for various substrates and other wiring substrates based on the formation flat-panel screens screen of organic EL display.
As the material that constitutes distribution, be not only copper, silver, for example also can form indium-tin-oxide such conductive films of metal oxide such as (ITO).
The present invention is applicable to display unit such as liquid crystal indicator, organic El device, inorganic EL device, can maximize these display unit, but also can be applicable to display unit distribution in addition.
Claims (40)
1, a kind of semiconductor device, have: substrate, be arranged on this substrate and have groove insulator layer, be arranged in the described groove so that the conductor layer of its surface and the surperficial general planar of described insulator layer, be arranged on dielectric film on this conductor layer, above at least a portion of described conductor layer and the semiconductor layer that on described dielectric film, is provided with, it is characterized in that
Described dielectric film has the insulator coating film.
2, semiconductor device as claimed in claim 1 is characterized in that, described dielectric film only is made of described insulator coating film.
3, semiconductor device as claimed in claim 1 is characterized in that, described dielectric film also has other insulator film.
4, semiconductor device as claimed in claim 3 is characterized in that, described other insulator film is the insulator cvd film.
5, semiconductor device as claimed in claim 3 is characterized in that, described other insulator film is arranged between described insulator coating film and the described semiconductor layer.
6, semiconductor device as claimed in claim 3 is characterized in that, described other insulator film is arranged between described insulator coating film and the described conductor layer.
7, semiconductor device as claimed in claim 1 is characterized in that, the part of described conductor layer is a gate electrode, and the described dielectric film on this gate electrode is a gate insulating film, and described semiconductor layer is arranged on the described gate insulating film.
8, semiconductor device as claimed in claim 7 is characterized in that, at least one of source electrode and drain electrode is electrically connected with described semiconductor layer.
9, a kind of semiconductor device, insulator layer on substrate is provided with groove, in this groove, gate electrode is formed as conductor layer so that the surperficial general planar of its surface and described insulator layer, on this gate electrode via gate insulating film configuring semiconductor layer, at least one of source electrode and drain electrode is electrically connected with this semiconductor layer, it is characterized in that
Described semiconductor device has the insulator cvd film that described gate insulating film is arranged on the insulator coating film on the described gate electrode and forms thereon.
As claim 1 or 9 described semiconductor devices, it is characterized in that 10, its surperficial flatness of described insulator coating film is that Ra is below the 1nm, peak-valley is below the 20nm.
As claim 7 or 9 described semiconductor devices, it is characterized in that 11, its surperficial flatness of described gate electrode is that Ra is more than the 3nm, peak-valley is more than the 30nm.
12, as claim 1 or 9 described semiconductor devices, it is characterized in that described substrate comes down to transparent insulator substrate, described insulator layer comes down to transparent resin bed.
13, semiconductor device as claimed in claim 12 is characterized in that, described transparent resin bed is formed by the photosensitive resin composition that contains alkali-soluble alicyclic olefin resinoid and sense ray composition.
14, semiconductor device as claimed in claim 12, it is characterized in that described transparent resin layer has more than one the resin of selecting from the group who is constituted by acrylic resin, silicon resinoid, fluorine-type resin, polyimide based resin, polyolefin resin, ester ring type olefine kind resin and epoxylite.
As claim 7 or 9 described semiconductor devices, it is characterized in that 15, described gate electrode has substrate at least and is adjacent to layer, conductive metal layer, conducting metal diffusion inhibition layer.
As claim 1 or 9 described semiconductor devices, it is characterized in that 16, described insulator coating film is the gap landfill between described conductor layer and the described insulator layer and extend on the surface of described insulator layer.
As claim 7 or 9 described semiconductor devices, it is characterized in that 17, described insulator coating film comes down to transparent, the gap landfill between described gate electrode and the described insulator layer and on the surface of described insulator layer, extend.
As claim 4 or 9 described semiconductor devices, it is characterized in that 18, described insulator cvd film comes down to transparent, on the described insulator coating film that extends on the surface of described insulator layer, extend.
As claim 1 or 9 described semiconductor devices, it is characterized in that 19, described insulator coating film is the liquid coated film drying that makes at least a compound that contains metallo-organic compound and metal inorganic compound and solvent, fire and the film that obtains.
20, as claim 1 or 9 described semiconductor devices, it is characterized in that, described insulator layer comes down to transparent resin bed, and described insulator coating film is to make the film that the liquid coated film of at least one and the solvent that contain metallo-organic compound and metal inorganic compound is dry and obtain firing below 300 ℃.
As claim 1 or described semiconductor device, it is characterized in that 21, the dielectric constant of described insulator coating film is more than 2.6.
22, as claim 4 or 9 described semiconductor devices, it is characterized in that the dielectric constant of described insulator cvd film is more than 4.
As claim 7 or 9 described semiconductor devices, it is characterized in that 23, the thickness of described gate insulating film is that 95nm is to 200nm by EOT (silicon dioxide conversion).
As claim 4 or 9 described semiconductor devices, it is characterized in that 24, the thickness of described insulator cvd film is that 80nm is to 185nm by EOT (silicon dioxide conversion).
As claim 1 or 9 described semiconductor devices, it is characterized in that 25, the thickness of described insulator coating film is that 15nm is to 120nm by EOT (silicon dioxide conversion).
26, semiconductor device as claimed in claim 15 is characterized in that, described conductive metal layer has at least one of Cu, Ag, and described conducting metal diffusion suppresses layer to have from the metal of any selection of Ni, W, Ta, Nb, Ti.
27, a kind of display unit of using claim 1 or 9 described semiconductor devices to make.
28, display unit as claimed in claim 27 is characterized in that, described display unit is liquid crystal indicator or organic EL display.
29, a kind of manufacture method of semiconductor device is characterized in that, comprising: on substrate, be provided with the insulator layer with groove operation,
In this groove, form conductor layer so that the operation of its surface and the surperficial general planar of described insulator layer,
On this conductor layer, form the insulator coating film operation,
On at least a portion of described insulator coating film, form the operation of semiconductor layer.
30, the manufacture method of semiconductor device as claimed in claim 29 is characterized in that, has the operation that forms other insulator films before or after the operation that forms described insulator coating film.
31, the manufacture method of semiconductor device as claimed in claim 30 is characterized in that, utilizes the CVD method to form described other insulator film.
32, the manufacture method of semiconductor device as claimed in claim 29, it is characterized in that, the part of described conductor layer as gate electrode, the at least a portion of the described insulator coating film on this gate electrode, described semiconductor layer is arranged on the described gate insulating film as gate insulating film.
33, semiconductor device as claimed in claim 32 is a manufacture method, it is characterized in that, also has at least one the operation that described semiconductor layer forms source electrode and drain electrode.
34, a kind of manufacture method of semiconductor device is characterized in that, comprising:
On substrate, be provided with the insulator layer with groove operation,
In described groove, form gate electrode so that the operation of its surface and the surperficial general planar of described insulator layer,
On described gate electrode, form the insulator coating film operation,
Utilize the CVD method on described insulator coating film, form dielectric film operation,
On described dielectric film, form semiconductor layer operation,
At least one operation that is electrically connected with described semiconductor layer of source electrode and drain electrode.
As the manufacture method of claim 32 or 34 described semiconductor devices, it is characterized in that 35, the operation that forms described insulator coating film has:
The operation that the liquid material of at least one and the solvent that contain metallo-organic compound and metal inorganic compound is coated with on described gate electrode,
Make the film drying of coating operation,
The operation that dry film is fired.
36, as the manufacture method of claim 32 or 34 described semiconductor devices, it is characterized in that, form the operation of described gate electrode
Has the operation of utilizing coating process, print process, ink-jet method or splash method to form conductive metal layer.
37, the manufacture method of semiconductor device as claimed in claim 35, it is characterized in that, the operation that forms described insulator coating film has the operation of coating, and the operation of this coating makes described liquid material the gap landfill between described gate electrode and the described insulator layer and extend on the surface of described insulator layer.
As the manufacture method of claim 29 or 34 described semiconductor devices, it is characterized in that 38, the operation that the insulator layer with groove is set has on described substrate:
On described substrate, form resin molding operation,
By described resin molding being formed the operation that figure is formed for accommodating the groove of described gate electrode.
39, the manufacture method of semiconductor device as claimed in claim 35 is characterized in that, fires the operation of the film of described drying in inert gas environment or in the atmospheric environment.
40, the manufacture method of a kind of liquid crystal indicator or organic EL display is characterized in that, has the operation that the manufacture method of using claim 29 or 34 forms semiconductor device.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP257848/2006 | 2006-09-22 | ||
| JP2006257848 | 2006-09-22 | ||
| JP313492/2006 | 2006-11-20 |
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| CN101506985A true CN101506985A (en) | 2009-08-12 |
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| CNA2007800310951A Pending CN101506985A (en) | 2006-09-22 | 2007-09-21 | Semiconductor device and semiconductor device manufacturing method |
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