CN102956468A - 半导体器件以及包括研磨步骤的制造半导体器件的方法 - Google Patents
半导体器件以及包括研磨步骤的制造半导体器件的方法 Download PDFInfo
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- CN102956468A CN102956468A CN2012103044040A CN201210304404A CN102956468A CN 102956468 A CN102956468 A CN 102956468A CN 2012103044040 A CN2012103044040 A CN 2012103044040A CN 201210304404 A CN201210304404 A CN 201210304404A CN 102956468 A CN102956468 A CN 102956468A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 234
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000227 grinding Methods 0.000 title claims description 25
- 239000000463 material Substances 0.000 claims abstract description 145
- 238000000034 method Methods 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 abstract description 20
- 239000010410 layer Substances 0.000 description 45
- 238000004806 packaging method and process Methods 0.000 description 23
- 239000002390 adhesive tape Substances 0.000 description 11
- 239000004020 conductor Substances 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 229910001092 metal group alloy Inorganic materials 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000004033 plastic Substances 0.000 description 5
- 229920003023 plastic Polymers 0.000 description 5
- 208000037656 Respiratory Sounds Diseases 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000002648 laminated material Substances 0.000 description 2
- 150000002739 metals Chemical group 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000003578 releasing effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000011188 CEM-1 Substances 0.000 description 1
- 239000011189 CEM-2 Substances 0.000 description 1
- 239000011190 CEM-3 Substances 0.000 description 1
- 239000011191 CEM-4 Substances 0.000 description 1
- 239000011192 CEM-5 Substances 0.000 description 1
- 101100257127 Caenorhabditis elegans sma-2 gene Proteins 0.000 description 1
- 101100257133 Caenorhabditis elegans sma-3 gene Proteins 0.000 description 1
- 101100257134 Caenorhabditis elegans sma-4 gene Proteins 0.000 description 1
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 244000287680 Garcinia dulcis Species 0.000 description 1
- 206010019133 Hangover Diseases 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 229910008433 SnCU Inorganic materials 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000005469 granulation Methods 0.000 description 1
- 230000003179 granulation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 239000012764 mineral filler Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 1
- 239000012766 organic filler Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000010136 thermoset moulding Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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Abstract
本发明公开了半导体器件以及包括研磨步骤的制造半导体器件的方法。一种制造器件的方法包括提供具有第一面和与第一面相对的第二面的半导体芯片,其中接触垫被布置在第一面上。所述半导体芯片被放置在载体上,其中第一面面对载体。利用封装材料封装所述半导体芯片。所述载体被移除,并且从第一半导体芯片的第二面移除半导体材料而同时不移除封装材料。
Description
技术领域
本发明涉及半导体器件以及制造半导体器件的方法,其中所述方法包括一个或多个研磨步骤。
背景技术
由于在成本和性能方面的优点,晶片级封装正在整个半导体工业中获得关注。当使用标准晶片级封装技术时,所有技术工艺步骤都在晶片级被执行。因为标准晶片级封装是扇入解决方案,所以在半导体芯片下面仅仅有限数目的接触垫(pad)是可能的。因此,为了放置大量接触垫,半导体芯片可以被设计得更大或者附加材料可以作为围绕管芯的间隔保持器被放置以承载允许扇出再分布的布线。
晶片级封装通常涉及研磨步骤以减小半导体管芯的厚度。然而,任何经研磨的半导体表面都包含裂纹、脊和谷的***。如果施加附加机械应力,则在半导体材料中的这些损坏可能诱发穿过半导体块状材料的裂纹。这种机械应力可能在半导体器件的加工、处理或装运期间或者在应用(例如移动电话)中的使用期间发生。
发明内容
根据本发明的第一方面,提供一种制造器件的方法。所述方法包括:提供第一半导体芯片;将所述第一半导体芯片放置在载体上;在将所述第一半导体芯片放置在所述载体上之后,利用封装材料封装所述第一半导体芯片;移除所述载体;以及在移除所述载体之后,从所述第一半导体芯片移除半导体材料而同时基本上不移除所述封装材料。
根据本发明的第二方面,提供一种制造器件的方法。所述方法包括:提供具有第一面、与第一面相对的第二面以及侧面的半导体芯片,其中接触垫被布置在第一面上;利用封装材料覆盖所述半导体芯片的第二面和侧面;研磨所述封装材料以从所述半导体芯片的第二面移除所述封装材料并且减小所述半导体芯片的厚度,从而产生所述半导体芯片的第二面和所述封装材料的平表面;以及从所述半导体芯片的第二面移除半导体材料,从而在所述半导体芯片的第二面和所述封装材料的所述平表面之间产生间隙。
根据本发明的第三方面,提供一种制造器件的方法。所述方法包括:提供具有第一面和与第一面相对的第二面的半导体芯片,其中接触元件从第一面突出至少1μm;利用封装材料封装所述半导体芯片和所述接触元件;研磨所述封装材料,直至所述接触元件被暴露;以及从所述半导体芯片的第二面移除半导体材料而同时基本上不移除封装材料。
根据本发明的第四方面,提供一种器件。所述器件包括:具有第一面和与第一面相对的第二面的半导体芯片,其中接触垫被布置在第一面上;以及具有第一面和与第一面相对的第二面的封装材料,其中,所述封装材料封装所述半导体芯片,所述半导体芯片的第一面和所述封装材料的第一面是共面的,从而限定平面,以及所述半导体芯片的第二面和所述封装材料的第二面具有处于从3到10μm的范围的高度差。
根据本发明的第五方面,提供一种器件。所述器件包括:具有第一面和与第一面相对的第二面的半导体芯片,其中接触元件从第一面突出至少1μm;以及具有第一面和与第一面相对的第二面的封装材料,其中,所述封装材料封装所述半导体芯片,所述封装材料的第一面和所述接触元件的面限定平面,以及所述半导体芯片的第二面和所述封装材料的第二面具有处于从3到10μm的范围的高度差。
附图说明
附图被包括以提供对实施例的进一步理解,以及附图被结合在本说明书中并构成本说明书的一部分。附图示出实施例,并且与描述一起用来解释实施例的原理。其他实施例以及实施例的许多预期优点将容易被认识到,因为通过参考下面的详细描述,它们变得更好理解。附图的元件相对于彼此不一定是按比例的。相同的附图标记表示对应的类似部分。
图1A-1H示意性地示出制造器件的方法的一个实施例的剖视图,所述方法包括在载体上放置半导体芯片、利用封装材料覆盖半导体芯片、移除载体、研磨半导体芯片和封装材料、形成再分布层、进一步研磨半导体芯片和封装材料、以及减小半导体芯片的厚度;
图2A-2P示意性地示出制造器件的方法的一个实施例的剖视图,所述方法包括产生半导体芯片的扇出型封装、研磨该封装两次、以及在封装和半导体芯片之间产生台阶(step);
图3示意性地示出包括利用封装材料封装的半导体芯片的器件的一个实施例的剖视图;
图4示意性地示出包括安装在电路板上的半导体器件的***的一个实施例的剖视图;以及
图5A-5I示意性地示出制造器件的方法的一个实施例的剖视图,所述方法包括产生包括从半导体芯片突出的接触元件的半导体芯片的扇出型封装、研磨该封装、以及在封装和半导体芯片之间产生台阶。
具体实施方式
在下面的详细描述中参考了形成其一部分的附图,并且其中通过说明的方式示出可以实践本发明的特定实施例。在这方面,参考所描述的(一幅或多幅)附图的取向使用了诸如“顶部”、“底部”、“前”、“后”、“前导”、“拖尾”等等之类的方向术语。由于可以将各实施例的部件定位在许多不同的取向中,因此使用所述方向术语是为了进行说明而绝非进行限制。应当理解,在不背离本发明的范围的情况下,可以利用其他实施例并且可以做出结构或逻辑的改变。因此不应当将下面的详细描述视为进行限制,并且本发明的范围由所附权利要求书来限定。
应当理解,可以将在这里所描述的各种示例性实施例的特征彼此组合,除非另有专门说明。
如在本说明书中所采用的,术语“耦合”和/或“电耦合”并非打算是指,元件必须被直接地耦合到一起;可以在“耦合”或“电耦合”元件之间提供中间元件。
在下面描述了包含半导体芯片的器件。半导体芯片可以属于不同类型,可以通过不同技术来制造,并且可以包括例如集成的电、电光或机电电路或无源元件(passive)。集成电路可以例如被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储器电路或集成无源元件。此外,半导体芯片可以被配置为所谓的MEMS(微机电***),并且可以包括微机械结构,例如桥、膜或舌结构。半导体芯片可以被配置为传感器或致动器,例如压力传感器、加速度传感器、转动传感器、麦克风等等。在其中嵌入这种功能元件的半导体芯片通常包含用于驱动功能元件或者进一步处理由功能元件生成的信号的电子电路。半导体芯片不需要由特定的半导体材料(例如Si、SiC、SiGe、GaAs)制造,并且此外可以包含不是半导体的无机和/或有机材料,举例来说,例如分立的无源元件、天线、绝缘体、塑料或金属。
半导体芯片可以具有接触垫(或电极或接触元件),其允许与包括在半导体芯片中的集成电路进行电接触。接触垫可以包括一个或多个金属层,其被施加到半导体芯片的半导体材料。金属层可以被制造成具有任何期望的几何形状和任何期望的材料成分。金属层可以例如处于覆盖区域的层的形式。任何期望的金属或金属合金(例如铝、钛、金、银、铜、钯、铂、镍、铬或镍钒)都可以被用作该材料。金属层不需要是均质的或者由仅仅一种材料制造,也就是说,在金属层中包含的材料的各种成分和浓度都是可能的。接触垫可以位于半导体芯片的有源主面上或者半导体芯片的其他面上。
具有导体线(或导体迹线(track))的形状的一个或多个金属层可以被提供,并且可以被电耦合到半导体芯片。金属层可以例如被用来产生再分布层。导体线可以作为布线层被采用以与来自器件外部的半导体芯片进行电接触和/或与在器件中包含的其他半导体芯片和/或部件进行电接触。导体线可以将半导体芯片的接触垫耦合到外部接触垫。导体线可以被制造成具有任何期望的几何形状和任何期望的材料成分。任何期望的金属(例如铝、镍、钯、银、锡、金或铜)或金属合金都可以被用作该材料。导体线不需要是均质的或者由仅仅一种材料制造,也就是说,在导体线中包含的材料的各种成分和浓度都是可能的。此外,导体线可以被布置在电绝缘层上方或下方或之间。
在下面描述的器件包括外部接触垫(或外部接触元件),其可以具有任何形状和尺寸。外部接触垫可以是能够从器件外部到达的,并且可以因此允许与来自器件外部的半导体芯片进行电接触。此外,外部接触垫可以是导热的,并且可以用作热沉以用于耗散由半导体芯片生成的热。外部接触垫可以由任何期望的导电材料或者不同材料(例如金属(例如铜、镍、铝或金)、金属合金或导电有机材料)的堆叠构成。外部接触垫可以由金属层的一些部分形成。可以在外部接触垫上沉积焊料材料,例如焊球或焊料块。
半导体芯片或者半导体芯片的至少一些部分可以利用封装材料覆盖,该封装材料可以是电绝缘的并且可以形成封装体。封装材料可以是任何适当的硬质塑料、热塑性或热固性材料或者层压材料(预浸料坯),并且可以包含填充材料。可以采用各种技术以利用封装材料封装半导体芯片,例如压力成型、注射成型、粉末成型、液体成型、层叠或印刷。可以使用热和/或压力来施加封装材料。
封装材料可以被用来产生扇出型封装。在扇出型封装中,外部接触垫和/或将半导体芯片连接到外部接触垫的导体线中的至少一些横向地位于半导体芯片的轮廓外部,或者的确至少与半导体芯片的轮廓交叉。因此,在扇出型封装中,半导体芯片的封装的周界的外部部分通常(另外地)被用于将该封装电接合到外部应用,例如应用板等等。该封装的、包围半导体芯片的这个外部部分相对于半导体芯片的覆盖区有效地扩大了该封装的接触区域,因此导致关于稍后的加工(例如二级组装)在封装垫尺寸和间距方面放松的约束。
图1A-1H示意性地示出制造器件100的方法。在图1H中示出通过该方法获得的器件100的横截面。
图1A示意性地示出载体10。
图1B示意性地示出放置在载体10上的第一半导体芯片11。第一半导体芯片11具有第一面12和与第一面12相对的第二面13。接触垫14被布置在半导体芯片11的第一面侧12上。半导体芯片11被放置在载体10上,其第一面12面对载体10。
图1C示意性地示出封装第一半导体芯片11以形成封装体16的封装材料15。
图1D示意性地示出从封装体16移除载体10。
图1E示意性地示出第一研磨步骤,其中通过从封装体16和第一半导体芯片11的第二面13移除材料来薄化封装体16和第一半导体芯片11。
图1F示意性地示出再分布层17,其被形成在第一半导体芯片11的第一面12和包围第一半导体芯片11的封装材料15上。
图1G示意性地示出第二研磨步骤,其中封装体16和第一半导体芯片11的第二面13被再次研磨。
图1H示意性地示出从第一半导体芯片11的第二面13移除半导体材料而同时基本上未移除封装材料15。
图2A-2P示意性地示出用于制造器件200的方法,器件200的横截面被示出在图2P中。图2A-2P所示的方法是图1A-1H所示的方法的实施。在下面描述的生产方法的细节因此能够同样被应用于图1A-1H的方法。
图2A示意性地示出载体10,载体10可以是由刚性材料(例如金属(例如镍、钢或不锈钢))、层压材料、膜或材料堆叠制成的板。载体10可以具有能够在其上放置器件200的部件的至少一个平坦面。载体10的形状不限于任何几何形状,例如,载体10可以是圆的或方形的。载体10可以具有任何适当的尺寸。
胶带20(例如双面粘性带)可以被层叠到载体10上。胶带20的功能是提供在后续加工步骤期间在载体10上放置的部件的、可释放的固定。代替胶带20,可以采用达到相同功能的任何其他合适的装置。为此,载体10可以具有某种涂层,例如允许从在载体10上放置的部件释放载体10的金或特氟隆涂层。
图2B示意性地示出第一半导体芯片11和第二半导体芯片21,它们被放置在胶带20的顶面上。第一半导体芯片11具有第一面12和与第一面12相对的第二面13。接触垫14被布置在第一面12上。第二半导体芯片21具有第一面22和与第一面22相对的第二面23。接触垫24被布置在第一面22上。两个半导体芯片11、21的第一面12、22都面对载体10。在一个实施例中,半导体芯片11、21具有大约725或775μm的厚度d1,但是其他厚度d1也是可能的。
虽然在图2B中示出仅仅两个半导体芯片11、21,但是可以在载体10上放置任何数目的半导体芯片,例如多于50或500或1000个半导体芯片。半导体芯片可以例如被布置成阵列。当半导体芯片已经处于晶片接合时,它们通常以更大的间隔在载体10上重新定位。半导体芯片可以已被制造在相同的半导体晶片上,但是可以可替换地已被制造在不同的半导体晶片上。此外,半导体芯片可以是物理上相同的,但是还可以包含不同的集成电路和/或代表其他部件。
图2C示意性地示出封装材料15,其被用来封装半导体芯片11、21以及形成封装体16。封装材料15覆盖半导体芯片11、21的第二面13、23和所有的侧面。在一个实施例中,封装材料15是硬质塑料或者热固性模塑材料。在这种情况下,封装材料15可以基于环氧材料,并且可以包含由小玻璃颗粒(SiO2)组成的填充材料或者其他电绝缘矿物填充材料(比如Al2O3)或者有机填充材料。封装材料15可以例如通过压力成型、注射成型、粒化成型、粉末成型或液体成型来施加。
在一个实施例中,封装材料15是由电绝缘聚合物材料制成的片材(sheet)。聚合物材料可以例如是预浸料坯(对于预浸渍纤维而言是短的),预浸料坯是纤维毡(例如玻璃或碳纤维)和树脂(例如硬质塑料材料)的组合。预浸料坯材料通常被用来制造PCB(印刷电路板)。在PCB工业中使用并且能够在这里被用作聚合物材料的众所周知的预浸料坯材料是:FR-2、FR-3、FR-4、FR-5、FR-6、G-10、CEM-1、CEM-2、CEM-3、CEM-4和CEM-5。在一个实施例中,封装材料15是均质的,并且完全由相同的材料制成。因此,在该实施例中,封装材料15包括恰好一个层,而不是以逐层方式制成的。
图2D示意性地示出从载体10释放封装体16。为此,胶带20可以具有热释放性质的特征,该性质允许在热处理期间移除胶带20和载体10。从封装体16移除胶带20和载体10是在适当的温度执行的,该温度取决于胶带20的热释放性质并且通常高于150℃。在移除载体10和胶带20之后,半导体芯片11、21的第一面12、22与封装材料15的第一面一起限定基本上平的表面25。封装材料15具有与平表面25相对的第二面26。
图2E示意性地示出例如通过研磨封装材料15的第二面26来薄化封装体16。在一个实施例中,封装体16在研磨之后具有大约690μm的厚度d2,但是其他厚度d2也是可能的。在研磨过程期间,覆盖半导体芯片11、21的第二面13、23的封装材料15被移除。另外,还通过从它们的第二面13、23移除半导体材料来薄化半导体芯片11、21。
图2F示意性地示出介电层30,其在平表面25上被沉积从而至少部分地覆盖半导体芯片11、21的第一面12、22和封装材料15的顶表面。介电层30具有暴露半导体芯片11、21的接触垫14、24的通孔。可以以各种方式制造介电层30。例如,介电层30可以从气相或从溶液沉积,或者能够在表面25上印刷或层叠。此外,薄膜技术方法(比如旋涂)或者标准PCB工业工艺流程能够被用于施加介电层30。可以由聚合物(例如聚酰亚胺)、PBO、帕利灵、光致抗蚀剂材料、酰亚胺、环氧、环氧树脂、硬质塑料、硅树脂、氮化硅或者无机、类陶瓷材料(例如硅树脂-碳化合物)制造介电层30。介电层30的厚度可以高达10μm或者甚至更高。在一个实施例中,省略了介电层30的沉积。
图2G示意性地示出薄的种子层31,其被沉积到介电层30和接触垫14、24上。种子层31的沉积可以例如通过溅射或者从溶液的无电沉积来执行。种子层31的材料可以是钛、钛钨、铜、钯或任何其他适当的金属、金属堆叠或金属合金。
图2H示意性地示出电镀抗蚀剂32。电镀抗蚀剂32可以是光致抗蚀剂材料层,并且可以被印刷、电镀或旋涂在种子层31的顶表面上。通过经过掩模暴露于具有合适波长的光和后续的显影或者激光施加或者激光直接成像,在电镀抗蚀剂32中形成凹部。
图2I示意性地示出金属层33,其以电方式(galvanically)生长并且增强种子层31的、被电镀抗蚀剂32中的凹部暴露的部分。铜或其他金属或金属合金可以被用作金属层33的材料。在金属材料的电沉积期间,可以采用种子层31作为电极。金属层33具有大于3μm的厚度。
图2J示意性地示出,在金属层33的电镀之后,通过使用适当的溶剂来剥离电镀抗蚀剂32。通过简短的蚀刻步骤来移除尚未用金属层33覆盖的、种子层31的现在暴露的部分,从而产生如在图2J中所示的结构化金属层。
图2K示意性地示出介电层34,其被沉积在金属层33之上并且在特定区域中开口以暴露金属层33的部分。金属层33的暴露部分用作外部接触垫35。可以通过使用与如上结合介电层30所述的相同或者类似的材料和加工步骤来产生介电层34。介电层34具有焊料阻挡层的功能。种子层31和金属层33与介电层30、34一起形成再分布层17。在一个实施例中,省略了介电层34的沉积。
图2L示意性地示出通过研磨封装材料15的第二面26再次薄化封装体16。在研磨过程期间,封装材料15和半导体芯片11、21的半导体材料被同时移除。在研磨之后半导体芯片11、21(和封装材料15)的厚度d3取决于为其设计器件200的应用的要求。在一个实施例中,半导体芯片11、21的厚度d3在研磨之后是大约450μm,但是其他厚度d3也是可能的。在一个实施例中,省略了在图2L中所示的研磨步骤。
图2L还以放大视图示出第二半导体芯片21的一部分。该图示出,半导体芯片11、21的经研磨的半导体表面包含裂纹、脊和谷的***。峰和谷形成缓解层40。缓解层40的下面是由微裂纹、位错、滑移和应力表征的受损层41。如果例如在器件200的加工、处理或装运期间或者在应用(例如移动电话)中的使用期间施加附加应力,则层40和41这二者都可以诱发穿过块状半导体材料42的裂纹。
图2M示意性地示出从半导体芯片11、21移除缓解层40和受损层41。这是在抛光步骤中完成的,该抛光步骤从半导体芯片11、21移除半导体材料但是基本上不移除封装材料15。结果,在抛光步骤之后在半导体芯片11、21的第二面13、23和封装材料15的第二面26之间存在高度差d4(或间隙或台阶)。半导体芯片11、21的第二面13、23和封装材料15的第二面26这二者可以是相互平行的、基本上平的表面。在一个实施例中,高度差d4处于从3到10μm的范围,特别是处于从3到5μm的范围。高度差d4还可以更大,例如处于从3到20μm的范围。移除缓解层40和受损层41引起高得多的力以使半导体芯片11、21的半导体材料破裂。
抛光半导体芯片11、21的第二面13、23可以通过选择性地移除受损半导体材料但是基本上不腐蚀封装材料15的任何技术来执行。这种技术的实例是湿蚀刻和干蚀刻。湿蚀刻涉及将封装体16的表面26暴露于蚀刻剂,该蚀刻剂蚀刻半导体材料而不蚀刻封装材料15,举例来说,例如HF和HNO3。能够使用蚀刻时间和已知的蚀刻速率来控制在半导体芯片11、21中通过蚀刻产生的腔的深度。常常通过使用等离子体蚀刻机来执行干蚀刻。等离子体蚀刻机使用强电场从工艺气体(例如含氟气体)产生等离子体。封装体16被放置在等离子体蚀刻机中,并且使用真空泵***从工艺腔室将空气抽空。然后工艺气体在低压下被引入,并且通过电介质击穿而被激发成等离子体。然而,可以提供,封装材料15包括树脂基质和在树脂基质中嵌入的硅颗粒。在抛光步骤期间,树脂基质不被移除,但是那些硅颗粒与在封装材料15的表面上暴露的半导体芯片11、21的半导体材料一起被移除。
图2N示意性地示出背面保护层43,其被沉积到封装体16的背面上。背面保护层43可以由在封装体16上层叠的适当箔或者使用橡皮滚子(squeegee)涂覆在封装体16的背面上的适当膏剂制成。在一个实施例中,背面保护层43并不再现在封装体16的背面中的台阶。代之以,背面保护层43具有基本上平的表面44。
图2O示意性地示出被放置到外部接触垫35上的焊球45。焊料材料由金属合金形成,该金属合金例如由下列材料构成:SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu和SnBi。焊球45被用来将器件200电耦合到其他部件(例如PCB)。
图2P示意性地示出通过切割封装体16来将器件200相互分开。切割封装体16可以例如通过使用锯、切、铣、蚀刻或激光束来执行。
通过上述方法制造的器件200是扇出型封装。封装材料15允许再分布层17延伸超出半导体芯片11、21的轮廓。外部接触垫35因此不需要被布置在半导体芯片11、21的轮廓内,而是能够在更大的区域上分布。由于封装体16而可用于布置外部接触垫35的增加的区域意味着,外部接触垫35不仅能够以彼此之间大的距离被布置,而且与当所有的外部接触垫35被布置在半导体芯片11、21的轮廓内时的情形相比,能够布置在那里的外部接触垫35的最大数目同样被增加。
对于本领域技术人员而言明显的是,如上所述的图2P所示的器件200及其制造仅仅意图是示例性实施例,并且许多变型是可能的。上述器件200中的每个包含单个半导体芯片。可替换地,可以在相同器件200中包括不同类型的两个或更多个半导体芯片或无源元件。半导体芯片和无源元件可以在功能、尺寸、制造技术等等方面不同。此外,器件200的再分布层17包括仅仅一个导体迹线层。可替换地,可以提供两个或更多个导体迹线层。这些层可以被堆叠在彼此之上,并且介电层可以被布置在相邻的导体迹线层之间。
图3示意性地示出器件300,其类似于图2P所示的器件200。不同之处在于,在器件300中,背面保护层43再现从第一半导体芯片11的第二面13到包围第一半导体芯片11的封装材料15的台阶。在该实施例中,箔被层叠到封装体16上以产生背面保护层43。
图4示意性地示出***400,其包括安装在电路板50(例如PCB)上的器件200。电路板50具有接触垫51,并且器件200借助于焊球45被焊接到接触垫51。
图5A-5I示意性地示出用于制造器件500的方法,器件500的横截面被示出在图5I中。图5A-5I所示的方法类似于图2A-2P所示的方法。相同的附图标记表示对应的类似部分。
图5A示意性地示出如上结合图2A所述的载体10和层叠到载体10上的胶带20。
图5B示意性地示出半导体芯片11和21,它们被放置在胶带20的顶面上。与在图2B中所示的实施例形成对比,半导体芯片11、21的第二面13、23面对载体10。另外,从接触垫14、24突出的接触元件60被布置在半导体芯片11、21上。在一个实施例中,半导体芯片11、21具有大约725或775μm的厚度d1,但是其他厚度d1也是可能的。
接触元件60可以由任何期望的导电材料(例如金属(例如铜)、金属合金、金属堆叠或导电有机材料)构成。接触元件60可以具有从半导体芯片11、21的顶面12、22突出的、在从1到20μm的范围中的高度d5,但是它们可以甚至更大。可以利用任何适当方法产生接触元件60,例如接线柱球焊(stud bumping)、无电电镀或者放置金属柱。
当使用接线柱球焊以用于产生接触元件60时,修改了在常规引线接合中使用的球焊工艺。在球焊中,接合线的尖端被熔化以形成球。引线接合工具朝着所要连接的半导体芯片的接触垫挤压该球,从而施加机械力、热和/或超声能量以产生金属连接。引线接合工具接着将引线延伸到在板、基板或引线框上的接触垫并且与该垫形成“针脚”接合,从而通过断开接合线以开始另一循环而结束。对于接线柱球焊,如所述地在半导体晶片的接触垫上形成第一球焊,但是引线然后邻近球上方断裂。在接触垫14、24上保留的、所得到的球或“接线柱球焊”提供到下面的、接触垫14、24的导电材料的永久的、可靠的连接。
作为对于接线柱球焊的替代,可以利用电化学沉积来产生接触元件60。为此,可以从溶液在接触垫14、24上无电沉积金属层(例如铜)。随后其他金属(例如镍和金)可以被无电沉积到铜层上。此外,还可以采用其他沉积方法,举例来说,例如溅射和/或电沉积。然而,在后一种情况下,结构化步骤可能是必要的。
作为另一替代,预制的金属柱(或支柱)(例如铜柱)可以被安装在接触垫14、24上以形成接触元件60。
图5C示意性地示出封装材料15,类似于在图2C中所示的实施例,其被用来封装半导体芯片11、21。封装材料15覆盖半导体芯片11、21的第一面12、22、接触元件60以及所有的侧面。
图5D示意性地示出通过研磨从封装材料15的上表面移除材料。研磨被执行,直至接触元件60的上表面被从封装材料15暴露。在研磨期间接触元件60的高度被减小也是可能的。在研磨步骤之后,接触元件60可以具有小于20μm、特别是小于10或5μm的高度d6。此外,在研磨步骤之后,接触元件60的上表面和封装材料15的上表面限定公共平面。
图5E示意性地示出再分布层17,其以与如上结合图2F-2K所述的相同或者类似的方式被沉积在封装材料15的上表面上。再分布层17被耦合到接触元件60的暴露部分。
图5F示意性地示出载体10被移除并且通过研磨封装材料15的第二面26再次薄化封装体16。在研磨过程期间,封装材料15和半导体芯片11、21的半导体材料被同时移除。在研磨之后半导体芯片11、21(和封装材料15)的厚度d3取决于为其设计器件500的应用的要求。在一个实施例中,在研磨之后,半导体芯片11、21的厚度d3是大约450μm,但是其他厚度d3也是可能的。
图5G示意性地示出如上结合图2M所述的半导体芯片11、21的第二面13、23被抛光。在抛光步骤期间,从半导体芯片11、21移除半导体材料而基本上不移除封装材料15。结果,在半导体芯片11、21的第二面13、23和封装材料15的第二面26之间产生高度差d4。在一个实施例中,高度差d4处于从3到10μm的范围,特别是处于从3到5μm的范围。高度差d4还可以更大,例如处于从3到20μm的范围。
图5H示意性地示出被沉积到封装材料15的第二面26上的背面保护层43和被放置在外部接触垫35上的焊球45。
图5I示意性地示出封装材料15被切割,从而产生各个器件500。
另外,虽然可能已经相对于几个实施的仅仅一个公开了本发明的实施例的特定特征或方面,但是如可以对于任何给定或特定应用而言期望的并且有利的那样,这种特征或方面可以与其他实施的一个或多个其他特征或方面进行组合。此外,就在详述或权利要求书中使用术语“包括”、“具有”、“具有”或其其他变体来说,这种术语意图以类似于术语“包括”的方式而为包括性的。此外,应当理解,本发明的实施例可以在分立电路、部分集成电路或完全集成电路或编程装置中被实施。而且,术语“示例性”仅仅意味着作为实例,而非最佳或最优。还应认识到,为了简单性和易于理解,在这里描绘的特征和/或元件以相对于彼此的特定尺寸(dimension)被示出,并且实际尺寸可能大大不同于在这里所示的尺寸。
虽然在这里已经示出并描述了特定实施例,但是本领域普通技术人员将认识到,在不背离本发明的范围的情况下可以用多种替换的和/或等同的实施来替代所示出并描述的特定实施例。本申请意图覆盖在这里所讨论的特定实施例的任何适配或变化。因此,本发明意图仅由权利要求书及其等同物来限定。
Claims (25)
1. 一种制造器件的方法,所述方法包括:
提供第一半导体芯片;
将所述第一半导体芯片放置在载体上;
在将所述第一半导体芯片放置在所述载体上之后,利用封装材料封装所述第一半导体芯片;
移除所述载体;以及
在移除所述载体之后,从所述第一半导体芯片移除半导体材料而同时基本上不移除所述封装材料。
2. 根据权利要求1所述的方法,其中,
所述第一半导体芯片具有第一面和与第一面相对的第二面,其中接触垫被布置在第一面上,
将所述第一半导体芯片放置在所述载体上包括:将所述第一半导体芯片放置在所述载体上,其中所述第一半导体芯片的第一面面对所述载体,以及
从所述第一半导体芯片移除半导体材料包括:从所述第一半导体芯片的第二面移除半导体材料。
3. 根据权利要求2所述的方法,还包括:
在利用所述封装材料封装所述第一半导体芯片之后,研磨所述第一半导体芯片的第二面和所述封装材料。
4. 根据权利要求2所述的方法,还包括:
在移除所述载体之后在所述第一半导体芯片的第一面上形成再分布层。
5. 根据权利要求4所述的方法,其中,所述再分布层延伸超出所述第一半导体芯片的轮廓。
6. 根据权利要求4所述的方法,其中,形成再分布层包括:在所述第一半导体芯片的第一面和所述封装材料上电沉积金属层。
7. 根据权利要求4所述的方法,还包括:
在形成所述再分布层之后并且在从所述第一半导体芯片的第二面移除所述半导体材料而同时不移除封装材料之前,研磨所述第一半导体芯片的第二面和所述封装材料。
8. 根据权利要求1所述的方法,还包括:
将第二半导体芯片放置在所述载体上;以及
利用所述封装材料封装所述第二半导体芯片。
9. 根据权利要求8所述的方法,还包括:
切割所述封装材料,从而使所述第一半导体芯片与所述第二半导体芯片分开。
10. 根据权利要求1所述的方法,其中,当从所述第一半导体芯片移除所述半导体材料而同时不移除封装材料时,所述第一半导体芯片的厚度被减小3到10μm。
11. 根据权利要求2所述的方法,其中,在从所述第一半导体芯片的第二面移除所述半导体材料而同时不移除封装材料之后,所述第一半导体芯片的第二面是基本上平的。
12. 根据权利要求2所述的方法,其中,在从所述第一半导体芯片的第二面移除半导体材料而同时不移除封装材料之后,在所述第一半导体芯片的第二面和所述封装材料的上表面之间存在间隙,所述间隙具有处于从3到10μm的范围的高度。
13. 根据权利要求1所述的方法,其中,
所述第一半导体芯片具有第一面和与第一面相对的第二面,其中接触元件从第一面突出至少1μm,
将所述第一半导体芯片放置在所述载体上包括:将所述第一半导体芯片放置在所述载体上,其中所述第一半导体芯片的第二面面对所述载体,以及
从所述第一半导体芯片移除半导体材料包括:从所述第一半导体芯片的第二面移除半导体材料。
14. 一种制造器件的方法,所述方法包括:
提供具有第一面、与第一面相对的第二面以及侧面的半导体芯片,其中接触垫被布置在第一面上;
利用封装材料覆盖所述半导体芯片的第二面和侧面;
研磨所述封装材料以从所述半导体芯片的第二面移除所述封装材料并且减小所述半导体芯片的厚度,从而产生所述半导体芯片的第二面和所述封装材料的平表面;以及
从所述半导体芯片的第二面移除半导体材料,从而在所述半导体芯片的第二面和所述封装材料的所述平表面之间产生间隙。
15. 一种制造器件的方法,所述方法包括:
提供具有第一面和与第一面相对的第二面的半导体芯片,其中接触元件从第一面突出至少1μm;
利用封装材料封装所述半导体芯片和所述接触元件;
研磨所述封装材料,直至所述接触元件被暴露;以及
从所述半导体芯片的第二面移除半导体材料而同时基本上不移除封装材料。
16. 一种器件,包括:
具有第一面和与第一面相对的第二面的半导体芯片,其中接触垫被布置在第一面上;以及
具有第一面和与第一面相对的第二面的封装材料,其中,
所述封装材料封装所述半导体芯片,
所述半导体芯片的第一面和所述封装材料的第一面是共面的,从而限定平面,以及
所述半导体芯片的第二面和所述封装材料的第二面具有处于从3到10μm的范围的高度差。
17. 根据权利要求16所述的器件,其中,所述半导体芯片的第二面从所述封装材料被暴露。
18. 根据权利要求16所述的器件,其中,所述封装材料覆盖所述半导体芯片的侧面。
19. 根据权利要求16所述的器件,其中,再分布层被布置在由所述半导体芯片的第一面和所述封装材料的第一面限定的所述平面上。
20. 根据权利要求19所述的器件,其中,所述再分布层延伸超出所述半导体芯片的轮廓。
21. 根据权利要求16所述的器件,其中,在所述半导体芯片的厚度和所述封装材料的厚度之间的差等于在所述半导体芯片的第二面和所述封装材料的第二面之间的高度差。
22. 根据权利要求16所述的器件,其中,所述封装材料是均质的并且完全由相同材料制成。
23. 一种器件,包括:
具有第一面和与第一面相对的第二面的半导体芯片,其中接触元件从第一面突出至少1μm;以及
具有第一面和与第一面相对的第二面的封装材料,其中,
所述封装材料封装所述半导体芯片,
所述封装材料的第一面和所述接触元件的面限定平面,以及
所述半导体芯片的第二面和所述封装材料的第二面具有处于从3到10μm的范围的高度差。
24. 根据权利要求23所述的器件,其中,所述半导体芯片的第二面从所述封装材料被暴露。
25. 根据权利要求23所述的器件,还包括再分布层,其被布置在由所述封装材料的第一面和所述接触元件的所述面限定的所述平面上。
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Also Published As
Publication number | Publication date |
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DE102012107696A1 (de) | 2013-02-28 |
TW201312666A (zh) | 2013-03-16 |
DE102012025818B4 (de) | 2023-10-19 |
TWI502654B (zh) | 2015-10-01 |
US20130049205A1 (en) | 2013-02-28 |
CN102956468B (zh) | 2016-01-13 |
US9064883B2 (en) | 2015-06-23 |
US9646856B2 (en) | 2017-05-09 |
KR101517347B1 (ko) | 2015-05-04 |
KR20130023117A (ko) | 2013-03-07 |
DE102012107696B4 (de) | 2020-06-04 |
US20150262844A1 (en) | 2015-09-17 |
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