CN102082102A - 形成柔性应力消除缓冲区的半导体器件和方法 - Google Patents

形成柔性应力消除缓冲区的半导体器件和方法 Download PDF

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CN102082102A
CN102082102A CN2010105596319A CN201010559631A CN102082102A CN 102082102 A CN102082102 A CN 102082102A CN 2010105596319 A CN2010105596319 A CN 2010105596319A CN 201010559631 A CN201010559631 A CN 201010559631A CN 102082102 A CN102082102 A CN 102082102A
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stress
buffering area
semiconductor element
parts
layer
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CN102082102B (zh
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林耀剑
沈一权
邹胜源
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及形成柔性应力消除缓冲区的半导体器件和方法。半导体器件具有在指定用于凸点形成的位置处安装到暂时衬底的应力消除缓冲区。应力消除缓冲区可以是多层复合材料，诸如第一柔性层、在所述第一柔性层上形成的硅层以及在所述硅层上形成的第二柔性层。半导体管芯也安装到暂时衬底。应力消除缓冲区可以比半导体管芯薄。在半导体管芯和应力消除缓冲区之间沉积密封剂。去除暂时衬底。在半导体管芯、密封剂和应力消除缓冲区上形成互连结构。互连结构电连接到半导体管芯。可以在应力消除缓冲区和密封剂上形成增强板层。可以在应力消除缓冲区内形成包含有源器件、无源器件、导电层和介电层的电路层。

Description

形成柔性应力消除缓冲区的半导体器件和方法
技术领域
本发明大体上涉及半导体器件，并且更具体地涉及在大阵列WLCSP和FO-WLCSP周围形成柔性（compliant）应力消除缓冲区的半导体器件和方法。
背景技术
半导体器件普遍存在于现代电子产品中。半导体器件在电部件的数量和密度方面变化。分立半导体器件一般包含一种类型的电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百到几百万个电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。
半导体器件执行各种各样的功能，诸如高速计算、发射和接收电磁信号、控制电子器件、把太阳光转换成电力以及为电视显示器创建视觉投影。半导体器件存在于娱乐、通信、功率变换、网络、计算机和消费品中。半导体器件也存在于军事应用、航空、汽车、工业控制器和办公设备中。
半导体器件利用半导体材料的电学属性。半导体材料的原子结构允许通过施加电场或基极电流或者通过掺杂工艺来操纵其电导率。掺杂将杂质引入到半导体材料中以操纵和控制半导体器件的电导率。
半导体器件包含有源和无源电结构。包括双极型和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和电场或基极电流的施加，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构产生为执行各种电功能所需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路使得半导体器件能够执行高速计算和其他有用功能。
半导体器件一般使用两个复杂的制造工艺（即前端制造和后端制造）进行制造，每个制造工艺可能涉及几百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个管芯典型地完全相同并且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片中单颗化个别管芯以及封装该管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是产生更小的半导体器件。更小的半导体器件典型地消耗更少的功率，具有更高的性能，并且可以被更高效地生产。另外，更小的半导体器件具有更小的占位面积（footprint），这对于更小的终端产品而言是所期望的。更小的管芯大小可以通过前端工艺的改进（导致管芯具有更小的、更高密度的有源和无源部件）来获得。后端工艺可以通过电互连和封装材料的改进而导致具有更小占位面积的半导体器件封装。
WLCSP和FO-WLCSP往往包含大阵列半导体管芯，其再分配从管芯的细间距接合垫到***扇出区域的信号路径以便与外部器件更高地功能集成。大阵列WLCSP已知经历可靠性问题，具体地是在温度循环和跌落冲击测试期间的焊接接缝故障。另外，大阵列WLCSP由于大管芯尺寸而易于具有翘曲问题。
发明内容
存在对减小大阵列WLCSP和FO-WLCSP中的焊接接缝故障的需要。因而，在一个实施例中，本发明是一种制作半导体器件的方法，该方法包括以下步骤：形成应力消除缓冲区；提供暂时衬底；把半导体管芯安装到所述暂时衬底；把所述应力消除缓冲区安装到所述半导体管芯周围的所述暂时衬底；在所述半导体管芯和应力消除缓冲区之间沉积密封剂；去除所述暂时衬底；以及在所述半导体管芯、密封剂和应力消除缓冲区上形成互连结构。该互连结构电连接到所述半导体管芯。
在另一个实施例中，本发明是一种制作半导体器件的方法，该方法包括以下步骤：提供暂时衬底；把半导体管芯或部件安装到所述暂时衬底；在所述暂时衬底上形成应力消除层；在所述应力消除层和半导体管芯或部件上沉积密封剂；去除所述暂时衬底；以及在所述半导体管芯或部件和应力消除层上形成互连结构。该互连结构电连接到所述半导体管芯。
在另一个实施例中，本发明是一种制作半导体器件的方法，该方法包括以下步骤：提供暂时衬底；把半导体管芯或部件安装到所述暂时衬底；把应力消除缓冲区安装到所述暂时衬底；以及在所述应力消除缓冲区和半导体管芯或部件之间沉积密封剂。
在另一个实施例中，本发明是一种半导体器件，其包括半导体管芯或部件和设置在所述半导体管芯或部件周围的应力消除缓冲区。密封剂沉积在所述应力消除缓冲区和半导体管芯或部件之间。互连结构形成在所述半导体管芯或部件和应力消除缓冲区上。互连结构电连接到所述半导体管芯或部件。
附图说明
图1示出具有安装到其表面的不同类型的封装的PCB；
图2a-2c示出安装到PCB的代表性半导体封装的进一步细节；
图3a-3f示出在半导体管芯周围形成柔性应力消除缓冲区的工艺；
图4示出具有在半导体管芯周围的应力消除缓冲区的FO-WLCSP；
图5a-5b示出部分或完全沿FO-WLCSP一侧延伸的应力消除缓冲区；
图6示出多层复合物应力消除缓冲区；
图7示出安装在应力消除缓冲区和半导体管芯上的增强板（stiffener）；
图8示出形成在应力消除缓冲区中的电路层；
图9a-9b示出形成在比半导体管芯更薄的应力消除缓冲区上的增强板；
图10a-10c示出在半导体管芯周围形成柔性应力消除层的工艺；以及
图11a-11b示出具有在半导体管芯周围的应力消除层的FO-WLCSP。
具体实施方式
本发明是参考附图在以下描述的一个或多个实施例中描述的，其中同样的数字代表相同或类似的元件。虽然本发明是按照用于获得本发明目标的最佳模式描述的，但是本领域的技术人员会明白其旨在覆盖如可以被包括在如以下公开和附图所支持的所附权利要求书及其等价物所定义的发明的精神和范围内的更改、修改和等价物。
一般使用两个复杂的制造工艺来制造半导体器件：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，诸如晶体管和二极管，具有控制电流流动的能力。无源电部件，诸如电容器、电感器、电阻器和变压器，产生为执行电路功能所需的电压和电流之间的关系。
无源和有源部件通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤而形成在半导体晶片的表面上。掺杂通过诸如离子注入或热扩散之类的技术而把杂质引入到半导体材料中。掺杂工艺修改有源器件中半导体材料的电导率，从而把半导体材料转换成绝缘体、导体或者响应于电场或基极电流而动态改变半导体材料电导率。晶体管包含为使得晶体管能够在电场或基极电流的施加下促进或限制电流流动而需要布置的变化掺杂类型和程度的区域。
有源和无源部件由具有不同电属性的材料层形成。这些层可以通过部分由被沉积的材料类型所确定的各种沉积技术形成。例如，薄膜沉积可以涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀以及化学电镀工艺。每层一般被图案化以形成各部分的有源部件、无源部件或部件之间的电连接。
这些层可以使用光刻来图案化，所述光刻涉及在要图案化的层上沉积光敏材料（例如，光致抗蚀剂）。使用光把图案从光掩模转移到光致抗蚀剂。经受光的光致抗蚀剂图案的部分使用溶剂来去除，暴露要图案化的底层的部分。光致抗蚀剂的其余部分被去除，留下图案化后的层。可选地，一些类型的材料通过把该材料直接沉积到由先前沉积/蚀刻工艺使用诸如化学和电解电镀之类的技术而形成的区域或空隙中进行图案化。
在现有图案上沉积薄膜材料可能扩大底下图案并且产生不均匀的平坦表面。为产生较小且更密集的有源和无源部件而要求均匀的平坦表面。平坦化可以用来从晶片的表面去除材料并且产生均匀的平坦表面。平坦化涉及用抛光垫片对晶片的表面进行抛光。在抛光期间研磨材料和腐蚀性化学制剂被添加到晶片的表面。组合的、磨料的机械作用和化学制剂的腐蚀作用去除任何不规则形貌，导致均匀的平坦表面。
后端制造指的是把完成的晶片切割或单颗化成个别管芯并且然后对管芯进行封装以用于结构支撑和环境隔离。为了单颗化管芯，晶片沿被称作划片街区（saw street）或划线的晶片的非功能区域被刻痕并切断。使用激光切割工具或锯刀来单颗化晶片。在单颗化后，个别管芯被安装到包括用于与其他***部件互连的管脚或接触垫的封装衬底上。在半导体管芯上形成的接触垫然后连接到封装内的接触垫。电连接可以用焊料凸点、柱形凸点、导电胶或引线接合制成。密封剂或其他模制材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被***到电***中并且使半导体器件的功能性可用于其他***部件。
图1示出具有在其表面上安装有多个半导体封装的芯片载体衬底或印刷电路板（PCB）52的电子器件50。电子器件50可以根据应用而具有一种类型的半导体封装或者多种类型的半导体封装。为了说明目的而在图1中示出不同类型的半导体封装。
电子器件50可以是独立式***，其使用半导体封装来执行一个或多个电功能。可选地，电子器件50可以是较大***的子部件。例如，电子器件50可以是图形卡、网络接口卡或者其他可以***到计算机中的信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或者其他半导体管芯或电部件。
在图1中，PCB 52提供用于安装在PCB上的半导体封装的结构支撑和电互连的一般衬底。使用蒸发、电解电镀、化学电镀、丝网印刷或者其他合适的金属沉积工艺来把导电信号迹线54形成在表面上或在各层PCB 52内。信号迹线54提供每个半导体封装、所安装部件以及其他外部***部件之间的电通信。迹线54也提供到每个半导体封装的电源和地连接。
在一些实施例中，半导体器件具有两个封装等级。一级封装是一种用于把半导体管芯机械且电地附着到中间载体的技术。二级封装涉及把中间载体机械且电地附着到PCB。在其他实施例中，半导体器件可以只有一级封装，其中管芯被机械且电地直接安装到PCB。
为了说明的目的，在PCB 52上示出包括引线接合封装56和倒装芯片58的若干类型的一级封装。另外，示出安装在PCB 52上的包括球栅阵列（BGA）60、凸点芯片载体（BCC）62、双列直插式封装（DIP）64、连接盘网格阵列（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）70和四方扁平封装72的若干类型的二级封装。根据***要求，配有一级和二级封装方式的任何组合的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，而其他实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以把预制部件合并到电子器件和***中。因为半导体封装包括复杂的功能性，所以可以使用较廉价的部件和流水线的制造工艺来制造电子器件。所得到的器件不太可能出故障并且制造较便宜，导致消费者的更低成本。
图2a-2c示出示例性半导体封装。图2a示出安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，其包含模拟或数字电路，所述模拟或数字电路被实施为形成在管芯内的并且根据管芯的电设计进行电互连的有源器件、无源器件、导电层和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器以及其他形成在半导体管芯74的有源区域内的电路元件。接触垫76是一层或多层导电材料，诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag），并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，半导体管芯74使用金硅共晶层或粘合材料（诸如热环氧化物）而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导体引线80和引线接合82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上以通过防止湿气和颗粒进入封装并且污染管芯74或引线接合82来实现环境保护。
图2b示出安装在PCB 52上的BCC 62的进一步细节。使用底部填充或环氧树脂粘合材料92把半导体管芯88安装在载体90上。引线接合94提供接触垫96和98之间的一级封装互连。模制化合物或密封剂100沉积在半导体管芯88和引线接合94上以为器件提供物理支撑和电隔离。使用诸如电解电镀或化学电镀之类的合适的金属沉积工艺来防止氧化，在PCB 52的表面上形成接触垫102。接触垫102电连接到PCB 52中的一条或多条导电信号迹线54。凸点104形成在BCC 62的接触垫98和PCB 52的接触垫102之间。
在图2c中，半导体管芯58以倒装芯片式一级封装而面朝下地安装到中间载体106。半导体管芯58的有源区域108包含模拟或数字电路，其被实施为根据管芯的电设计而形成的有源器件、无源器件、导电层和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器和有源区域108内的其他电路元件。半导体管芯58通过凸点110电且机械地连接到载体106。
BGA 60使用凸点112以BGA式二级封装而电且机械地连接到PCB 52。半导体管芯58通过凸点110、信号线114和凸点112而电连接到PCB 52中的导电信号迹线54。模制化合物或封装剂116沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的传导通道的短电传导通路以便减小信号传播距离、降低电容并且改善整体电路性能。在另一个实施例中，半导体管芯58可以在不用中间载体106的情况下使用倒装芯片式一级封装而机械且电地直接连接到PCB 52。
图3a-3f示出针对图1和2a-2c的在半导体管芯周围形成柔性应力消除缓冲区的工艺。在图3a中，衬底或载体120包含暂时或牺牲基底材料，诸如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃环氧树脂、氧化铍或者其他用于结构支撑的合适的低成本、刚性材料或体半导体材料。任选的界面层122可以形成在载体120上作为暂时粘接膜或蚀刻停止层。
半导体管芯或部件124安装到界面层122，其中有源表面128上的接触垫126朝载体120向下定向。有源表面128包含模拟或数字电路，所述模拟或数字电路被实施为形成在管芯内的并且根据管芯的电设计和功能进行电互连的有源器件、无源器件、导电层和介电层。例如，电路可以包括一个或多个晶体管、二极管以及其他形成在有源表面128内的电路元件以实施模拟电路或数字电路（诸如数字信号处理器（DSP）、ASIC、存储器或者其他信号处理电路）的电路元件。半导体管芯124也可以包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。
在图3b中，柔性应力消除缓冲区或块结构130使用模制工艺而预形成为圆形或方形小片（patch）或矩形带。应力消除缓冲区130包含柔性材料，诸如聚合物、环氧化物、聚合物材料、具有填充剂的环氧树脂、或者具有填充剂的环氧丙烯酸酯。可选地，应力消除缓冲区130可以是用酚醛棉纸、环氧化物、玻璃织物（woven glass）、毛玻璃、聚酯或者其他增强纤维或织物、具有核心层的PCB板材料或其他阻尼材料的组合预浸渍（预浸处理）的聚四氟乙烯。在指定用于凸点形成的位置132，即在所完成FO-WLCSP的边缘或拐角处，把应力消除缓冲区130安装到界面层122。
在图3c中，使用膏印刷、压缩模制、转移模制、液封模制、真空层压、旋涂或者其他合适的敷料器将密封剂或模制化合物136沉积在应力消除缓冲区130和半导体管芯124之间以及在半导体管芯上至与应力消除缓冲区齐平的水平。应力消除缓冲区130可以比半导体管芯124更厚，因此密封剂136覆盖管芯的背表面138。密封剂136可以是聚合物复合材料，诸如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。密封剂136是不导电的并且环境上保护半导体器件不受外部元件和污染物的影响。
图3d示出在载体120上四个半导体管芯124、应力消除缓冲区130和密封剂136的分组的顶视图。应力消除缓冲区130安装到在FO-WLCSP的边缘和拐角处指定用于凸点形成的位置132。
在图3e中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘、激光扫描或湿法脱模来去除暂时载体120和任选的界面层122。底侧累积（build-up）互连结构140形成在半导体管芯124、应力消除缓冲区130和密封剂136上。该累积互连结构140包括绝缘或钝化层142，其包含一层或多层二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、低温（≤250℃）固化聚合物光刻胶（诸如苯环丁烯（BCB）、聚苯并恶唑（PBO）、基于环氧化物的光敏聚合物电介质）或者其他具有类似绝缘和结构属性的材料。绝缘层142使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层142。通过蚀刻工艺来去除绝缘层142的一部分以暴露半导体管芯124的接触垫124。
使用诸如PVD、CVD、溅射、电解电镀和化学电镀工艺的图案化和金属沉积工艺在缘层142和接触垫126上形成导电层144。导电层144可以是一层或多层Al、Cu、Ti、TiW、Sn、Ni、Au、Ag或其他合适的导电材料。导电层144操作为再分配层（RDL）。导电层144的一部分电连接到半导体管芯124的接触垫126。导电层144的其他部分可以根据半导体器件的设计和功能而是电公共或电隔离的。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在绝缘层142和导电层144上形成绝缘或钝化层146。绝缘层146可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3、低温（≤250℃）固化聚合物光致抗蚀剂（诸如BCB、PBO或基于环氧化物的光敏聚合物电介质）或者其他具有类似绝缘和结构属性的材料。通过蚀刻工艺来去除绝缘层146的一部分以暴露导电层144。
使用蒸发、电解电镀、化学电镀、球落（ball drop）或丝网印刷工艺，导电凸点材料被沉积在累积互连结构140上并且电连接到导电层144。凸点材料可以是具有任选焊剂（flux）溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或者无铅焊料。凸点材料使用合适的附着或接合工艺而接合到导电层144。在一个实施例中，凸点材料通过将材料加热到其熔点之上被回流以形成球形球或凸点148。在一些应用中，凸点148被二次回流以改善到导电层144的电接触。凸点也可以压缩接合到导电层144。凸点148代表可以形成在导电层144上的一种类型的互连结构。该互连结构也可以使用接合线、柱形凸点、微凸点以及其他电互连。
图3f示出四个半导体管芯124、应力消除缓冲区130和密封剂136的分组的顶视图，其中接触垫126通过导电层144电连接到凸点148。
包括半导体管芯124、密封剂化合物136、应力消除缓冲区130和互连结构140的最终的半导体封装用图3e和3f中的锯条或激光切割设备150沿线149被单颗化成个别半导体器件。图4示出在单颗化后的FO-WLCSP 151。半导体管芯124电连接到底侧累积互连结构140和凸点148。预形成的柔性应力消除缓冲区130设置在FO-WLCSP 151的边缘、拐角以及其他封装完整性临界区域周围以通过吸收热机械应力防止在可靠性或跌落测试的温度循环测试和其他机械震动或冲击期间凸点148的故障。应力消除缓冲区130具有低杨氏模量（即小于密封剂136）、良好的弹性和弹力特性、以及类似于或略小于密封剂的热膨胀系数（CTE）。应力消除缓冲区130也用来减小密封工艺期间的管芯移位。
图5a和5b示出沿FO-WLCSP 152一侧部分或完全延伸的预形成的柔性应力消除缓冲区130的截面图和顶视图。
图6示出具有包含多层的预形成的复合物应力消除缓冲区156的、与图3a-3f中描述的结构类似的FO-WLCSP 154的实施例。在一个实施例中，复合物应力消除缓冲区156具有柔性材料层158、硅层160和柔性材料层158。可选地，复合物应力消除缓冲区156的层是金属/柔性材料/金属或者硅/柔性材料/硅。复合物应力消除缓冲区156减小FO-WLCSP 154中的翘曲。通过减小翘曲和CTE诱导的应力，FO-WLCSP 154减小了尤其在半导体管芯的***周围的焊接接缝故障。
图7示出具有安装在应力消除缓冲区130和密封剂136上的金属增强板或层164的、与图3a-3f中描述的结构类似的FO-WLCSP 162的实施例。粘合层沉积在应力消除缓冲区130上以固定增强板164。增强板164减小FO-WLCSP 162中的翘曲。增强板164可以被用作热沉，该热沉具有任选的热界面材料（TIM）166用于自半导体管芯124散热。作为热沉，增强板164可以是Al、Cu或另一种具有高热导率的材料。TIM 166辅助由半导体管芯124生成的热的分布和消散。增强板164也可以操作为电磁干扰（EMI）或射频干扰（RFI）屏蔽层。作为EMI或RFI屏蔽层，增强板164可以是Cu、Al、铁氧体或羰基铁、不锈钢、镍银、低碳刚、硅铁刚、箔、环氧化物、导电树脂或者其他能够阻挡或吸收EMI、RFI和其他设备间干扰的金属和复合物。屏蔽层也可以是诸如炭黑或铝片（aluminum flake）的非金属材料，以减小EMI和RFI的效应。增强板164可以被接地以转移EMI和RFI信号。
图8示出具有包含嵌入在柔性应力消除材料178内的电路层176的预形成的应力消除缓冲区172的、与图3a-3f中描述的结构类似的FO-WLCSP 170的实施例。电路层176可以包含模拟或数字电路，所述模拟或数字电路被实施为形成在应力消除材料178内的有源器件、无源器件、导电层和介电层。
图9a示出具有被制得比半导体管芯124更薄的应力消除缓冲区184的、与图3a-3f中描述的结构类似的FO-WLCSP 180的实施例。在沉积密封剂136之前在应力消除缓冲区130上安装金属增强板或层182。粘合层沉积在应力消除缓冲区184上以固定增强板182。增强板182可以形成为完全环绕半导体管芯124的窗口，如图9b所示。增强板182减小FO-WLCSP 180中的翘曲。
图10a-10c示出针对图1和2a-2c的在半导体管芯周围形成柔性应力消除层的工艺。继续图3a中描述的结构，使用旋涂或丝网印刷将柔性应力消除层190形成在半导体管芯124周围的界面层122上。应力消除层190可以在安装半导体管芯124之前进行沉积。在应力消除层190和半导体管芯124之间可以存在间隙或可以不存在间隙。在有间隙的情况下，底部填充材料，诸如环氧化物或聚合物材料，被施加在管芯边缘上以覆盖该间隙从而防止封装期间的管芯移位。应力消除层190可以是柔性材料，诸如聚合物、环氧化物、聚合物材料、具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯、光敏抗蚀剂或者其他具有高延伸率、低模量和平衡CTE的柔性材料。在一个实施例中，应力消除层190是绝缘材料，诸如聚酰亚胺、PBO、硅基弹性体或者其他具有低CTE（20ppm/℃或更小）和低模量（200Mpa或更小）的类似材料。应力消除层190的厚度典型地为15-100微米（μm）。
在图10b中，使用膏印刷、压缩模制、转移模制、液封模制、真空层压、旋涂或者其他合适的敷料器将密封剂或模制化合物192沉积在应力消除层190和半导体管芯124上。密封剂192可以是聚合物复合材料，诸如具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸酯或者具有适当填充剂的聚合物。密封剂192是不导电的并且环境上保护半导体器件不受外部元件和污染物的影响。
在图10c中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘、激光扫描或湿法脱模来去除暂时载体120和任选的界面层122。底侧累积互连结构194形成在半导体管芯124和应力消除层190上。该累积互连结构194包括绝缘或钝化层196，其包含一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者其他具有类似绝缘和结构属性的材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化来形成绝缘层196。通过蚀刻工艺来去除绝缘层196的一部分以暴露半导体管芯124的接触垫126。
使用诸如PVD、CVD、溅射、电解电镀和化学电镀工艺的图案化和金属沉积工艺在缘层196和接触垫126上形成导电层198。导电层198可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料。导电层198操作为RDL。导电层198的一部分电连接到半导体管芯124的接触垫126。导电层198的其他部分可以根据半导体器件的设计和功能而是电公共或电隔离的。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在绝缘层196和导电层198上形成绝缘或钝化层200。绝缘层200可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或者其他具有类似绝缘和结构属性的材料。通过蚀刻工艺来去除绝缘层200的一部分以暴露导电层198。
使用蒸发、电解电镀、化学电镀、球落或丝网印刷工艺，导电凸点材料被沉积在累积互连结构194上并且电连接到导电层198。凸点材料可以是具有任选焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或者无铅焊料。凸点材料使用合适的附着或接合工艺而接合到导电层198。在一个实施例中，凸点材料通过将材料加热到其熔点之上被回流以形成球形球或凸点202。在一些应用中，凸点202被二次回流以改善到导电层198的电接触。凸点也可以压缩接合到导电层198。凸点202代表可以形成在导电层198上的一种类型的互连结构。该互连结构也可以使用接合线、柱形凸点、微凸点以及其他电互连。
用锯条或激光切割设备204把半导体管芯124单颗化成个别半导体器件。图11a示出在单颗化后FO-WLCSP 206的截面图。图11b示出半导体管芯124和应力消除层190的底视图，其中接触垫126通过导电层198电连接到凸点202。柔性应力消除层190设置在半导体管芯124周围以通过吸收热机械应力防止在可靠性或跌落测试的温度循环测试以及其他机械震动或冲击期间凸点202的故障。应力消除层190具有低杨氏模量（即小于密封剂192）、良好的弹性和弹力特性、以及类似于或略小于密封剂的CTE。应力消除层190也用来减小密封工艺期间的管芯移位。
虽然详细示出了本发明的一个或多个实施例，但是本领域技术人员会明白，可以在不偏离如所附权利要求书所述的本发明的范围的情况下做出对那些实施例的修改和变型。

Claims (25)

1. 一种制作半导体器件的方法，包括：
形成应力消除缓冲区；
提供暂时衬底；
把半导体管芯安装到所述暂时衬底；
把所述应力消除缓冲区安装到所述半导体管芯周围的所述暂时衬底；
在所述半导体管芯和应力消除缓冲区之间沉积密封剂；
去除所述暂时衬底；以及
在所述半导体管芯、密封剂和应力消除缓冲区上形成互连结构，该互连结构电连接到所述半导体管芯。
2. 权利要求1的方法，还包括在指定用于凸点形成的位置处形成所述应力消除缓冲区。
3. 权利要求1的方法，其中所述应力消除缓冲区包括具有阻尼属性的多层复合材料和结构。
4. 权利要求1的方法，其中形成应力消除缓冲区包括：
形成第一柔性层；
在所述第一柔性层上形成硅层；以及
在所述硅层上形成第二柔性层。
5. 权利要求1的方法，还包括在所述应力消除缓冲区和密封剂上形成增强板层。
6. 权利要求1的方法，其中所述应力消除缓冲区比所述半导体管芯薄。
7. 权利要求1的方法，还包括在所述应力消除缓冲区内形成电路。
8. 一种制作半导体器件的方法，包括：
提供暂时衬底；
把半导体管芯或部件安装到所述暂时衬底；
在所述暂时衬底上形成应力消除层；
在所述应力消除缓冲区和半导体管芯或部件上沉积密封剂；
去除所述暂时衬底；以及
在所述半导体管芯或部件和应力消除层上形成互连结构，该互连结构电连接到所述半导体管芯。
9. 权利要求8的方法，还包括在应力消除缓冲区和密封剂上形成增强板层。
10. 权利要求8的方法，其中所述应力消除层比所述半导体管芯或部件薄。
11. 权利要求8的方法，还包括在所述应力消除缓冲区内形成电路层。
12. 一种制作半导体器件的方法，包括：
提供暂时衬底；
把半导体管芯或部件安装到所述暂时衬底；
把应力消除缓冲区安装到所述暂时衬底；以及
在所述应力消除缓冲区和半导体管芯或部件之间沉积密封剂。
13. 权利要求12的方法，还包括：
去除所述暂时衬底；以及
在所述半导体管芯和应力消除缓冲区上形成互连结构，该互连结构电连接到所述半导体管芯或部件。
14. 权利要求12的方法，还包括在指定用于凸点形成的位置处形成所述应力消除缓冲区。
15. 权利要求12的方法，其中所述应力消除缓冲区包括多层复合材料。
16. 权利要求12的方法，其中形成应力消除缓冲区包括：
形成第一柔性层；
在所述第一柔性层上形成刚性层；以及
在所述刚性层上形成第二柔性层。
17. 权利要求12的方法，还包括在所述应力消除缓冲区和密封剂上形成增强板层。
18. 权利要求12的方法，其中所述应力消除缓冲区比所述半导体管芯或部件薄。
19. 权利要求12的方法，还包括在所述应力消除缓冲区内形成电路层。
20. 一种半导体器件，包括：
半导体管芯或部件；
应力消除缓冲区，设置在所述半导体管芯或部件周围；
密封剂，沉积在所述应力消除缓冲区和半导体管芯或部件之间；以及
互连结构，形成在所述半导体管芯或部件和应力消除缓冲区上，该互连结构电连接到所述半导体管芯或部件。
21. 权利要求20的半导体器件，其中所述应力消除缓冲区设置在指定用于凸点形成的位置处。
22. 权利要求20的半导体器件，其中所述应力消除缓冲区包括多层复合材料。
23. 权利要求20的半导体器件，还包括形成在所述应力消除缓冲区和密封剂上的增强板层。
24. 权利要求20的半导体器件，其中所述应力消除缓冲区比所述半导体管芯或部件薄。
25. 权利要求20的半导体器件，还包括在所述应力消除缓冲区内的电路层。
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