CN102948071B - 调制不可知的数字混合模式功率放大器***及方法 - Google Patents
调制不可知的数字混合模式功率放大器***及方法 Download PDFInfo
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Abstract
公开了一种用于在宽带通信***中实现高效率和高线性度的RF数字混合模式功率放大器***。本发明基于用于在RF域内线性化功率放大器的自适应数字预失真的方法。本公开内容使功率放大器***能够现场可重构并支持多调制方案(调制不可知)、多载波和多信道。因此,数字混合模式功率放大器***特别适合不容易获得基带I-Q信号信息的无线传输***,诸如基站、中继器和室内信号覆盖***。
Description
相关申请
本申请要求以下申请的权益:
2009年12月21日递交的、申请号为61/288,844、发明名称为“ADVANCEDDIGITALHYBRIDMODEPOWERAMPLIFIERSYSTEMANDMETHOD”且发明人为Wan-JongKim、Kyoung-JoonCho、ShawnPatrickStapleton和YingXiao的美国专利申请。
本发明总体上涉及使用复合调制技术的无线通信***。更具体地,本发明涉及用于无线通信的功率放大器***。
使用诸如宽带码分多址(WCDMA)和正交频分复用(OFDM)的复合调制技术的宽带移动通信***具有大的峰值平均功率比(PAPR)规格,从而需要用于其射频(RF)发送的高线性功率放大器。常规的前馈线性功率放大器(FFLPA)由于其极好的线性度性能已被广泛使用,尽管其具有低功率效率。
技术领域
背景技术
常规的FFLPA主要基于利用专用硬件电路来实现对PA的非线性校正的误差扣除和功率匹配的原理。这些方法必须使用辅助PA和复杂硬件电路来准确地匹配由主PA生成的发送功率平衡、时间延迟和误差。在获得完美的匹配之后,来自主PA的非线性失真误差于是可以由来自辅助PA的那些失真误差消除。由于此外还包括许多变量和参数的非线性预失真电路的复杂性,FFLPA需要极精细的调谐和其它校准努力。另外,由于主PA的信号与辅助PA的信号的极好地对准是至关重要的,因而这样的传统的FFLPA方案也易受诸如温度变化和湿度变化的波动的环境条件的影响。因此,传统的预失真方案实现成本高且在商业无线***环境中在其预失真精度和稳定性方面受限。
为了克服FFLPA的低效率,由于数字信号处理(DSP)技术的最新发展而展现了数字基带预失真(PD)。另外,Doherty功率放大器(DPA)也被应用于这些线性化***来改善功率效率。然而,仍然存在对功率放大器的较高性能的需求,诸如更好的线性度和更好的效率以及廉价的架构。
常规的基于DSP的PD方案通常通过对PA***中的信号进行快速跟踪和调节来使用数字微处理器估计、计算并校正PA的非线性度。然而,由于诸如温度的环境变化和由记忆效应导致的PA输出信号的不对称失真所引起的放大器的线性度性能的变化,对常规的基于DSP的PD方案提出了挑战。必须补偿所有这些变化和失真。常规的PD算法基于宽带反馈信号,并且需要高速模数转换器(ADC)来捕获需要的信息。另外,为了捕获参考信号与失真信号之间的误差信号,通常需要时间同步。该时间匹配处理会导致可能进一步影响常规的PD方案的线性化性能的小同步误差。为了对准参考信号和失真信号,还需要幅度和相位同步。
此外,常规的PD方案必须用基带的编码的同相(I)和正交(Q)信道信号作为所需的理想信号或参考信号。因此,常规的PD方案常常是标准特定或调制特定的,并且必须针对每个基带***精确地定制。因此,为了将常规的PD方案部署到基站中,PD引擎必须嵌入进基站的基带架构中。这种嵌入是实际的实施挑战,这是因为修改现有基站或基站设计的基带架构常常是不方便的或不可能的。一旦针对具体的基站设计建立了PD方案,则该PD方案通常是不可重构的,从而不可升级至标准或调制的未来变化。此外,因为传统的PD方法需要基带I-Q信号源来操作,所以传统的PD方法不能应用于没有任何基带I-Q信号源的某些RF***,诸如中继器和室内信号覆盖子***。
发明内容
因此,考虑到以上问题完成了本发明,本发明的目的是对于宽带通信***应用提供一种具有高线性度和高效率的功率放大器***的高性能且节省成本的方法。本公开内容提供一种支持多调制方案(调制不可知)、多载波和多信道的现场可重构功率放大器***。在本发明的多信道配置中,针对多波段可以存在多于一个的PA。
为了实现以上目的,本发明总体上基于在RF域内使RF功率放大器线性化的自适应数字预失真的方法。公开了本发明的各种实施方式。在一个实施方式中,在PA***内使用了峰值因数衰减、PD、功率效率提升技术和系数自适应算法的组合。在另一实施方式中,还使用模拟正交调制器补偿结构来增强性能。
本发明的一些实施方式能够监测功率放大器特性的波动并能够借助自适应算法进行自调节。目前公开的一种这样的自适应算法称作数字预失真算法,其在数字域中实现。
本发明的应用适合与所有无线基站、接入点、移动装备无线终端、便携式无线设备、以及诸如微波和卫星通信的其它无线通信***一起使用。
公开了一种用于在宽带通信***中实现高效率和高线性度的RF数字混合模式功率放大器***。本发明基于在RF域中使功率放大器线性化的自适应数字预失真方法。在反馈路径中对诸如放大器输出信号的线性度变化和非对称失真的功率放大器特性进行采样,并且在数字模块中通过自适应算法来控制。因此,在实施方式中,本发明能够补偿功率放大器***的非线性度以及记忆效应,并且还改善在功率增加效率、相邻信道泄露比(ACLR)和峰值平均功率比方面的性能。本公开内容使功率放大器***能够现场可重构并且支持多调制方案(调制不可知)、多载波和多信道。因此,该数字混合模式功率放大器***特别适合不容易获得基带I-Q信号信息的无线传输***,诸如基站、中继器和室内信号覆盖***。
附图说明
根据结合附图进行的以下详细描述可以更充分地理解本发明的另外的目的和优点,在附图中:
图1为示出数字混合模式功率放大器***的基本形式的框图。
图2为示出根据本发明的一个实施方式的用于功率放大器***的简单数字预失真框图的框图。
图3为示出本发明的数字混合模式功率放大器***中的基于多项式的预失真的框图。
图4为应用于本发明的数字混合模式功率放大器***中的自适应的数字预失真算法的框图。
图5为本发明的延迟估计框图。
图6为用于本发明的分数延迟的框图。
图7为示出根据本发明的另一实施方式的、实现有下变频器(DNC)和基于UPC的削波误差恢复路径的数字混合模式功率放大器***的框图。
图8为示出根据本发明的另一实施方式的、实现有DNC和模拟正交调制器(AQM)的数字混合模式功率放大器***的框图。
图9为示出模拟正交调制器补偿结构的实施方式的框图。
术语表
本文中所使用的缩写具有以下含义:
ACLR相邻信道泄漏比
ACPR相邻信道功率比
ADC模数转换器
AQDM模拟正交解调器
AQM模拟正交调制器
AQDMC模拟正交解调校正器
AQMC模拟正交调制校正器
BPF带通滤波器
CDMA码分多址
CFR峰值因数衰减
DAC数模转换器
DET检测器
DHMPA数字混合模式功率放大器
DDC数字下变频器
DNC下变频器
DPADoherty功率放大器
DQDM数字正交解调器
DQM数字正交调制器
DSP数字信号处理
DUC数字上变频器
EER包络消除和恢复
EF包络跟随
ET包络跟踪
EVM误差矢量幅度
FFLPA前馈线性功率放大器
FIR有限脉冲响应
FPGA现场可编程门阵列
GSM全球移动通信***
I-Q同相-正交
IF中频
LlNC使用非线性部件的线性放大
LO本地振荡器
LPF低通滤波器
MCPA多载波功率放大器
MDS多方向搜索
OFDM正交频分复用
PA功率放大器
PAPR峰值平均功率比
PD数字基带预失真
PLL锁相环
QAM正交幅度调制
QPSK正交相移键控
RF射频
SAW表面声波滤波器
UMTS通用移动通信***
UPC上变频器
WCDMA宽带码分多址
WLAN无线局域网
具体实施方式
本发明为使用自适应数字预失真算法的新颖的RF-输出PA***。本发明为数字模块和模拟模块的混合***。混合***的数字模块和模拟模块的相互作用使频谱再生线性化且增强PA的功率效率,同时保持或增大宽的带宽。因此,本发明实现了对于宽带复合调制载波的更高的效率和更高的线性度。
图1为示出基本***架构的高层级框图,至少对于一些实施方式,可以认为该基本***架构包括数字模块和模拟模块以及反馈路径。数字模块为包括PD算法、其它的辅助DSP算法和相关数字电路的数字预失真控制器101。模拟模块为主功率放大器102、诸如DPA的其它辅助模拟电路和整个***的相关***模拟电路。本发明为“黑盒”、即插即用型的***,这是由于其接受RF调制信号100作为其输入并提供基本相同但放大的RF信号103作为其输出,因此,其为RF输入/RF输出。根据本发明的一个实施方式,可以将基带输入信号直接地应用于数字预失真器控制器。根据本发明的一个实施方式,可以将光输入信号直接地应用于数字预失真器控制器。反馈路径基本上将输出信号的表示提供给预失真控制器101。在后文中有时将本发明称为数字混合模式功率放大器(DHMPA)。
数字预失真器算法
数字预失真(DPD)为用于线性化功率放大器(PA)的技术。图2以框图形式示出了线性数字预失真PA的实施方式。在DPD块中,使用记忆多项式模型作为预失真函数(图3),并且该模型符合公式:
其中,aij为DPD系数。
在DPD估计器块中,使用最小二乘法求解DPD系数,然后将DPD系数传递至DPD块。在图4中示出详细的DPD算法。
图3为示出本发明的DHMPA***中的预失真(PD)部分的框图。本发明中的PD一般使用自适应的基于多项式的数字预失真***。PD的另一个实施方式使用基于LUT的数字预失真***。更具体地,在数字处理器中通过如下专利申请中提出的自适应算法来处理在下述图7和图8中所公开的实施方式中和图3中说明的PD:标题为“AMethodforBasebandPredistortionLinearizationinMulti-ChannelWidebandCommunicationSystems”、申请号为11/961,969的美国专利申请。图3中的用于DHMPA***的PD具有多个有限脉冲响应(FIR)滤波器,即,FIR1301、FIR2303、FIR3305和FIR4307。PD还包含三阶乘积生成块302、五阶乘积生成块304和七阶乘积生成块306。来自FIR滤波器的输出信号在求和块308中被合并。通过数字预失真算法更新多个FIR滤波器的系数。
延迟估计算法:
DPD估计器将x(n)与其相应的反馈信号y(n-△d)进行比较以求得DPD系数,其中,△d是反馈路径的延迟。由于对于每个PA而言反馈路径延迟不同,因此应当在信号到达系数估计之前对该延迟进行识别。在本设计中,应用发送x(n)和反馈数据y(n)的幅度差关联函数来求反馈路径延迟。该关联由下式给出
n(delay)=Max(C(m))
使关联C(m)最大化的延迟n为反馈路径延迟。图5中示出延迟估计块。
由于反馈路径经过模拟电路,因此发送路径与反馈路径之间的延迟可以是分数样本延迟。为了使信号更精确地同步,分数延迟估计是必要的。为了简化设计,如图6中示出的,本设计中仅考虑半样本延迟。应当理解,在至少一些实施方式中也可以使用更小的分数延迟。
为了得到半样本延迟数据,上采样(upsampling)方法是普遍的选择,然而在本设计中,为了避免FPGA中的非常高的采样频率,使用插值法来得到半样本延迟数据。具有整数延迟和分数延迟的数据并行传送。分数延迟的插值函数为:
其中,ci为权重系数。
根据幅度差相关器的结果来确定选择分数延迟路径还是整数延迟路径。如果相关结果是奇数,则选择整数路径,否则选择分数延迟路径。
相位偏移估计和校正算法:
电路中存在发送信号与反馈信号之间的相位偏移。为了DPD系数估计更好和更快地收敛,应当去除该相位偏移。
发送信号x(n)和反馈信号y(n)可以表示为:
相位偏移可以通过下式来计算:
因此,发送路径与反馈路径之间的相位偏移为:
可以通过下式计算去除了相位偏移的反馈信号:
幅度校正:
由于PA的增益可能会轻微变化,因此应当校正反馈增益以避免由于增益失配而产生的误差。根据以下函数校正反馈信号:
在本设计中,将N选择为4096。N的选择取决于所期望的精度。
QR_RLS自适应算法:
DPD系数估计的最小二乘方案用如下公式表示:
F(x(n))=y(n)
定义hk=x(n-i)|x(n-i)|j,wk=aij,其中,k=(i-1)N+j。最小二乘公式可以表示为:
在本设计中,实施QR-RLS算法(Haykin,1996)来解决该问题。QR_RLS算法的公式为:
其中,φi为对角矩阵,qi为矢量。
QR_RLS算法通过酉变换根据其第(i-1)个矩得到第i个矩φi和qi:
θi为酉变换的酉矩阵。
为了在FPGA中更有效地应用QR_RLS算法,将无平方根定标旋转应用于酉变换处理(E.N.Frantzeskakis,1994)
k′b=kakb/k′a
a′j=(kaa1aj+kbb1bj)/k′a
b′j=-b1aj+a1bj
对于RLS算法,如下实现第i个矩:
wi可以通过求解下式来获得:
在迭代处理中,数据的块(在本设计中,一个块中有4096个数据)被存储在存储器中,并且算法使用存储器中的所有数据来估计DPD系数。为了使得DPD性能更稳定,仅在对一个块的数据进行了处理之后才更新DPD系数。矩阵A将用于下一个迭代处理,其使得收敛更快。
为了确保DPD的性能稳定,在更新DPD系数时以如下方式使用加权因数f:
wi=f×wi-1+(1-f)wi
DPD系数估计器通过使用QR_RLS算法来计算系数wi。这些wi被复制至DPD块以线性化PA。
图7和图8为示出DHMPA***的更复杂的实施方式的框图,其中相同的元件用相同的标记来表示,且图8中未标号的元件具有与图7中示出的附图标记相同的附图标记。图7和图8的实施方式在一个数字处理器中在利用自适应算法进行PD之前,应用峰值因数衰减(CFR),以便降低PAPR、EVM和ACPR并补偿记忆效应和由于PA的温度变化导致的线性度的变化。数字处理器可以采取几乎任意形式;为了方便,示出FPGA实施作为示例,但是在许多实施方式中通用处理器也是可接受的。在实施方式的数字模块中实施的CFR基于如下专利申请中所提出的成比例迭代脉冲消除(scalediterativepulsecancellation):在2008年3月31日递交的、标题为“AnEfficientPeakCancellationMethodForReducingThePeak-To-AveragePowerRatioInWidebandCommunicationSystems”的专利申请US61/041,164,该申请通过引用合并在本文中。包括CFR是为了增强性能,因而是可选的。可以从实施方式中去除CFR而不影响整体功能性。
图7为示出根据本发明的实施方式的实现有DQM的DHMPA***的框图。图7中示出的***在输入端具有双模式,而在输出端处具有RF信号710,其中双模式分别为RF输入700和/或多载波数字信号输入705。信号输入的双模式能够使灵活性最大:RF输入(“RF输入模式”)或者基带数字输入(“基带输入模式”)。图7中示出的***包括三个关键的部分:可重构数字(后文中称为“基于FPGA的数字”)模块715、功率放大器模块760和反馈路径725。
基于FPGA的数字部分包括数字处理器715(例如,FPGA)、数模转换器735(DAC)、模数转换器740(ADC)和锁相环(PLL)745。由于图7的实施方式具有双输入模式,所以数字处理器具有两条信号处理路径。对于RF信号输入路径,数字处理器实施数字正交解调器(DQDM)、CFR、PD、和数字正交调制器(DQM)。对于基带数字输入路径,实施数字上变频器(DUC)、CFR、PD和DQM。
图7中示出的实施方式的RF输入模式在基于FPGA的数字部分之前实施了下变频器(DNC)750,并且在FPGA之前实施了ADC740。模拟下变频信号被提供给基于FPGA的数字模块,并且通过ADC740转换成数字信号。数字转换的信号被DQDM解调以生成实信号和虚信号,然后通过CFR来降低信号的PAPR。峰值降低的信号被预失真以线性化放大器,并且被传递通过DQM以生成实信号,然后在基于FPGA的数字部分中被DAC转换成中频(IF)模拟信号。然而,不是在所有实施方式中都需要在FPGA中实施DQDM和DQM。如图7和图8中示出的,如果不使用数字调制器,那么在FPGA之后的对AQM模块800进行馈入的两个DAC801可以分别用来生成实信号和虚信号(“AQM实施”)。
图7的***的基带输入模式与RF输入模式工作稍有不同。来自多信道的数字数据流作为I-Q信号进入基于FPGA的数字模块,并且被DUC数字地上变频成数字IF信号。此后,基带输入模式和RF输入模式等同地进行。然后,这些IF信号被传递通过CFR块,以降低信号的PAPR。对PAPR抑制的信号进行数字预失真,以预补偿功率放大器的非线性失真。
在任一输入模式下,还通过PD中的自适应算法补偿由于自加热产生的记忆效应、偏置网络和有源设备的频率依赖性。通过将来自反馈路径725的宽带捕获输出信号与参考信号同步来调节PD的系数。数字预失真算法执行同步和补偿。预失真信号被传递通过DQM以生成实信号,然后通过所示出的DAC740转换成IF模拟信号。如以上公开的,不需要或根本不需要在所有实施方式中在FPGA中实施DQM。可替代地,如果在FPGA中不使用DQM,则AQM实施可以实施有两个DAC以分别生成实信号和虚信号。功率放大器的栅极偏置电压753通过自适应算法确定,然后通过DAC535进行调节,以稳定由于功率放大器的温度变化导致的线性度波动。
功率放大器部分包括:用于实信号的UPC(诸如在图7中示出的实施方式中所示的),或者用于来自基于FPGA的数字模块的实信号和复信号的AQM(诸如在图8中描绘的DHMPA***的实施方式)、具有多级驱动放大器的高功率放大器、以及温度传感器。为了改善DHMPA***的效率性能,取决于实施方式可以使用效率提升技术,诸如Doherty、包络消除和恢复(EER)、包络跟踪(ET)、包络跟随(EF)和使用非线性部件的线性放大(LINC)。这些功率效率技术可以被混合并匹配,并且对于基础DHMPA***是可选特征。在通过引用合并在本文中的、2007年4月23日递交的标题为“N-WayDohertyDistributedPowerAmplifier”的共同转让的美国临时专利申请60/925,577和2009年10月21日递交的标题为“N-WayDohertyDistributedPowerAmplifierwithPowerTracking”的美国专利申请12/603,419中提出了一种这样的Doherty功率放大器技术。为了稳定放大器的线性度性能,通过温度传感器来监测放大器的温度,然后通过基于FPGA的数字部分来控制放大器的栅极偏置。
反馈部分包括定向耦合器、混频器、增益放大器、带通滤波器(BPF)、和数模转换器(DAC)。取决于实施方式,这些模拟部件可以与其它模拟部件混合并匹配。放大器的RF输出信号部分通过定向耦合器来采样,然后在混频器中通过本地振荡信号下变频成IF模拟信号。IF模拟信号被传递通过增益放大器和可以捕获带外失真的BPF(例如表面声波滤波器)。BPF的输出被提供给基于FPGA的数字模块的ADC,以根据输出功率水平和由于记忆效应导致的非对称失真来确定数字PD的动态参数。另外,还通过检测器580来检测温度以计算线性度的变化然后调节PA的栅极偏置电压。从以上讨论的图3和以上讨论的图4可以了解PD算法和自适应反馈算法的更多细节,其中,图3示出了基于多项式的预失真算法,图4示出了可以在本发明的一些实施方式中使用的数字预失真器同步算法的框图。
在对诸如WiMAX的宽带无线接入或其它基于OFDM的方案具有严格EVM要求的情况下(EVM<2.5%),为满足严格的EVM规范,基于FPGA的数字部分中的CFR仅能够实现PAPR的小的降低。在一般情况下,这意味着CFR的功率效率增强能力是有限的。在本发明的一些实施方式中,包括新颖的技术以通过使用“削波误差恢复路径”790来补偿来自CFR的带内失真,从而使那些严格的EVM环境下的DHMPA***功率效率最大化。如以上提到的,削波误差恢复路径在基于FPGA的数字部分中具有另外的DAC735且在功率放大器部分中具有额外的UPC720(见图7和图8)。削波误差恢复路径使得能够在功率放大器的输出端补偿由CFR产生的带内失真。另外,可以在FPGA中使用数字延迟来对准主路径与削波误差恢复路径之间的延迟失配。
再次参照图7,RF输入信号首先被下变频成基带数字信号,然后被数字上变频成数字IF信号(-7.5MHz、-2.5MHz、2.5MHz、7.5MHz)。如果图7的***具有基带输入模式,则来自多信道的数字数据流在其进入数字处理器时被直接数字上变频成数字IF信号(-7.5MHz、-2.5MHz、2.5MHz、7.5MHz)。然后,CFR降低PAPR。峰值降低的信号被预失真以线性化DPA,并传输通过用于实信号和虚信号的两个DAC,且最终通过AQM。
图9为示出模拟正交调制器补偿结构的实时方式的框图。输入信号被分成同相分量XI和正交分量XQ。模拟正交调制器补偿结构包括四个实滤波器{g11、g12、g21、g22}和两个DC偏置补偿参数c1、c2。通过参数c1、c2补偿AQM中的DC偏置。通过滤波器{g11、g12、g21、g22}补偿AQM的频率依赖性。实滤波器的阶数取决于所需要的补偿水平。输出信号YI和YQ将被提供给AQM的同相端口和正交端口。
图8中示出的***的功率放大器部分和反馈部分的配置与针对图7中示出的***的配置相同。
在图8示出的***中,DNC频率将RF信号转换成低的IF信号。然后,IF信号被提供给ADC,在ADC处,该IF信号在经过CFR和预失真(PD)后被数字下变频成基带。PD的输出为基带信号,基带信号然后被数字上变频成IF频率并被提供给DAC。然后,DAC的输出进一步通过上变频器(UPC)被频率转换成RF频率。图8的***的功率放大器部分和反馈部分的配置与针对图7中示出的***的配置相同。
总之,本发明的DHMPA***能够在一个数字处理器中实施CFR、DPD和自适应算法,结果,这节省了硬件资源和处理时间,因而DHMPA***相对于现有技术提高了效率和线性度。由于可以在数字处理器中在任意时刻像软件一样来调节算法和功率效率提高特征,DHMPA***也是可重构且现场可编程的。
此外,由于DHMPA***接受RF调制信号作为输入,因而不必在基带中使用经过编码的I和Q信道信号。因此,可以简单地通过用DHMPA代替现有PA模块来提高无线基站***的性能。结果是,本发明提供了“即插即用”PA***解决方案,使得对于新的一组信号信道不需要修改或重建现有基站***的结构以便于受益于高效率和高线性度PA***性能。
此外,DHMPA***对于诸如在码分多址(CDMA)、全球无线通信***(GSM)、WCDMA、CDMA2000和无线LAN***中的正交相移键控(QPSK)、正交幅度调制(QAM)、正交频分复用(OFDM)等的调制方案可以不可知。这意味着DHMPA***能够支持多调制方案、多载波和多信道。本发明的DHMPA***的其它的益处包括:在不具有容易获得的必要基带信号信息的中继器或室内覆盖***中对PA非线性度的校正。
尽管已参照优选实施方式描述了本发明,但是应当理解本发明不限于优选实施方式中所描述的细节。在之前的描述中已建议了各种替代和修改,而本领域的普通技术人员会想到其它的替代和修改。因此,所有这样的替代和修改意图被包括在如在所附权利要求中限定的本发明的范围内。
Claims (2)
1.一种数字预失真***,用于线性化功率放大器的输出,所述数字预失真***包括:
用于无线通信的输入信号;
用于输出放大的信号的至少一个功率放大器;
根据所述放大的信号导出的至少一个反馈信号,其中,所述至少一个反馈信号包括所述功率放大器的噪声特性的表示;
数字预失真模块,用于对所述输入信号进行预失真并将预失真的信号提供给所述至少一个功率放大器,其中,所述数字预失真模块至少部分地遵循以下等式:
其中,z(n)为预失真函数,n为表示时间的变量,xt()为输入信号,并且aij为预失真系数,以及
延迟估计模块,其被配置成估计所述输入信号与所述反馈信号之间的延迟,其中,所述延迟估计模块被配置成提供整数延迟或分数延迟;
用于存储预失真系数的存储器;
估计器模块,其被配置成确定预失真系数,其中,所述估计器模块包括最小二乘算法,并且其中所述预失真系数是至少部分地基于所估计的延迟的;以及
选择器,用于在来自所述存储器的预失真系数与来自估计器模块的预失真系数之间进行选择,其中,所述选择器将预失真系数提供给所述数字预失真模块。
2.一种数字预失真***,用于线性化功率放大器的输出,所述数字预失真***包括:
适于无线通信的输入信号;
用于输出放大的信号的至少一个功率放大器;
根据所述放大的信号导出的至少一个反馈信号,所述至少一个反馈信号包括至少一个所述功率放大器的噪声特性的表示;
估计器模块,所述估计器模块对所述至少一个反馈信号进行响应,以至少部分地基于根据由以下等式给出的关联所确定的反馈路径延迟来生成预失真系数:
其中,x(n)表示发送数据,y(n)表示反馈数据,C(m)为关联函数,N为每个块的数据数,m为表示时间的变量,以及其中使得关联函数C(m)最大化的延迟为反馈路径延迟。
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Application Number | Priority Date | Filing Date | Title |
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US28884409P | 2009-12-21 | 2009-12-21 | |
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