CN102870386B - Decision feedback equalizer and receiver - Google Patents
Decision feedback equalizer and receiver Download PDFInfo
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- CN102870386B CN102870386B CN201280000698.6A CN201280000698A CN102870386B CN 102870386 B CN102870386 B CN 102870386B CN 201280000698 A CN201280000698 A CN 201280000698A CN 102870386 B CN102870386 B CN 102870386B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
- H04L25/03885—Line equalisers; line build-out devices adaptive
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- Synchronisation In Digital Transmission Systems (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
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Abstract
The embodiment of the present invention relates to a decision feedback equalizer and a receiver. The equalizer comprises: a receiving end for receiving a first data signal; a first adjusting unit, for performing phase adjustment to a square wave signal outputted by a decider, and performing a signal superposition to the square wave signal after phase adjustment and a first data signal to obtain a second data signal, and then inputting the second data signal to a first input end of the decider; a second adjusting unit for performing phase adjustment along a proceeding phase to the data of the square wave signal outputted by the decider, and then inputting the square wave signal after phase adjustment to the second input end of the decider as a third data signal; a decider for comparing the amplitude of the second data signal of the first input end with the amplitude of the third data signal of the second input end, and inputting the square wave signal into the first adjusting unit and the second adjusting unit. Both the voltage amplitude and data jitter of the adjusted data signal are taken into account.
Description
Technical field
The embodiment of the present invention relates to communication technical field, particularly a kind of DFF and receiver.
Background technology
Along with digital signal technique is towards high-speed high capacity future development, more and more urgent to the demand of two-forty signal processing technology.Intersymbol interference (the Inter Symbollnterference produced in signals transmission, ISI) be the key factor that restrictive signal speed promotes, ISI can cause pulse stretching, cause the voltage amplitude of data-signal unstable, cause the shake on the data edge of data-signal, the error rate (Bit Error Ratio, BER) of channel is caused to increase.
In prior art, feed back to receiving terminal after the data-signal of reception is carried out time delay processing, the data-signal received with receiving terminal superposes, but this method cannot take into account the voltage amplitude of data-signal and the adjustment of data edge shake.
Summary of the invention
The embodiment of the present invention provides a kind of DFF and receiver, realizes the voltage amplitude and the shake of data edge that take into account adjustment data-signal.
On the one hand, embodiments provide a kind of DFF, comprising: receiving terminal, the first adjustment unit, the second adjustment unit and decision device;
Described receiving terminal, for receiving the first data-signal, by the Frequency Synchronization of local clock and described first data-signal, makes the cycle of described local clock consistent with the cycle of described first data-signal;
Described first adjustment unit, square-wave signal for exporting described decision device enters horizontal phasing control, and the square-wave signal after phase place being adjusted superposes with described first data-signal, obtains the second data-signal, and described second data-signal is inputed to the first input end of described decision device;
Described second adjustment unit, the data edge for the described square-wave signal exported described decision device adjusts, and the square-wave signal after adjustment is inputed to the second input of described decision device as the 3rd data-signal;
Described decision device, amplitude for described 3rd data-signal of described second data-signal that inputs described first input end and described second input input compares, export described square-wave signal, and described square-wave signal is inputed to respectively described first adjustment unit and described second adjustment unit.
On the other hand, the embodiment of the present invention provides a kind of receiver, comprising: optical-electrical converter, DFF and clock and data recovery module;
Described photoelectric conversion module, for the light signal of reception is converted to the signal of telecommunication, and inputs to described DFF using the described signal of telecommunication as the first data-signal;
Described DFF comprises: receiving terminal, the first adjustment unit, the second adjustment unit and decision device; Described receiving terminal, for receiving the first data-signal, by the Frequency Synchronization of local clock and described first data-signal, makes the cycle of described local clock consistent with the cycle of described first data-signal; Described first adjustment unit, square-wave signal for exporting described decision device enters horizontal phasing control, and the square-wave signal after phase place being adjusted superposes with described first data-signal, obtains the second data-signal, and described second data-signal is inputed to the first input end of described decision device; Described second adjustment unit, the data edge for the described square-wave signal exported described decision device adjusts, and the square-wave signal after adjustment is inputed to the second input of described decision device as the 3rd data-signal; Described decision device, amplitude for described 3rd data-signal of described second data-signal that inputs described first input end and described second input input compares, export described square-wave signal, and described square-wave signal is inputed to respectively described first adjustment unit and described second adjustment unit;
Described clock recovery module, the square-wave signal that the decision device for receiving described judgement equalizer exports, and local clock is carried out synchronous with described square-wave signal.
The DFF that the embodiment of the present invention provides and receiver, two adjustment units are adopted to adjust the square-wave signal that decision device exports respectively, the data-signal obtained after the adjustment of adjustment unit is added to data-signal that feedback equalizer receives as an input of decision device, realizes regulating the voltage magnitude of data-signal; The data-signal obtained after the adjustment of another adjustment unit, as another input of decision device, realizes the adjustment on the data edge to data-signal, thus can take into account voltage amplitude and the shake of data edge of adjustment data-signal.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of DFF first embodiment provided by the invention;
Fig. 2 is the unit impact response under middle transmission channel embodiment illustrated in fig. 1 exists ISI situation;
Fig. 3 is the structural representation of DFF second embodiment provided by the invention;
Fig. 4 is the structural representation of DFF provided by the invention 3rd embodiment;
Fig. 5 is the structural representation of DFF provided by the invention 4th embodiment;
Fig. 6 is the structural representation of DFF provided by the invention 5th embodiment;
Fig. 7 is the structural representation of receiver first embodiment provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the structural representation of DFF first embodiment provided by the invention, and as shown in Figure 1, this DFF comprises: receiving terminal 11, first adjustment unit 12, second adjustment unit 13 and decision device 14;
Receiving terminal 11, for receiving the first data-signal, by the Frequency Synchronization of local clock and described first data-signal, makes the cycle of described local clock consistent with the cycle of described first data-signal;
First adjustment unit 12, square-wave signal for exporting decision device 14 enters horizontal phasing control, and the square-wave signal after phase place being adjusted superposes with the first data-signal, obtains the second data-signal, and the second data-signal is inputed to the first input end 141 of decision device 14;
Second adjustment unit 13, the data edge for the square-wave signal exported decision device 14 adjusts, and the square-wave signal after adjustment is inputed to the second input 142 of decision device 14 as the 3rd data-signal;
Decision device 14, voltage magnitude for the 3rd data-signal of the second data-signal of inputting first input end 141 and the input of the second input 142 compares, export described square-wave signal, and described square-wave signal is inputed to respectively the first adjustment unit 12 and the second adjustment unit 13.
The DFF that the embodiment of the present invention provides, can be arranged on multiple optical network device, such as: Optical Network Terminal (Optical Line Terminal can be arranged on, OLT), also optical network unit (Optical Network Unit can be arranged on, ONU), on, optical network unit (Optical network terminal, ONT) can also be arranged on.This DFF can adjust along (edge) the voltage magnitude of the data-signal that transmitting terminal sends and data.
In the DFF that the embodiment of the present invention provides, comprise two feedback loops, wherein, output and first adjustment unit 12 of decision device 14 form a feedback loop, and the voltage magnitude for the square-wave signal exported the output of decision device 14 adjusts; Second input 142 of the output of decision device 14, the second adjustment unit 13 and decision device 14 forms another feedback loop, for the data of square-wave signal that export the output of decision device 14 along adjusting.
The data-signal sent due to transmitting terminal is generally square-wave signal, and these data-signals are after the transmission of transmission link, interference signal can be mingled with in the first data-signal that receiving terminal receives, make data-signal distortion, such as: the period ratio of data-signal is comparatively large, hangover (tailing) time of the unit impact response of data-signal is longer etc.After the adjustment of the first adjustment unit 12, the square-wave signal of the output output of decision device 14, the interference of channel to the voltage magnitude of described square-wave signal reduces; After the adjustment of the second adjustment unit 13, the square-wave signal of the output output of decision device 14, the shake on the data edge of described square-wave signal reduces.
Decision device 14 can adopt existing various comparator to realize, or the logical circuit that logical device can also be adopted to form realizes.The voltage magnitude of decision device 14 to the second data-signal and the 3rd data-signal compares, under one implements scene, the voltage magnitude of the second data-signal of synchronization is greater than the voltage magnitude of the 3rd data-signal, then decision device 14 can export high level, if the voltage magnitude of the second data-signal is less than the voltage magnitude of the 3rd data-signal, then decision device 14 can output low level.Or, the voltage magnitude of the second data-signal of synchronization is greater than the voltage magnitude of the 3rd data-signal, then decision device 14 can output low level, if the voltage magnitude of the second data-signal is less than the voltage magnitude of the 3rd data-signal, then decision device 14 can export high level.The low and high level composition square-wave signal that decision device 14 exports, this square-wave signal inputs in the first adjustment unit 12 and the second adjustment unit 13 respectively.
Optionally, first adjustment unit 12 can be specifically for: carry out phase delay at least one times to square-wave signal, an integral multiple cycle of local clock described in each phase delay, each phase delay obtains first inhibit signal, therefore, carry out repeatedly phase delay and just obtain multiple first inhibit signal, multiple inhibit signal is superposed with the first data-signal and obtains the second data-signal.If the first adjustment unit 12 pairs square-wave signal carries out a phase delay, just have to first inhibit signal, so, the second data-signal is exactly the first inhibit signal itself.
Optionally, second adjustment unit 3 can be specifically for: carry out phase delay at least one times to square-wave signal, an odd-multiple half period of local clock described in each phase delay, each phase delay obtains first inhibit signal, therefore, carry out repeatedly phase delay and just obtain multiple second inhibit signal, multiple second inhibit signal superposition is obtained the 3rd data-signal.If the second adjustment unit 3 pairs square-wave signal carries out a phase delay, just have to second inhibit signal, so, the 3rd data-signal is exactly the second inhibit signal itself.
In transmission channel empty situation between transmitting terminal and receiving terminal, input square wave test signal, obtain unit impact response figure as shown in Figure 2, Fig. 2 is the unit impact response under transmission channel between transmitting terminal and receiving terminal exists ISI situation, solid-line curve represents that the time domain waveform that the data-signal of current time produces at receiving terminal through transmission channel, imaginary curve represent the time domain waveform that the data-signal of previous moment produces at receiving terminal.As can be seen from Figure 2, for the voltage magnitude of data-signal, except the voltage magnitude that current data signal produces, also previous moment can be superposed, even more early the voltage that produces at current time of the data-signal in moment.Further, to the moment in an integral multiple cycle of the mainly data-signal that the voltage magnitude of current data signal has an impact, that is, 0, T, 2T ..., nT.Therefore, data-signal can be expressed as at the voltage magnitude of current time: α 1*T+ α 2*2T+......+ α n*nT.Wherein, α 1, α 2 ... α n are coefficient, the value of α 1, α 2 ... α n can calculate acquisition according to Fig. 2, such as: the value of unit impact response at current sample time and the ratio of unit impact response peak value can be chosen, wherein, current sample time is an integral multiple cycle of data-signal.Accordingly, first adjustment unit 12 can carry out repeatedly phase delay to square-wave signal, in an integral multiple cycle of local clock described in each phase delay, obtains multiple first inhibit signal, and multiple first inhibit signal is superposed with the first data-signal, obtain the second data-signal.Superpose the last cycle in this second data-signal, even more early the data-signal in cycle, therefore, eliminate the voltage magnitude interference in the square-wave signal of decision device 14 output.
Similar, for the data edge of data-signal, that is, the trailing portion of data-signal, except comprising voltage that current data signal produces, also superpose the data-signal of previous moment, the voltage that the hangover of even more front data-signal produces at current time.And to the data of the current data signal moment along an odd-multiple half period of the mainly data-signal had an impact, that is, T/2,3T/2 ..., (2n+1) T/2.Therefore, data-signal can be expressed as on the data edge of current time: 0.5-(β 1-0.5) * T/2-(β 2-0.5) * 3T/2-...-(β n-0.5) * (2n+1) T/2).Wherein, β 1, β 2 ... β n are coefficient, the value of β 1, β 2 ... β n can calculate acquisition according to Fig. 2, such as: the value of unit impact response at current sample time and the ratio of unit impact response peak value can be chosen, wherein, current sample time can be an odd-multiple half period of data-signal.Accordingly, the second adjustment unit 13 can carry out repeatedly phase delay to square-wave signal, an odd-multiple half period of local clock described in each phase delay, obtains multiple second inhibit signal, and described multiple second inhibit signal superposition is obtained the 3rd data-signal.Superposed front half period in 3rd data-signal, the data-signal of half period even more early, therefore, the data eliminated in the square-wave signal of decision device 14 output are disturbed along hangover.
The DFF that the present embodiment provides, two adjustment units are adopted to enter horizontal phasing control to the square-wave signal that decision device exports respectively, the data-signal obtained after the adjustment of adjustment unit is added to data-signal that feedback equalizer receives as an input of decision device, realizes regulating the voltage magnitude of data-signal; The data-signal obtained after the adjustment of another adjustment unit, as another input of decision device, realizes regulating the data edge of data-signal, thus can take into account voltage amplitude and the shake of data edge of adjustment data-signal.
Fig. 3 is the structural representation of DFF second embodiment provided by the invention, and as shown in Figure 3, as a kind of feasible structure, the first adjustment unit 12 can comprise: the first time delay module 21, first coefficient module 22 and superimposer 23;
First time delay module 21, for carrying out a phase delay to square-wave signal, the integral multiple cycle postponing described local clock obtains the 3rd inhibit signal, and the 3rd inhibit signal is inputed to the first coefficient module 22;
First coefficient module 22, the voltage magnitude for the 3rd inhibit signal inputted the first time delay module 21 adjusts, and obtains the first inhibit signal, and the first inhibit signal is inputed to superimposer 23;
Superimposer 23, superposes with the first data-signal for the first inhibit signal the first coefficient module 22 inputted, and the second data-signal obtained is inputed to the first input end 141 of decision device 14.
Voltage magnitude based on previously described data-signal current time can be expressed as:
α1＊T+α2＊2T+......+αn＊nT。
Multiple first time delay module 21 can be set at the first adjustment unit 12, these the first time delay modules 21 can be respectively used to carry out a phase delay to square-wave signal, obtain multiple 3rd inhibit signals obtained after square-wave signal postpones T, 2T ... nT respectively.That is, the phase place that each first time delay module 21 postpones can be different, and multiple first time delay module 21 can be respectively used to square-wave signal be postponed T, 2T ... nT.
Accordingly, multiple first coefficient module 22 can be set at the first adjustment unit 12, each first coefficient module 22 can be corresponding with a first time delay module 21, such as: first coefficient module 22 can be corresponding with the first time delay module 21 for square-wave signal being postponed T, may be used for by postpone through this first time delay module 21 adjust after obtain the 3rd inhibit signal voltage magnitude adjustment, such as be multiplied by α 1, obtain the first inhibit signal; Another first coefficient module 22 can be corresponding with the first time delay module 21 for square-wave signal being postponed 2T, may be used for the range-adjusting of the 3rd inhibit signal will obtained after postponing through this first time delay module 21 to adjust, such as be multiplied by α 2, obtain the first inhibit signal; ... first coefficient module 22 can be corresponding with the first time delay module 21 for square-wave signal being postponed nT, may be used for the range-adjusting of the 3rd inhibit signal will obtained after postponing through this first time delay module 21 to adjust, such as be multiplied by α n, obtain the first inhibit signal.
Superimposer 23 can adopt the devices such as such as adder, for being connected with the first coefficient module 22, the first inhibit signal that first coefficient module 22 inputs is superposed with the first data-signal, the second data-signal obtained is inputed to the first input end 141 of decision device 14.
In order to simplify the structure of the first adjustment unit 12, as a kind of feasible execution mode, as shown in Figure 3, many first time delay modules 21 in first adjustment unit 12 can be arranged in series, the input of each first coefficient module 22 can be connected with the output of a first time delay module 21, and the output of each first coefficient module 22 is connected with the input of superimposer 23.Under this enforcement scene, the time of delay of each first time delay module 21 pairs of square-wave signals can be equal, such as: all can postpone one-period T.
Optionally, the number of the first time delay module 21 between adjacent first coefficient module 22 is equal, as shown in Figure 3, a first time delay module 21 all can be set between adjacent first coefficient module 22, thus the first adjustment unit 12 all can be added to the data-signal in each front integral multiple cycle of current time data-signal on current time data-signal, realize the voltage magnitude of the data-signal in each the front integral multiple cycle at elimination current time data-signal to the impact of current data signal voltage magnitude.
Fig. 4 is the structural representation of DFF provided by the invention 3rd embodiment, and as shown in Figure 4, as a kind of feasible structure, the second adjustment unit 13 can comprise: the second time delay module 31 and the second coefficient module 32;
Second time delay module 31, for carrying out a phase delay to square-wave signal, the odd-multiple half period postponing described local clock obtains the 4th inhibit signal, and the 4th inhibit signal is inputed to the second coefficient module 32;
Second coefficient module 32, the voltage magnitude for the 4th inhibit signal inputted the second time delay module 31 adjusts, and obtains the second inhibit signal, and the second inhibit signal is inputed to the second input 142 of decision device 14.
Second time delay module 31 may be used for carrying out phase delay to square-wave signal, can obtain the 4th inhibit signal obtained after square-wave signal postpones T/2 or 3T/2 ... or (2n+1) T/2.
Accordingly, the second coefficient module 32 may be used for by postpone through this second time delay module 31 adjust after obtain the 4th inhibit signal voltage magnitude adjustment, obtain second inhibit signal.Wherein, the voltage magnitude adjusting range of the second coefficient module 32 can according to different from the difference of second time delay module 31 time of delay.
Optionally, if square-wave signal is postponed T/2 by the second time delay module 31, then the second coefficient module 32 can by postpone through this second time delay module 31 adjust after obtain the 4th inhibit signal voltage magnitude adjustment, be such as multiplied by (β 1-0.5), obtain second inhibit signal; Or, if square-wave signal is postponed 3T/2 by the second time delay module 31, then the second coefficient module 32 can by postpone through this second time delay module 31 adjust after obtain the 4th inhibit signal voltage magnitude adjustment, be such as multiplied by (β 2-0.5), obtain second inhibit signal; ... or, square-wave signal is postponed (2n+1) T/2 by the second time delay module 31, then the second coefficient module 32 can by postpone through this second time delay module 31 adjust after obtain the 4th inhibit signal voltage magnitude adjustment, such as be multiplied by (β n-0.5), obtain second inhibit signal.
In the present embodiment, due to second inhibit signal that the second adjustment unit 13 obtains, therefore, this second inhibit signal itself is the 3rd data-signal, and the second delay time signal obtained (i.e. the 3rd data-signal) inputs in the second input 142 of decision device 14 by the second coefficient module 32.
Fig. 5 is the structural representation of DFF provided by the invention 4th embodiment, and as shown in Figure 5, as a kind of feasible structure, the second adjustment unit 13 can comprise: the second time delay module 31, second coefficient module 32 and subtracter 33;
Second time delay module 31, for carrying out a phase delay to square-wave signal, the odd-multiple half period postponing described local clock obtains the 4th inhibit signal, and the 4th inhibit signal is inputed to the second coefficient module 32;
Second coefficient module 32, the voltage magnitude for the 4th inhibit signal inputted the second time delay module 31 adjusts, and obtains the second inhibit signal, and the second inhibit signal is inputed to subtracter 33;
Subtracter 33, superposes for the second inhibit signal the second coefficient module 32 inputted, and the 3rd data-signal obtained is inputed to the second input 142 of decision device 14.
Optionally, multiple second time delay module 31 can be arranged in series, and the input of each second coefficient module 32 is connected with the output of a second time delay module 31, and the output of each second coefficient module 32 is connected with the input of subtracter 33.
Data edge based on previously described data-signal current time can be expressed as:
0.5-(β1-0.5)＊T/2-(β2-0.5)＊3T/2-...-(βn-0.5)＊(2n+1)T/2)。
Multiple second time delay module 31, can be respectively used to carry out phase delay to square-wave signal, obtains multiple 4th inhibit signals obtained after square-wave signal postpones T/2,3T/2 ... (2n+1) T/2 respectively.That is, the phase place that each second time delay module 31 postpones can be different, and multiple first time delay module 21 can be respectively used to square-wave signal be postponed T/2,3T/2 ... (2n+1) T/2.
Accordingly, each second coefficient module 32 can be corresponding with a second time delay module 31, such as: second coefficient module 32 can be corresponding with the second time delay module 31 for square-wave signal being postponed T/2, may be used for by postpone through this second time delay module 31 adjust after obtain the 4th inhibit signal voltage magnitude adjustment, such as be multiplied by (β 1-0.5), obtain second inhibit signal; Another second coefficient module 32 can be corresponding with the second time delay module 31 for square-wave signal being postponed 3T/2, may be used for by postpone through this second time delay module 31 adjust after obtain the 4th inhibit signal voltage magnitude adjustment, such as be multiplied by (β 2-0.5), obtain second inhibit signal; ... second coefficient module 32 can be corresponding with the second time delay module 31 for square-wave signal being postponed (2n+1) T/2, may be used for by postpone through this second time delay module 31 adjust after obtain the 4th inhibit signal voltage magnitude adjustment, such as be multiplied by (β n-0.5), obtain second inhibit signal.
Subtracter 33, may be used for being connected with multiple second coefficient module 32, and the multiple second inhibit signals superpositions multiple second coefficient module 32 inputted, will obtain the 3rd data-signal and input to the second input 142 of decision device 14.
In order to simplify the structure of the first adjustment unit 13, as a kind of feasible execution mode, as shown in Figure 5, multiple second time delay modules 31 in first adjustment unit 13 can be arranged in series, the input of each second coefficient module 32 can be connected with the output of a second time delay module 31, and the output of each second coefficient module 32 is connected with the input of subtracter 33.Under this enforcement scene, the time of delay of each second time delay module 31 pairs of square-wave signals can be equal, such as: all can postpone half period T/2.
Optionally, the number of the second time delay module 31 between adjacent second coefficient module 32 is equal, as shown in Figure 5, a second time delay module 31 all can be set between adjacent second coefficient module 32, thus the second adjustment unit 13 all can be added to the data-signal of each front odd-multiple half period of current time data-signal on current time data-signal, realize the impact of data edge on current data signal data edge at the data-signal of each front odd-multiple half period of eliminating current time data-signal.
On the basis of the embodiment of the DFF shown in Fig. 3 and Fig. 5, in order to the structure of DFF simplified further, as shown in Figure 6, optionally, second time delay of every two series connection in the second adjustment unit 13 adjusts 31 modules, can as a first time delay adjusting module 21 in the first adjustment unit 12.
In embodiment shown in Fig. 6, the delay time that each second time delay adjusts 31 modules can be the half period, multiple second time delay adjustment 31 of series connection belong to two feedback loops be made up of the first adjustment unit 12 and the second adjustment unit 13 respectively, the time delay belonging to the feedback loop of the first adjustment unit 12 is an integral multiple cycle, and the feedback delay belonging to the feedback loop of the second adjustment unit 13 is an odd-multiple half period.The signal that the first input end 141 of decision device 14 inputs is: the data-signal after current data signal and an integral multiple cycle time delay, can be expressed by expression formula α 1*T+ α 2*2T+......+ α n*nT; The signal that second input 142 of decision device 14 inputs is: the data-signal after an odd-multiple half period time delay, can pass through expression formula:
0.5-(β 1-0.5) * T/2-(β 2-0.5) * 3T/2-...-(β n-0.5) * (2n+1) T/2) express.
The DFF that the present embodiment provides, form a feedback loop by the output of decision device 14 and the first adjustment unit 12 to adjust the voltage magnitude of the square-wave signal that decision device 14 exports, the feedback loop be made up of the second input 142 of the output of decision device 14, the second adjustment unit 13 and decision device 14 can export the data of square-wave signal along adjusting to decision device 14, can realize voltage magnitude and the data edge of taking into account adjustment data-signal.
Fig. 7 is the structural representation of receiver first embodiment provided by the invention, and as shown in Figure 7, this receiver comprises: optical-electrical converter 41, DFF 42 and clock and data recovery module 43;
Photoelectric conversion module 41, for the light signal of reception is converted to the signal of telecommunication, and inputs to DFF using the signal of telecommunication as the first data-signal;
This DFF 42 can be the DFF that above embodiment discloses; Can comprise: receiving terminal, the first adjustment unit, the second adjustment unit and decision device; Receiving terminal, for receiving the first data-signal; First adjustment unit, enters horizontal phasing control for the square-wave signal exported decision device, and the square-wave signal after phase place being adjusted superposes with the first data-signal, obtains the second data-signal, and the second data-signal is inputed to the first input end of decision device; Second adjustment unit, horizontal phasing control is entered on the data edge for the square-wave signal exported decision device, and the square-wave signal after adjustment is inputed to the second input of decision device as the 3rd data-signal; Decision device, the amplitude for the 3rd data-signal of the second data-signal of inputting first input end and the input of the second input compares, and exports square-wave signal, and square-wave signal is inputed to respectively the first adjustment unit and the second adjustment unit;
Clock recovery module 43, the square-wave signal that the decision device for receiving judgement equalizer exports, and local clock is carried out synchronous with square-wave signal.Concrete, clock recovery module 43 pairs of local clocks synchronously process, make the phase place of local clock and the square-wave signal received and frequency consistent so that it is accurate to sample.
The receiver that the embodiment of the present invention provides can be the optical network devices such as OLT, ONU or ONT, the DFF embodiment that the structure of DFF wherein and function thereof can provide with reference to Fig. 1-Fig. 6 of the present invention, does not repeat them here.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that program command is relevant.Aforesaid program can be stored in computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (15)
1. a DFF, is characterized in that, comprising: receiving terminal, the first adjustment unit, the second adjustment unit and decision device;
Described receiving terminal, for receiving the first data-signal, by the Frequency Synchronization of local clock and described first data-signal, makes the cycle of described local clock consistent with the cycle of described first data-signal;
Described first adjustment unit, square-wave signal for exporting described decision device enters horizontal phasing control, and the square-wave signal after phase place being adjusted superposes with described first data-signal, obtains the second data-signal, and described second data-signal is inputed to the first input end of described decision device;
Described second adjustment unit, the data edge for the described square-wave signal exported described decision device adjusts, and the square-wave signal after adjustment is inputed to the second input of described decision device as the 3rd data-signal;
Described decision device, voltage magnitude for described 3rd data-signal of described second data-signal that inputs described first input end and described second input input compares, export described square-wave signal, and described square-wave signal is inputed to respectively described first adjustment unit and described second adjustment unit.
2. DFF according to claim 1, it is characterized in that, described first adjustment unit specifically for: phase delay is at least one times carried out to described square-wave signal, an integral multiple cycle of local clock described in each phase delay, obtain at least one first inhibit signal, at least one first inhibit signal described is superposed with described first data-signal and obtains described second data-signal;
Described second adjustment unit specifically for: phase delay is at least one times carried out to described square-wave signal, an odd-multiple half period of local clock described in each phase delay, obtain at least one second inhibit signal, if the second inhibit signal has multiple, described multiple second inhibit signal is carried out superposition and obtains described 3rd data-signal, if the second inhibit signal only has one, the second inhibit signal is described 3rd data-signal inherently.
3. DFF according to claim 2, is characterized in that, described first adjustment unit comprises: the first time delay module, the first coefficient module and superimposer;
Described first time delay module, for carrying out phase delay to described square-wave signal, the integral multiple cycle postponing described local clock obtains the 3rd inhibit signal, and described 3rd inhibit signal is inputed to described first coefficient module;
Described first coefficient module, the voltage magnitude for described 3rd inhibit signal to described first time delay module input adjusts, and obtains described first inhibit signal, and described first inhibit signal is inputed to described superimposer;
Described superimposer, for the first inhibit signal of described first coefficient module input being superposed with described first data-signal, inputs to the described first input end of described decision device by described second data-signal obtained.
4. DFF according to claim 3, it is characterized in that, described first coefficient module, for being multiplied by α n to the voltage magnitude of described 3rd inhibit signal, the value of α n is the value of unit impulse response at current sample time and the ratio of unit impact response peak value, and wherein, n is the numerical value in an integral multiple cycle of described local clock, n is integer, and current sample time is a n doubly cycle of described local clock.
5. DFF according to claim 3, it is characterized in that, multiple first time delay block coupled in series, the input of each described first coefficient module is connected with the output of a described first time delay module, and the output of each described first coefficient module is connected with the input of described superimposer.
6. DFF according to claim 3, is characterized in that, the delay time of each described first time delay module to described square-wave signal is equal, and the number of the described first time delay module between adjacent described first coefficient module is equal.
7. DFF according to claim 3, is characterized in that, described second adjustment unit comprises: the second time delay module and the second coefficient module;
Described second time delay module, for carrying out time lag of first order to described square-wave signal, the odd-multiple half period postponing described local clock obtains the 4th inhibit signal, and described 4th inhibit signal is inputed to described second coefficient module;
Described second coefficient module, the voltage magnitude for described 4th inhibit signal to described second time delay module input adjusts, and obtains described second inhibit signal, and described second inhibit signal is inputed to the second input of described decision device.
8. DFF according to claim 7, it is characterized in that, described second coefficient module, for being multiplied by (β m-0.5) the voltage magnitude of described 4th inhibit signal, the value of β m is the value of unit impulse response at current sample time and the ratio of unit impact response peak value, and wherein, m is the numerical value of an odd-multiple half period of described local clock, m is odd number, and current sample time is a m doubly half period of described local clock.
9. DFF according to claim 2, is characterized in that, described second adjustment unit comprises the second time delay module, the second coefficient module and subtracter,
Described second time delay module, for carrying out time lag of first order to described square-wave signal, the odd-multiple half period postponing described local clock obtains the 4th inhibit signal, and described 4th inhibit signal is inputed to described second coefficient module;
Described second coefficient module, the voltage magnitude for described 4th inhibit signal to described second time delay module input adjusts, and obtains described second inhibit signal, and described second inhibit signal is inputed to described subtracter;
Described subtracter is used for the second inhibit signal of described second coefficient module input to superpose, and described 3rd data-signal obtained is inputed to the second input of described decision device.
10. DFF according to claim 9, it is characterized in that, described second coefficient module, for being multiplied by (β m-0.5) the voltage magnitude of described 4th inhibit signal, the value of β m is the value of unit impulse response at current sample time and the ratio of unit impact response peak value, and wherein, m is the numerical value of an odd-multiple half period of described local clock, m is odd number, and current sample time is a m doubly half period of described local clock.
11. DFF according to claim 7, it is characterized in that, described second adjustment unit also comprises subtracter, described subtracter is used for the second inhibit signal of described second coefficient module input to superpose, and described 3rd data-signal obtained is inputed to the second input of described decision device;
Multiple second time delay block coupled in series, the input of each described second coefficient module is connected with the output of a described second time delay module, and the output of each described second coefficient module is connected with the input of described subtracter.
12. DFF according to claim 7, is characterized in that, the delay time of each described second time delay module to described square-wave signal is equal, and the number of the described second time delay module between adjacent described second coefficient module is equal.
13. DFF according to claim 11 or 12, is characterized in that, the described second time delay modules of every two series connection in described second adjustment unit, as the described first time delay module of in described first adjustment unit.
14. 1 kinds of receivers, is characterized in that, comprising: optical-electrical converter, clock and data recovery module and the DFF according to any one of claim 1-13;
Described optical-electrical converter, for the light signal of reception is converted to the signal of telecommunication, and inputs to described DFF using the described signal of telecommunication as the first data-signal;
Described clock and data recovery module, for receiving the square-wave signal that in described judgement equalizer, decision device exports, and carries out synchronous by local clock with described square-wave signal.
15. receivers according to claim 14, is characterized in that, described receiver is Optical Network Terminal OLT, optical network unit ONU or optical network unit ONT.
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| PCT/CN2012/077339 WO2013189073A1 (en) | 2012-06-21 | 2012-06-21 | Decision feedback equalizer and receiver |
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| US10069654B2 (en) * | 2015-11-10 | 2018-09-04 | Huawei Technologies Co., Ltd. | Methods to minimize the recovered clock jitter |
| CN105978541B (en) * | 2016-04-28 | 2019-05-10 | 福州大学 | A kind of method of achievable fast signal tracking |
| CN109254942B (en) * | 2018-08-01 | 2021-10-08 | 中国科学院微电子研究所 | Method and device for adjusting bus signals |
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| US7106099B1 (en) * | 2004-10-22 | 2006-09-12 | Xilinx, Inc. | Decision-feedback equalization clocking apparatus and method |
| CN101425851B (en) * | 2008-12-06 | 2011-11-30 | 华中科技大学 | Electronic chromatic dispersion compensation equalizer for optical communication and tap regulation method |
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