CN102870386A - Decision feedback equalizer and receiver - Google Patents
Decision feedback equalizer and receiver Download PDFInfo
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- CN102870386A CN102870386A CN2012800006986A CN201280000698A CN102870386A CN 102870386 A CN102870386 A CN 102870386A CN 2012800006986 A CN2012800006986 A CN 2012800006986A CN 201280000698 A CN201280000698 A CN 201280000698A CN 102870386 A CN102870386 A CN 102870386A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
- H04L25/03885—Line equalisers; line build-out devices adaptive
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Abstract
The embodiment of the present invention relates to a decision feedback equalizer and a receiver. The equalizer comprises: a receiving end for receiving a first data signal; a first adjusting unit, for performing phase adjustment to a square wave signal outputted by a decider, and performing a signal superposition to the square wave signal after phase adjustment and a first data signal to obtain a second data signal, and then inputting the second data signal to a first input end of the decider; a second adjusting unit for performing phase adjustment along a proceeding phase to the data of the square wave signal outputted by the decider, and then inputting the square wave signal after phase adjustment to the second input end of the decider as a third data signal; a decider for comparing the amplitude of the second data signal of the first input end with the amplitude of the third data signal of the second input end, and inputting the square wave signal into the first adjusting unit and the second adjusting unit. Both the voltage amplitude and data jitter of the adjusted data signal are taken into account.
Description
Technical field
The embodiment of the invention relates to communication technical field, particularly a kind of DFF and receiver.
Background technology
Along with digital signal technique towards the high-speed high capacity future development, more and more urgent to the demand of two-forty signal processing technology.The intersymbol interference that produces in the signals transmission (Inter Symbol lnterference, ISI) be the key factor that restrictive signal speed promotes, ISI can cause pulse stretching, cause the voltage amplitude of data-signal unstable, cause the shake on the data edge of data-signal, cause the error rate (Bit Error Ratio, BER) of channel to increase.
In the prior art, the data-signal that receives is carried out feeding back to receiving terminal after the time delay processing, the data-signal that receives with receiving terminal superposes, yet this method can't be taken into account the voltage amplitude of data-signal and data along the adjustment of shake.
Summary of the invention
The embodiment of the invention provides a kind of DFF and receiver, realizes taking into account the voltage amplitude of adjusting data-signal and data along shake.
On the one hand, the embodiment of the invention provides a kind of DFF, comprising: receiving terminal, the first adjustment unit, the second adjustment unit and decision device;
Described receiving terminal is used for receiving the first data-signal, with the Frequency Synchronization of local clock and described the first data-signal, so that the cycle of described local clock is consistent with the cycle of described the first data-signal;
Described the first adjustment unit, be used for the square-wave signal of described decision device output is carried out the phase place adjustment, and the square-wave signal after the phase place adjustment and described the first data-signal superposeed, obtain the second data-signal, and described the second data-signal is inputed to the first input end of described decision device;
Described the second adjustment unit adjust for the data edge of the described square-wave signal that described decision device is exported, and the square-wave signal after will adjusting inputs to the second input of described decision device as the 3rd data-signal;
Described decision device, amplitude for described the 3rd data-signal that described the second data-signal and described second input of described first input end input are inputted compares, export described square-wave signal, and described square-wave signal is inputed to respectively described the first adjustment unit and described the second adjustment unit.
On the other hand, the embodiment of the invention provides a kind of receiver, comprising: optical-electrical converter, DFF and clock and data recovery module;
Described photoelectric conversion module, the light signal that is used for receiving is converted to the signal of telecommunication, and the described signal of telecommunication is inputed to described DFF as the first data-signal;
Described DFF comprises: receiving terminal, the first adjustment unit, the second adjustment unit and decision device; Described receiving terminal is used for receiving the first data-signal, with the Frequency Synchronization of local clock and described the first data-signal, so that the cycle of described local clock is consistent with the cycle of described the first data-signal; Described the first adjustment unit, be used for the square-wave signal of described decision device output is carried out the phase place adjustment, and the square-wave signal after the phase place adjustment and described the first data-signal superposeed, obtain the second data-signal, and described the second data-signal is inputed to the first input end of described decision device; Described the second adjustment unit adjust for the data edge of the described square-wave signal that described decision device is exported, and the square-wave signal after will adjusting inputs to the second input of described decision device as the 3rd data-signal; Described decision device, amplitude for described the 3rd data-signal that described the second data-signal and described second input of described first input end input are inputted compares, export described square-wave signal, and described square-wave signal is inputed to respectively described the first adjustment unit and described the second adjustment unit;
Described clock recovery module is used for receiving the square-wave signal of the decision device output of described judgement equalizer, and local clock and described square-wave signal are carried out synchronously.
The DFF that the embodiment of the invention provides and receiver, adopt two adjustment units respectively the square-wave signal of decision device output to be adjusted, the data-signal that obtains after adjustment unit adjustment is added to data-signal that feedback equalizer receives as an input of decision device, realizes the voltage magnitude of data-signal is regulated; The data-signal that obtains after another adjustment unit adjustment is as another input of decision device, realizes the adjustment to the data edge of data-signal, thereby can take into account the voltage amplitude of adjusting data-signal and data along shake.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of DFF the first embodiment provided by the invention;
Fig. 2 is that middle transmission channel embodiment illustrated in fig. 1 exists the unit impact response in the ISI situation;
Fig. 3 is the structural representation of DFF the second embodiment provided by the invention;
Fig. 4 is the structural representation of DFF the 3rd embodiment provided by the invention;
Fig. 5 is the structural representation of DFF the 4th embodiment provided by the invention;
Fig. 6 is the structural representation of DFF the 5th embodiment provided by the invention;
Fig. 7 is the structural representation of receiver the first embodiment provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Fig. 1 is the structural representation of DFF the first embodiment provided by the invention, and as shown in Figure 1, this DFF comprises: receiving terminal 11, the first adjustment unit 12, the second adjustment unit 13 and decision device 14;
Receiving terminal 11 is used for receiving the first data-signal, with the Frequency Synchronization of local clock and described the first data-signal, so that the cycle of described local clock is consistent with the cycle of described the first data-signal;
The first adjustment unit 12, be used for the square-wave signal of decision device 14 outputs is carried out the phase place adjustment, and the square-wave signal after the phase place adjustment and the first data-signal superposeed, obtain the second data-signal, and the second data-signal is inputed to the first input end 141 of decision device 14;
The second adjustment unit 13 adjust for the data edge of the square-wave signal that decision device 14 is exported, and the square-wave signal after will adjusting inputs to the second input 142 of decision device 14 as the 3rd data-signal;
The DFF that the embodiment of the invention provides, can be arranged on the multiple light network equipment, for example: can be arranged on Optical Network Terminal (Optical Line Terminal, OLT), also can be arranged on optical network unit (Optical Network Unit, ONU) on, can also be arranged on optical network unit (Optical network terminal, ONT).Voltage magnitude and the data of the data-signal that this DFF can send transmitting terminal are adjusted along (edge).
In the DFF that the embodiment of the invention provides, comprise two feedback loops, wherein, the output of decision device 14 and the first adjustment unit 12 consist of a feedback loop, adjust for the voltage magnitude of the square-wave signal that the output of decision device 14 is exported; The second input 142 of the output of decision device 14, the second adjustment unit 13 and decision device 14 consists of another feedback loop, adjusts for the data edge of the square-wave signal that the output of decision device 14 is exported.
Because the data-signal that transmitting terminal sends is generally square-wave signal, and these data-signals are through after the transmission of transmission link, can be mingled with interference signal in the first data-signal that receiving terminal receives, so that data-signal distortion, for example: the period ratio of data-signal is larger, and the hangover of the unit impact response of data-signal (tailing) time is long etc.After the adjustment through the first adjustment unit 12, the square-wave signal of the output of decision device 14 output, channel reduces to the interference of the voltage magnitude of described square-wave signal; After the adjustment through the second adjustment unit 13, the square-wave signal of the output of decision device 14 output, the shake on the data edge of described square-wave signal reduces.
Optionally, the first adjustment unit 12 can specifically be used for: square-wave signal is carried out at least one times phase delay, an integral multiple cycle of each described local clock of phase delay, each phase delay obtains first inhibit signal, therefore, carry out repeatedly phase delay and just obtain a plurality of the first inhibit signals, a plurality of inhibit signals and the stack of the first data-signal are obtained the second data-signal.If 12 pairs of square-wave signals of the first adjustment unit carry out phase delay one time, just have to first inhibit signal, so, the second data-signal is exactly the first inhibit signal itself.
Optionally, the second adjustment unit 3 can specifically be used for: square-wave signal is carried out at least one times phase delay, an odd-multiple half period of each described local clock of phase delay, each phase delay obtains first inhibit signal, therefore, carry out repeatedly phase delay and just obtain a plurality of the second inhibit signals, a plurality of the second inhibit signal stacks are obtained the 3rd data-signal.If 3 pairs of square-wave signals of the second adjustment unit carry out phase delay one time, just have to second inhibit signal, so, the 3rd data-signal is exactly the second inhibit signal itself.
In the transmission channel empty situation between transmitting terminal and the receiving terminal, input square-wave test signal, obtain unit impact response figure as shown in Figure 2, Fig. 2 is that the transmission channel between transmitting terminal and the receiving terminal exists the unit impact response in the ISI situation, solid-line curve represents the time domain waveform that the data-signal of current time produces at receiving terminal through transmission channel, and imaginary curve represents the time domain waveform that the data-signal of previous moment produces at receiving terminal.As can be seen from Figure 2, for the voltage magnitude of data-signal, except when outside the voltage magnitude that front data-signal produces, the previous moment that also can superpose, even the voltage that more morning, data-signal constantly produced at current time.And what the voltage magnitude of current data signal was exerted an influence mainly is the moment in an integral multiple cycle of data-signal, that is, 0, T, 2T ..., nT.Therefore, data-signal can be expressed as at the voltage magnitude of current time: α 1*T+ α 2*2T+......+ α n*nT.Wherein, α 1, α 2 ... α n is coefficient, α 1, α 2 ... the value of α n can be calculated acquisition according to Fig. 2, for example: can choose unit impact response at the value of current sampling instant and the ratio of unit impact response peak value, wherein, current sampling instant is an integral multiple cycle of data-signal.Accordingly, the first adjustment unit 12 can carry out repeatedly phase delay to square-wave signal, in an integral multiple cycle of each described local clock of phase delay, obtains a plurality of the first inhibit signals, and with a plurality of the first inhibit signals and the stack of the first data-signal, obtain the second data-signal.Superposeed the last cycle in this second data-signal, even the data-signal in cycle more early, therefore, the voltage magnitude of having eliminated in the square-wave signal of decision device 14 outputs disturbs.
Similarly, for the data edge of data-signal, that is, the hangover part of data-signal, except the voltage that comprises the generation of current data signal, the data-signal of the previous moment that also superposes, even the hangover of more front data-signal is at the voltage of current time generation.And mainly be the moment of an odd-multiple half period of data-signal to the data of current data signal along what exert an influence, that is, and T/2,3T/2 ..., (2n+1) T/2.Therefore, data-signal can be expressed as on the data edge of current time: 0.5-(β 1-0.5) * T/2-(β 2-0.5) * 3T/2-...-(β n-0.5) * (2n+1) T/2).Wherein, β 1, β 2 ... β n is coefficient, β 1, β 2 ... the value of β n can be calculated acquisition according to Fig. 2, for example: can choose unit impact response at the value of current sampling instant and the ratio of unit impact response peak value, wherein, current sampling instant can be an odd-multiple half period of data-signal.Accordingly, the second adjustment unit 13 can carry out repeatedly phase delay to square-wave signal, an odd-multiple half period of each described local clock of phase delay, obtain a plurality of the second inhibit signals, and described a plurality of the second inhibit signal stacks are obtained the 3rd data-signal.The front half period that superposeed in the 3rd data-signal, even the data-signal of half period more early, therefore, the data of having eliminated in the square-wave signal of decision device 14 outputs are disturbed along hangover.
The DFF that present embodiment provides, adopt two adjustment units respectively the square-wave signal of decision device output to be carried out the phase place adjustment, the data-signal that obtains after adjustment unit adjustment is added to data-signal that feedback equalizer receives as an input of decision device, realizes the voltage magnitude of data-signal is regulated; The data-signal that obtains after another adjustment unit adjustment is as another input of decision device, realizes data to data-signal along adjusting, thereby can take into account the voltage amplitude of adjusting data-signal and data along shake.
Fig. 3 is the structural representation of DFF the second embodiment provided by the invention, and as shown in Figure 3, as a kind of feasible structure, the first adjustment unit 12 can comprise: the first time delay module 21, the first coefficient module 22 and superimposer 23;
The first time delay module 21 is used for square-wave signal is carried out phase delay one time, and an integral multiple cycle that postpones described local clock obtains the 3rd inhibit signal, and the 3rd inhibit signal is inputed to the first coefficient module 22;
The first coefficient module 22 is adjusted for the voltage magnitude of the 3rd inhibit signal that the first time delay module 21 is inputted, and obtains the first inhibit signal, and the first inhibit signal is inputed to superimposer 23;
Superimposer 23 is used for the first inhibit signal and the stack of the first data-signal with 22 inputs of the first coefficient module, the second data-signal that obtains is inputed to the first input end 141 of decision device 14.
Voltage magnitude based on previously described data-signal current time can be expressed as:
α1＊T+α2＊2T+......+αn＊nT。
Can a plurality of the first time delay modules 21 can be set at the first adjustment unit 12, these the first time delay modules 21 can be respectively applied to square-wave signal is carried out phase delay one time, obtain respectively square-wave signal postpone T, 2T ... a plurality of the 3rd inhibit signals that obtain behind the nT.That is, the phase place that each first time delay module 21 postpones can be different, a plurality of the first time delay modules 21 can be respectively applied to square-wave signal postpone T, 2T ... nT.
Accordingly, can a plurality of the first coefficient module 22 can be set at the first adjustment unit 12, each first coefficient module 22 can be corresponding with first a time delay module 21, for example: first coefficient module 22 can be with corresponding for the first time delay module 21 that square-wave signal is postponed T, the voltage magnitude adjustment of the 3rd inhibit signal that obtains after can being used for to postpone to adjust through this first time delay module 21, for example multiply by α 1, obtain the first inhibit signal; Another first coefficient module 22 can be with corresponding for the first time delay module 21 that square-wave signal is postponed 2T, the range-adjusting of the 3rd inhibit signal that obtains after can being used for to postpone to adjust through this first time delay module 21, for example multiply by α 2, obtain the first inhibit signal; ... first coefficient module 22 can be with corresponding for the first time delay module 21 that square-wave signal is postponed nT, the range-adjusting of the 3rd inhibit signal that obtains after can being used for to postpone to adjust through this first time delay module 21, for example multiply by α n, obtain the first inhibit signal.
Superimposer 23 can adopt such as devices such as adders, be used for being connected with the first coefficient module 22, with the first inhibit signal and the stack of the first data-signal of the first coefficient module 22 inputs, the second data-signal that obtains is inputed to the first input end 141 of decision device 14.
In order to simplify the structure of the first adjustment unit 12, as a kind of feasible execution mode, as shown in Figure 3, the setting of can connecting of many first time delay modules 21 in the first adjustment unit 12, the input of each the first coefficient module 22 can be connected with the output of first a time delay module 21, and the output of each the first coefficient module 22 is connected with the input of superimposer 23.Implement to equate the time of delay of 21 pairs of square-wave signals of each the first time delay module, for example: all can postpone one-period T under the scene at this.
Optionally, the number of the first time delay module 21 between adjacent the first coefficient module 22 equates, as shown in Figure 3, a first time delay module 21 all can be set between adjacent the first coefficient module 22, thereby the first adjustment unit 12 can all be added to the data-signal in each front integral multiple cycle of current time data-signal on the current time data-signal, be implemented in the voltage magnitude of data-signal in each front integral multiple cycle of eliminating the current time data-signal to the impact of current data signal voltage amplitude.
Fig. 4 is the structural representation of DFF the 3rd embodiment provided by the invention, and as shown in Figure 4, as a kind of feasible structure, the second adjustment unit 13 can comprise: the second time delay module 31 and the second coefficient module 32;
The second time delay module 31 is used for square-wave signal is carried out phase delay one time, and an odd-multiple half period that postpones described local clock obtains the 4th inhibit signal, and the 4th inhibit signal is inputed to the second coefficient module 32;
The second coefficient module 32 is adjusted for the voltage magnitude of the 4th inhibit signal that the second time delay module 31 is inputted, and obtains the second inhibit signal, and the second inhibit signal is inputed to the second input 142 of decision device 14.
The second time delay module 31 can be used for square-wave signal is carried out phase delay, can obtain square-wave signal postpone T/2 or 3T/2 ... the 4th inhibit signal that perhaps obtains behind (2n+1) T/2.
Accordingly, the voltage magnitude adjustment of the 4th inhibit signal that the second coefficient module 32 obtains after can being used for postponing to adjust through this second time delay module 31 obtains second inhibit signal.Wherein, the voltage magnitude adjusting range of the second coefficient module 32 can be according to along with the differences of 31 time of delays of the second time delay module and difference.
Optionally, if the second time delay module 31 postpones T/2 with square-wave signal, then the second coefficient module 32 can for example multiply by (β 1-0.5) with passing through the voltage magnitude adjustment of the 4th inhibit signal that obtains after this second time delay module 31 postpones to adjust, and obtains second inhibit signal; Perhaps, if the second time delay module 31 postpones 3T/2 with square-wave signal, then the second coefficient module 32 can for example multiply by (β 2-0.5) with passing through the voltage magnitude adjustment of the 4th inhibit signal that obtains after this second time delay module 31 postpones to adjust, and obtains second inhibit signal; ... perhaps, the second time delay module 31 postpones (2n+1) T/2 with square-wave signal, then the second coefficient module 32 can will be passed through the voltage magnitude adjustment of the 4th inhibit signal that obtains after this second time delay module 31 postpones to adjust, for example multiply by (β n-0.5), obtain second inhibit signal.
In the present embodiment, because second inhibit signal that the second adjustment unit 13 obtains, therefore, this second inhibit signal itself is the 3rd data-signal, and the second delay time signal that the second coefficient module 32 will obtain (i.e. the 3rd data-signal) inputs in the second input 142 of decision device 14.
Fig. 5 is the structural representation of DFF the 4th embodiment provided by the invention, and as shown in Figure 5, as a kind of feasible structure, the second adjustment unit 13 can comprise: the second time delay module 31, the second coefficient module 32 and subtracter 33;
The second time delay module 31 is used for square-wave signal is carried out phase delay one time, and an odd-multiple half period that postpones described local clock obtains the 4th inhibit signal, and the 4th inhibit signal is inputed to the second coefficient module 32;
The second coefficient module 32 is adjusted for the voltage magnitude of the 4th inhibit signal that the second time delay module 31 is inputted, and obtains the second inhibit signal, and the second inhibit signal is inputed to subtracter 33;
Optionally, the setting of can connecting of a plurality of the second time delay modules 31, the input of each the second coefficient module 32 is connected with the output of second a time delay module 31, and the output of each the second coefficient module 32 is connected with the input of subtracter 33.
Data edge based on previously described data-signal current time can be expressed as:
0.5-(β1-0.5)＊T/2-(β2-0.5)＊3T/2-...-(βn-0.5)＊(2n+1)T/2)。
A plurality of the second time delay modules 31 can be respectively applied to square-wave signal is carried out phase delay, obtain respectively square-wave signal postpone T/2,3T/2 ... a plurality of the 4th inhibit signals that (2n+1) obtain behind the T/2.That is, the phase place that each second time delay module 31 postpones can be different, a plurality of the first time delay modules 21 can be respectively applied to square-wave signal postpone T/2,3T/2 ... (2n+1) T/2.
Accordingly, each second coefficient module 32 can be corresponding with second a time delay module 31, for example: second coefficient module 32 can be with corresponding for the second time delay module 31 that square-wave signal is postponed T/2, the voltage magnitude adjustment of the 4th inhibit signal that obtains after can being used for to postpone to adjust through this second time delay module 31, for example multiply by (β 1-0.5), obtain second inhibit signal; Another second coefficient module 32 can be with corresponding for the second time delay module 31 that square-wave signal is postponed 3T/2, the voltage magnitude adjustment of the 4th inhibit signal that obtains after can being used for to postpone to adjust through this second time delay module 31, for example multiply by (β 2-0.5), obtain second inhibit signal; ... second coefficient module 32 can be corresponding with the second time delay module 31 that is used for square-wave signal delay (2n+1) T/2, the voltage magnitude adjustment of the 4th inhibit signal that obtains after can being used for to postpone to adjust through this second time delay module 31, for example multiply by (β n-0.5), obtain second inhibit signal.
In order to simplify the structure of the first adjustment unit 13, as a kind of feasible execution mode, as shown in Figure 5, the setting of can connecting of a plurality of the second time delay modules 31 in the first adjustment unit 13, the input of each the second coefficient module 32 can be connected with the output of second a time delay module 31, and the output of each the second coefficient module 32 is connected with the input of subtracter 33.Implement to equate the time of delay of 31 pairs of square-wave signals of each the second time delay module, for example: all can postpone half period T/2 under the scene at this.
Optionally, the number of the second time delay module 31 between adjacent the second coefficient module 32 equates, as shown in Figure 5, a second time delay module 31 all can be set between adjacent the second coefficient module 32, thereby the second adjustment unit 13 can all be added to the data-signal of each front odd-multiple half period of current time data-signal on the current time data-signal, be implemented in the data edge of data-signal of each front odd-multiple half period of eliminating the current time data-signal to the impact on current data signal data edge.
On the basis of the embodiment of Fig. 3 and DFF shown in Figure 5, structure for the further DFF of simplifying, as shown in Figure 6, optionally, the second time delay of per two series connection in the second adjustment unit 13 is adjusted 31 modules, can be used as first a time delay adjusting module 21 in the first adjustment unit 12.
Among the embodiment shown in Figure 6, the delay time that each second time delay is adjusted 31 modules can be the half period, a plurality of second time delay adjustment 31 of series connection belong to respectively two feedback loops that are made of the first adjustment unit 12 and the second adjustment unit 13, the time delay that belongs to the feedback loop of the first adjustment unit 12 is an integral multiple cycle, and the feedback delay that belongs to the feedback loop of the second adjustment unit 13 is an odd-multiple half period.The signal of first input end 141 inputs of decision device 14 is: the data-signal after the cycle time-delay of current data signal and integral multiple, can express by expression formula α 1*T+ α 2*2T+......+ α n*nT; The signal of the second input 142 inputs of decision device 14 is: the data-signal after the odd-multiple half period time-delay, can pass through expression formula:
0.5-(β 1-0.5) * T/2-(β 2-0.5) * 3T/2-...-(β n-0.5) * (2n+1) T/2) express.
The DFF that present embodiment provides, consisting of a feedback loop by the output of decision device 14 and the first adjustment unit 12 can adjust the voltage magnitude of the square-wave signal of decision device 14 outputs, the feedback loop that is made of the second input 142 of output, the second adjustment unit 13 and the decision device 14 of decision device 14 can to the data of decision device 14 output square-wave signals along adjusting, can realize taking into account voltage magnitude and the data edge of adjusting data-signal.
Fig. 7 is the structural representation of receiver the first embodiment provided by the invention, and as shown in Figure 7, this receiver comprises: optical-electrical converter 41, DFF 42 and clock and data recovery module 43;
This DFF 42 can be the DFF of above embodiment announcement; Can comprise: receiving terminal, the first adjustment unit, the second adjustment unit and decision device; Receiving terminal is used for receiving the first data-signal; The first adjustment unit is used for the square-wave signal of decision device output is carried out the phase place adjustment, and the square-wave signal after the phase place adjustment and the first data-signal is superposeed, and obtains the second data-signal, and the second data-signal is inputed to the first input end of decision device; The second adjustment unit carry out the phase place adjustment for the data edge of the square-wave signal that decision device is exported, and the square-wave signal after will adjusting inputs to the second input of decision device as the 3rd data-signal; Decision device is used for the amplitude of the 3rd data-signal of the second data-signal of first input end input and the input of the second input is compared, the output square-wave signal, and square-wave signal inputed to respectively the first adjustment unit and the second adjustment unit;
The receiver that the embodiment of the invention provides can be the optical network devices such as OLT, ONU or ONT, and the DFF embodiment that the structure of DFF wherein and function thereof can provide with reference to Fig. 1-Fig. 6 of the present invention does not repeat them here.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can be finished by the relevant hardware of program command.Aforesaid program can be stored in the computer read/write memory medium.This program is carried out the step that comprises above-mentioned each embodiment of the method when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (15)
1. a DFF is characterized in that, comprising: receiving terminal, the first adjustment unit, the second adjustment unit and decision device;
Described receiving terminal is used for receiving the first data-signal, with the Frequency Synchronization of local clock and described the first data-signal, so that the cycle of described local clock is consistent with the cycle of described the first data-signal;
Described the first adjustment unit, be used for the square-wave signal of described decision device output is carried out the phase place adjustment, and the square-wave signal after the phase place adjustment and described the first data-signal superposeed, obtain the second data-signal, and described the second data-signal is inputed to the first input end of described decision device;
Described the second adjustment unit adjust for the data edge of the described square-wave signal that described decision device is exported, and the square-wave signal after will adjusting inputs to the second input of described decision device as the 3rd data-signal;
Described decision device, voltage magnitude for described the 3rd data-signal that described the second data-signal and described second input of described first input end input are inputted compares, export described square-wave signal, and described square-wave signal is inputed to respectively described the first adjustment unit and described the second adjustment unit.
2. DFF according to claim 1, it is characterized in that, described the first adjustment unit specifically is used for: described square-wave signal is carried out at least one times phase delay, an integral multiple cycle of each described local clock of phase delay, obtain at least one first inhibit signal, described at least one inhibit signal and the stack of described the first data-signal are obtained described the second data-signal;
Described the second adjustment unit specifically is used for: described square-wave signal is carried out at least one times phase delay, an odd-multiple half period of each described local clock of phase delay, obtain at least one second inhibit signal, if it is a plurality of that the second inhibit signal has, described a plurality of the second inhibit signals are superposeed obtain described the 3rd data-signal, if the second inhibit signal only has one, the second inhibit signal itself is exactly described the 3rd data-signal.
3. DFF according to claim 2 is characterized in that, described the first adjustment unit comprises: the first time delay module, the first coefficient module and superimposer;
Described the first time delay module is used for described square-wave signal is carried out phase delay, and an integral multiple cycle that postpones described local clock obtains the 3rd inhibit signal, and described the 3rd inhibit signal is inputed to described the first coefficient module;
Described the first coefficient module is adjusted for the voltage magnitude of described the 3rd inhibit signal that described the first time delay module is inputted, and obtains described the first inhibit signal, and described the first inhibit signal is inputed to described superimposer;
Described superimposer is used for the first inhibit signal and the stack of described the first data-signal with described the first coefficient module input, described the second data-signal that obtains is inputed to the described first input end of described decision device.
4. DFF according to claim 3, it is characterized in that, described the first coefficient module, be used for the voltage magnitude of described the 3rd inhibit signal be multiply by α n, the value of α n be unit impact response at the value of current sampling instant and the ratio of unit impact response peak value, wherein, n is the numerical value in an integral multiple cycle of described local clock, n is integer, and current sampling instant is the doubly individual cycle of the n of described local clock.
5. according to claim 3 or 4 described DFF, it is characterized in that, a plurality of the first time delay module series connection, the input of each described the first coefficient module is connected with the output of described first a time delay module, and the output of each described the first coefficient module is connected with the input of described superimposer.
6. each described DFF according to claim 3-5, it is characterized in that, each described first time delay module equates that to the delay time of described the first output signal the number of described the first time delay module between adjacent described the first coefficient module equates.
7. each described DFF is characterized in that according to claim 2-6, and described the second adjustment unit comprises: the second time delay module and the second coefficient module;
Described the second time delay module is used for described square-wave signal is carried out time lag of first order, and an odd-multiple half period that postpones described local clock obtains the 4th inhibit signal, and described the 4th inhibit signal is inputed to described the second coefficient module;
Described the second coefficient module is adjusted for the voltage magnitude of described the 4th inhibit signal that described the second time delay module is inputted, and obtains described the second inhibit signal, and described the second inhibit signal is inputed to the second input of described decision device.
8. DFF according to claim 7, it is characterized in that, described the second coefficient module, be used for the voltage magnitude of described the 4th inhibit signal be multiply by (β m-0.5), the value of β m be unit impact response at the value of current sampling instant and the ratio of unit impact response peak value, wherein, m is the numerical value of an odd-multiple half period of described local clock, m is odd number, and current sampling instant is the doubly individual half period of the m of described local clock.
9. each described DFF is characterized in that according to claim 2-6, and described the second adjustment unit comprises the second time delay module, the second coefficient module and subtracter,
Described the second time delay module is used for described square-wave signal is carried out time lag of first order, and an odd-multiple half period that postpones described local clock obtains the 4th inhibit signal, and described the 4th inhibit signal is inputed to described the second coefficient module;
Described the second coefficient module is adjusted for the voltage magnitude of described the 4th inhibit signal that described the second time delay module is inputted, and obtains described the second inhibit signal, and described the second inhibit signal is inputed to described subtracter;
Described subtracter is used for the second inhibit signal of described the second coefficient module input is superposeed, and described the 3rd data-signal that will obtain inputs to the second input of described decision device.
10. DFF according to claim 9, it is characterized in that, described the second coefficient module, be used for the voltage magnitude of described the 4th inhibit signal be multiply by (β m-0.5), the value of β m be unit impact response at the value of current sampling instant and the ratio of unit impact response peak value, wherein, m is the numerical value of an odd-multiple half period of described local clock, m is odd number, and current sampling instant is the doubly individual half period of the m of described local clock.
11. each described DFF according to claim 7-10, it is characterized in that, a plurality of the second time delay module series connection, the input of each described the second coefficient module is connected with the output of described second a time delay module, and the output of each described the second coefficient module is connected with the input of described subtracter.
12. each described DFF according to claim 7-10, it is characterized in that, each described second time delay module equates that to the delay time of described the first output signal the number of described the second time delay module between adjacent described the second coefficient module equates.
13. according to claim 11 or 12 described DFF, it is characterized in that the described second time delay adjusting module of per two series connection in described the second adjustment unit is as one in described the first adjustment unit described the first time delay adjusting module.
14. a receiver is characterized in that, comprising: optical-electrical converter, such as each described DFF and clock and data recovery module among the claim 1-13;
Described photoelectric conversion module, the light signal that is used for receiving is converted to the signal of telecommunication, and the described signal of telecommunication is inputed to described DFF as the first data-signal;
Described clock recovery module is used for receiving the square-wave signal that described judgement equalizer decision device is exported, and local clock and described square-wave signal is carried out synchronously.
15. receiver according to claim 14 is characterized in that, described receiver is Optical Network Terminal OLT, optical network unit ONU or optical network unit ONT.
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| PCT/CN2012/077339 WO2013189073A1 (en) | 2012-06-21 | 2012-06-21 | Decision feedback equalizer and receiver |
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| WO2013189073A1 (en) | 2013-12-27 |
| CN102870386B (en) | 2015-04-15 |
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