WO2013189073A1 - Decision feedback equalizer and receiver - Google Patents

Decision feedback equalizer and receiver Download PDF

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Publication number
WO2013189073A1
WO2013189073A1 PCT/CN2012/077339 CN2012077339W WO2013189073A1 WO 2013189073 A1 WO2013189073 A1 WO 2013189073A1 CN 2012077339 W CN2012077339 W CN 2012077339W WO 2013189073 A1 WO2013189073 A1 WO 2013189073A1
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WIPO (PCT)
Prior art keywords
delay
signal
input
module
data signal
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PCT/CN2012/077339
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French (fr)
Chinese (zh)
Inventor
付生猛
王海莉
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201280000698.6A priority Critical patent/CN102870386B/en
Priority to PCT/CN2012/077339 priority patent/WO2013189073A1/en
Publication of WO2013189073A1 publication Critical patent/WO2013189073A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a decision feedback equalizer and a receiver.
  • ISI Inter Symbol Interference
  • the Inter Symbol Interference (ISI) generated during signal transmission is a key factor that restricts the signal rate. ISI will cause pulse broadening, causing the voltage amplitude of the data signal to be unstable, causing jitter on the data edges of the data signal.
  • BER bit error ratio
  • the receiving end is configured to receive a first data signal, and synchronize a local clock with a frequency of the first data signal, so that a period of the local clock is consistent with a period of the first data signal; a unit, configured to perform phase adjustment on the square wave signal output by the determiner, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and the second data Transmitting a signal to a first input of the decider;
  • an embodiment of the present invention provides a receiver, including: a photoelectric converter, a decision feedback equalizer, and a clock data recovery module;
  • the photoelectric conversion module is configured to convert the received optical signal into an electrical signal, and input the electrical signal as the first data signal to the decision feedback equalizer;
  • the decision feedback equalizer includes: a receiving end, a first adjusting unit, a second adjusting unit, and a determiner; the receiving end is configured to receive the first data signal, and synchronize the local clock with the frequency of the first data signal And causing the period of the local clock to coincide with a period of the first data signal; the first adjusting unit, configured to perform phase adjustment on a square wave signal output by the determiner, and adjust a square wave after phase adjustment And superimposing the signal on the first data signal to obtain a second data signal, and inputting the second data signal to a first input end of the determiner; the second adjusting unit, configured to determine the Adjusting the data edge of the square wave signal output by the device, and inputting the adjusted square wave signal as a third data signal to the second input end of the determiner; the determiner is configured to Comparing the amplitude of the second data signal input by an input terminal and the third data signal input by the second input terminal, outputting the square wave signal, and converting the square wave Number are input to the first adjusting means and
  • the clock recovery module is configured to receive a square wave signal output by the decider of the decision equalizer, and synchronize the local clock with the square wave signal.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a decision feedback equalizer according to the present invention
  • FIG. 2 is a unit impulse response in the case where an ISI exists in a transmission channel in the embodiment shown in FIG. 1.
  • FIG. 3 is a decision feedback equalization provided by the present invention.
  • FIG. 4 is a schematic structural diagram of a third embodiment of a decision feedback equalizer according to the present invention
  • FIG. 5 is a schematic structural diagram of a fourth embodiment of a decision feedback equalizer according to the present invention
  • FIG. 7 is a schematic structural diagram of a first embodiment of a receiver provided by the present invention.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a decision feedback equalizer according to the present invention.
  • the decision feedback equalizer includes: a receiving end 11, a first adjusting unit 12, a second adjusting unit 13, and a decider. 14;
  • the receiving end 11 is configured to receive a first data signal, and synchronize a local clock with a frequency of the first data signal, so that a period of the local clock is consistent with a period of the first data signal;
  • the first adjusting unit 12 is configured to perform phase adjustment on the square wave signal output by the decider 14, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and the second data signal Input to the first input 141 of the decider 14;
  • the second adjusting unit 13 is configured to adjust the data edge of the square wave signal output by the determiner 14, and input the adjusted square wave signal as the third data signal to the second input end 142 of the determiner 14;
  • the decision feedback equalizer provided by the embodiment of the present invention may be set on multiple optical network devices. For example, it can be set in an Optical Line Terminal (OLT), or in an Optical Network Unit (ONU), or in an Optical Network Terminal (ONT).
  • OLT Optical Line Terminal
  • ONU Optical Network Unit
  • ONT Optical Network Terminal
  • the decision feedback equalizer can adjust the voltage amplitude and data edge of the data signal sent by the transmitting end.
  • the decision feedback equalizer provided by the embodiment of the present invention includes two feedback loops, wherein the output of the decider 14 and the first adjusting unit 12 form a feedback loop for outputting a square wave to the output of the decider 14.
  • the voltage amplitude of the signal is adjusted; the output of the decider 14, the second adjusting unit 13 and the second input 142 of the decider 14 form another feedback loop for the square wave signal outputted to the output of the decider 14.
  • the data is adjusted along the edge.
  • the first data signal received by the receiving end is interspersed with the interference signal, so that the data signal is distorted, for example: data signal
  • data signal The period of the data is relatively large, and the tailing time of the unit impulse response of the data signal is long.
  • the square wave signal outputted by the output end of the determiner 14 and the interference of the channel on the voltage amplitude of the square wave signal have been reduced; after the adjustment by the second adjusting unit 13, the decision is made.
  • the square wave signal outputted from the output of the device 14 has a reduced jitter of the data edge of the square wave signal.
  • the arbiter 14 can be implemented by using various existing comparators, or can be implemented by logic circuits composed of logic devices.
  • the determiner 14 compares the voltage amplitudes of the second data signal and the third data signal. In an implementation scenario, the voltage amplitude of the second data signal at the same time is greater than the voltage amplitude of the third data signal, and then the decision is made.
  • the device 14 can output a high level, and if the voltage amplitude of the second data signal is less than the voltage amplitude of the third data signal, the decider 14 can output a low level.
  • the determiner 14 may output a low level if the voltage amplitude of the second data signal is less than the voltage amplitude of the third data signal. The value, then the decider 14 can output a high level.
  • the high and low levels outputted by the decider 14 form a square wave signal, which is input to the first adjusting unit 12 and the second adjusting unit 13, respectively.
  • the second adjusting unit 3 is specifically configured to: perform at least one phase delay on the square wave signal, delay each phase by an odd multiple of a half cycle of the local clock, and obtain a first delay signal each time phase delay, And performing a plurality of phase delays to obtain a plurality of second delay signals, and superimposing the plurality of second delay signals to obtain a third data signal. If the second adjustment unit 3 performs a phase delay for the square wave signal, only one second delay signal is obtained, and then the third data signal is the second delay signal itself.
  • FIG. 2 is the case where the transmission channel between the transmitting end and the receiving end has ISI.
  • the unit impulse response, the solid curve represents the time domain waveform generated by the current time data signal through the transmission channel at the receiving end, and the dashed curve represents the time domain waveform generated by the data signal at the previous moment. It can be seen from Fig. 2 that, for the voltage amplitude of the data signal, in addition to the voltage amplitude generated by the current data signal, the voltage generated at the current time by the data signal at the previous moment or even earlier is superimposed.
  • the data edge of the data signal that is, the trailing portion of the data signal
  • the data signal of the previous moment is superimposed, and even the tail of the previous data signal is at the current moment.
  • the influence on the data edge of the current data signal is mainly the time of an odd multiple half cycle of the data signal, that is, T/2, 3 ⁇ /2 (2 ⁇ +1) ⁇ /2. Therefore, the data edge of the data signal at the current time can be expressed as: 0.5-( ⁇ 1 -0.5)* ⁇ /2-( ⁇ 2-0.5)*3 ⁇ /2- ...-( ⁇ -0.5)*(2 ⁇ +1 ) ⁇ /2).
  • FIG. 3 is a schematic structural diagram of a second embodiment of a decision feedback equalizer according to the present invention.
  • the first adjustment unit 12 may include: a first delay module 21 and a first coefficient. Module 22 and adder 23;
  • the first delay module 21 is configured to perform a phase delay for the square wave signal, delay the integer multiple of the local clock to obtain a third delay signal, and input the third delay signal to the first coefficient module 22;
  • the first coefficient module 22 is configured to adjust a voltage amplitude of the third delay signal input by the first delay module 21 to obtain a first delay signal, and input the first delay signal to the adder 23; the adder 23, The first delay signal input by the first coefficient module 22 is superimposed with the first data signal, and the obtained second data signal is input to the first input terminal 141 of the decider 14.
  • the voltage amplitude based on the current time of the data signal described above can be expressed as:
  • each first delay module 21 may be different, and the plurality of first delay modules 21 may be used to delay the square wave signal by D, 2 ⁇ ⁇ , respectively.
  • first coefficient modules 22 may be disposed in the first adjusting unit 12, each The first coefficient module 22 may correspond to a first delay module 21, for example: a first coefficient module 22 may correspond to the first delay module 21 for delaying the square wave signal T, and may be used to pass The first delay module 21 delays the voltage amplitude adjustment of the third delayed signal obtained after the adjustment, for example, by multiplying ⁇ 1 to obtain a first delayed signal; and the other first coefficient module 22 can be used to delay the square wave signal by 2 ⁇ .
  • a first coefficient module 22 may be associated with the first delay module 21 for delaying the square wave signal by ⁇ , and may be used for delaying the third delay signal obtained after the first delay module 21 is delayed.
  • the amplitude adjustment for example multiplied by an, yields the first delayed signal.
  • the adder 23 may be connected to the first coefficient module 22 by using a device such as an adder, superimposing the first delayed signal input by the first coefficient module 22 with the first data signal, and inputting the obtained second data signal to the decision.
  • a device such as an adder
  • the number of the first delay modules 21 between the adjacent first coefficient modules 22 is equal.
  • a first delay module 21 may be disposed between the adjacent first coefficient modules 22. So that the first adjusting unit 12 can superimpose the data signals of the respective previous integer multiples of the current time data signal on the current time data signal, thereby realizing the data signals of the previous integer multiple times of the current data signal. The effect of the voltage amplitude on the current data signal voltage amplitude.
  • the second adjusting unit 13 may include: a second delay module 31 and a second coefficient. Module 32;
  • the second delay module 31 is configured to perform a phase delay for the square wave signal, delay the odd multiple times of the local clock to obtain a fourth delay signal, and input the fourth delay signal to the second coefficient module 32;
  • the second coefficient module 32 is configured to adjust a voltage amplitude of the fourth delay signal input by the second delay module 31 to obtain a second delay signal, and input the second delay signal to the determiner 14 Two inputs 142.
  • the second delay module 31 can be used for phase delay of the square wave signal, and can obtain a fourth delay signal obtained after the square wave signal delay 172, or 3T/2 or (2n+1)T/2.
  • the second coefficient module 32 can be configured to adjust a voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 to obtain a second delay signal.
  • the magnitude of the voltage amplitude adjustment of the second coefficient module 32 may be different according to the delay time of the second delay module 31.
  • the second coefficient module 32 may adjust the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31. For example, multiplying ( ⁇ 1-0.5) to obtain a second delay signal; or, if the second delay module 31 delays the square wave signal by 3 ⁇ /2, the second coefficient module 32 may pass the second delay module. 31 The voltage amplitude adjustment of the fourth delayed signal obtained after the delay adjustment, for example, multiplied by ( ⁇ 2-0.5), to obtain a second delayed signal; ...
  • the second delay module 31 delays the square wave signal (2 ⁇ + 1) ⁇ /2
  • the second coefficient module 32 may adjust the voltage amplitude of the fourth delayed signal obtained by delay adjustment of the second delay module 31, for example, multiplying ( ⁇ -0.5) to obtain a second Delay signal.
  • the second coefficient module 32 obtains the obtained second delay signal (ie, the first The three data signals are input to the second input 142 of the decider 14.
  • FIG. 5 is a schematic structural diagram of a fourth embodiment of a decision feedback equalizer according to the present invention.
  • the second adjusting unit 13 may include: a second delay module 31 and a second coefficient. Module 32 and subtractor 33;
  • the second delay module 31 is configured to perform a phase delay for the square wave signal, delay the odd multiple times of the local clock to obtain a fourth delay signal, and input the fourth delay signal to the second coefficient module 32;
  • the second coefficient module 32 is configured to adjust a voltage amplitude of the fourth delay signal input by the second delay module 31 to obtain a second delay signal, and input the second delay signal to the subtractor 33; the subtractor 33, The second delay signal input by the second coefficient module 32 is superimposed, and the obtained third data signal is input to the second input terminal 142 of the decider 14.
  • the plurality of second delay modules 31 can be respectively used for phase delay of the square wave signal, and respectively obtain a plurality of fourth delayed signals obtained by delaying the square wave signal by ⁇ /2, 3 ⁇ /2 (2 ⁇ +1) ⁇ /2. . That is, the phase delayed by each second delay module 31 may be different, and the plurality of first delay modules 21 may be respectively used to delay the square wave signal by ⁇ /2, 3 ⁇ /2 (2 ⁇ +1) ⁇ /2.
  • each second coefficient module 32 can correspond to a second delay module 31, for example: a second coefficient module 32 can be associated with the second delay module 31 for delaying the square wave signal by ⁇ /2.
  • the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 can be adjusted, for example, multiplied by ( ⁇ 1-0.5) to obtain a second delay signal; another second coefficient The module 32 can be associated with the second delay module 31 for delaying the square wave signal by 3 ⁇ /2, and can be used to adjust the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31. For example, multiplying by ( ⁇ 2-0.5), a second delay signal is obtained; ...
  • a second coefficient module 32 can be associated with the second delay module 31 for delaying the square wave signal by (2 ⁇ +1) ⁇ /2
  • the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 can be adjusted, for example, multiplied by ( ⁇ -0.5) to obtain a second delayed signal.
  • the subtracter 33 is configured to be connected to the plurality of second coefficient modules 32, superimposing the plurality of second delay signals input by the plurality of second coefficient modules 32, and inputting the third data signal to the second input of the decider 14. End 142.
  • a plurality of second delay modules 31 in the first adjusting unit 13 may be arranged in series, and each second coefficient module 32
  • the input terminal can be connected to the output of a second delay module 31, and the output of each second coefficient module 32 is coupled to the input of the subtractor 33.
  • the delay time of the second wave delay signal of each second delay module 31 may be equal, for example: a half cycle 12 may be delayed.
  • the number of the second delay modules 31 between the adjacent second coefficient modules 32 is equal.
  • a second delay module 31 may be disposed between the adjacent second coefficient modules 32. So that the second adjusting unit 13 can superimpose the data signals of the previous odd-numbered half-cycles of the current time data signal on the current time data signal, thereby realizing the elimination of the current time data signals. The influence of the data edge of the data signal of the previous odd-numbered half-cycle on the data edge of the current data signal.
  • each of the second adjustment units 13 may be used as a first delay adjustment module 21 in the first adjustment unit 12.
  • the delay time of each second delay adjustment 31 module may be a half cycle, and the plurality of second delay adjustments 31 connected in series belong to the first adjustment unit 12 and the second adjustment unit, respectively.
  • the two feedback loops formed by the first feedback unit 12 have a delay of an integer multiple of the period, and the feedback delay of the feedback loop belonging to the second adjustment unit 13 is an odd multiple of a half period.
  • the signal input by the first input terminal 141 of the decider 14 is: the current data signal and the data signal after an integer multiple period delay, which can be expressed by the expression ⁇ 1 * ⁇ + ⁇ 2*2 ⁇ +...
  • the signal input by the second input terminal 142 of the arbiter 14 is: an odd-numbered half-cycle delay data signal, which can be expressed by the expression: 0.5-( ⁇ 1 -0.5)* ⁇ /2-( ⁇ 2- 0.5) *3 ⁇ /2- ...-( ⁇ -0.5)*(2 ⁇ +1)172) to express.
  • FIG. 7 is a schematic structural diagram of a receiver according to a first embodiment of the present invention.
  • the receiver includes: a photoelectric converter 41, a decision feedback equalizer 42 and a clock data recovery module 43; and a photoelectric conversion module 41.
  • a photoelectric converter 41 For converting the received optical signal into an electrical signal, and inputting the electrical signal as a first data signal to the decision feedback equalizer;
  • the clock recovery module 43 is configured to receive a square wave signal output by the decider of the decision equalizer, and synchronize the local clock with the square wave signal. Specifically, the clock recovery module 43 synchronizes the local clock so that the local clock and the received square wave signal have the same phase and frequency, so that the sampling is accurate.
  • the aforementioned program can be stored in a computer readable storage medium.
  • the program when executed, performs the steps including the above-described method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The embodiments of the present invention relate to a decision feedback equalizer and a receiver. The equalizer comprises: a receiving end for receiving a first data signal; a first adjusting unit for performing phase adjustment on a square wave signal outputted by a decider, superposing the square wave signal after phase adjustment and the first data signal to obtain a second data signal, and inputting the second data signal to a first input end of the decider; a second adjusting unit for performing phase adjustment on the data border of the square wave signal outputted by the decider, and then inputting the square wave signal after phase adjustment to a second input end of the decider as a third data signal; a decider for comparing the amplitude of the second data signal inputted to the first input end with the amplitude of the third data signal inputted to the second input end, outputting a square wave signal, and respectively outputting the square wave signal into the first adjusting unit and the second adjusting unit. Adjusting for both voltage amplitude jitter and data border jitter of the adjusted data signal is realized.

Description

判决反馈均衡器和接收机  Decision feedback equalizer and receiver
技术领域 本发明实施例涉及通信技术领域， 特别涉及一种判决反馈均衡器和接收 机。 背景技术 随着数字信号技术向着高速大容量方向发展， 对高速率信号处理技术的 需求越来越迫切。 信号传输过程中产生的码间串扰 （ Inter Symbol Interference, ISI )是制约信号速率提升的关键因素， ISI会导致脉冲展宽， 造成数据信号的电压幅度不稳定， 引起数据信号的数据沿的抖动， 导致信道 的误码率 ( Bit Error Ratio, BER )增大。 The present invention relates to the field of communications technologies, and in particular, to a decision feedback equalizer and a receiver. BACKGROUND OF THE INVENTION With the development of digital signal technology toward high speed and large capacity, the demand for high rate signal processing technology is becoming more and more urgent. The Inter Symbol Interference (ISI) generated during signal transmission is a key factor that restricts the signal rate. ISI will cause pulse broadening, causing the voltage amplitude of the data signal to be unstable, causing jitter on the data edges of the data signal. The bit error ratio (BER) of the channel increases.
现有技术中， 将接收的数据信号进行时延处理后反馈到接收端， 与接收 端接收的数据信号进行叠加， 然而， 这种方法无法兼顾数据信号的电压幅度 和数据沿抖动的调整。 发明内容 本发明实施例提供一种判决反馈均衡器和接收机， 实现兼顾调整数据信 号的电压幅度和数据沿抖动。  In the prior art, the received data signal is subjected to delay processing and then fed back to the receiving end to be superimposed with the data signal received by the receiving end. However, this method cannot balance the voltage amplitude of the data signal and the adjustment of the data edge jitter. SUMMARY OF THE INVENTION Embodiments of the present invention provide a decision feedback equalizer and a receiver, which achieve both voltage amplitude and data edge jitter of adjusting a data signal.
一方面， 本发明实施例提供了一种判决反馈均衡器， 包括： 接收端、 第 一调整单元、 第二调整单元和判决器；  In one aspect, an embodiment of the present invention provides a decision feedback equalizer, including: a receiving end, a first adjusting unit, a second adjusting unit, and a decider;
所述接收端， 用于接收第一数据信号， 将本地时钟与所述第一数据信号 的频率同步， 使得所述本地时钟的周期与所述第一数据信号的周期一致； 所述第一调整单元， 用于对所述判决器输出的方波信号进行相位调整， 并将相位调整后的方波信号与所述第一数据信号进行叠加 , 得到第二数据信 号 , 并将所述第二数据信号输入至所述判决器的第一输入端；  The receiving end is configured to receive a first data signal, and synchronize a local clock with a frequency of the first data signal, so that a period of the local clock is consistent with a period of the first data signal; a unit, configured to perform phase adjustment on the square wave signal output by the determiner, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and the second data Transmitting a signal to a first input of the decider;
所述第二调整单元， 用于对所述判决器输出的所述方波信号的数据沿进 行调整， 并将调整后的方波信号作为第三数据信号输入至所述判决器的第二 输入端； 所述判决器， 用于对所述第一输入端输入的所述第二数据信号和所述第 二输入端输入的所述第三数据信号的幅值进行比较， 输出所述方波信号， 并 将所述方波信号分别输入至所述第一调整单元和所述第二调整单元。 The second adjusting unit is configured to adjust a data edge of the square wave signal output by the decider, and input the adjusted square wave signal as a third data signal to a second input of the determiner end; The determiner is configured to compare the amplitudes of the second data signal input by the first input terminal and the third data signal input by the second input terminal, and output the square wave signal, And inputting the square wave signal to the first adjustment unit and the second adjustment unit, respectively.
另一方面， 本发明实施例提供一种接收机， 包括： 光电转换器、 判决反 馈均衡器和时钟数据恢复模块；  In another aspect, an embodiment of the present invention provides a receiver, including: a photoelectric converter, a decision feedback equalizer, and a clock data recovery module;
所述光电转换模块， 用于将接收的光信号转换为电信号， 并将所述电信 号作为第一数据信号输入至所述判决反馈均衡器；  The photoelectric conversion module is configured to convert the received optical signal into an electrical signal, and input the electrical signal as the first data signal to the decision feedback equalizer;
所述判决反馈均衡器包括： 接收端、 第一调整单元、 第二调整单元和判 决器； 所述接收端， 用于接收第一数据信号， 将本地时钟与所述第一数据信 号的频率同步， 使得所述本地时钟的周期与所述第一数据信号的周期一致； 所述第一调整单元， 用于对所述判决器输出的方波信号进行相位调整， 并将 相位调整后的方波信号与所述第一数据信号进行叠加， 得到第二数据信号， 并将所述第二数据信号输入至所述判决器的第一输入端；所述第二调整单元， 用于对所述判决器输出的所述方波信号的数据沿进行调整， 并将调整后的方 波信号作为第三数据信号输入至所述判决器的第二输入端； 所述判决器， 用 于对所述第一输入端输入的所述第二数据信号和所述第二输入端输入的所述 第三数据信号的幅值进行比较， 输出所述方波信号， 并将所述方波信号分别 输入至所述第一调整单元和所述第二调整单元；  The decision feedback equalizer includes: a receiving end, a first adjusting unit, a second adjusting unit, and a determiner; the receiving end is configured to receive the first data signal, and synchronize the local clock with the frequency of the first data signal And causing the period of the local clock to coincide with a period of the first data signal; the first adjusting unit, configured to perform phase adjustment on a square wave signal output by the determiner, and adjust a square wave after phase adjustment And superimposing the signal on the first data signal to obtain a second data signal, and inputting the second data signal to a first input end of the determiner; the second adjusting unit, configured to determine the Adjusting the data edge of the square wave signal output by the device, and inputting the adjusted square wave signal as a third data signal to the second input end of the determiner; the determiner is configured to Comparing the amplitude of the second data signal input by an input terminal and the third data signal input by the second input terminal, outputting the square wave signal, and converting the square wave Number are input to the first adjusting means and the second adjustment means;
所述时钟恢复模块，用于接收所述判决均衡器的判决器输出的方波信号， 并将本地时钟与所述方波信号进行同步。  The clock recovery module is configured to receive a square wave signal output by the decider of the decision equalizer, and synchronize the local clock with the square wave signal.
本发明实施例提供的判决反馈均衡器和接收机， 采用两个调整单元分别 对判决器输出的方波信号进行调整， 一个调整单元调整后得到的数据信号叠 加到反馈均衡器接收的数据信号作为判决器的一个输入端， 实现对数据信号 的电压幅值调节； 另一个调整单元调整后得到的数据信号作为判决器的另一 个输入端， 实现对数据信号的数据沿的调整， 从而能够兼顾调整数据信号的 电压幅度和数据沿抖动。 附图说明  The decision feedback equalizer and the receiver provided by the embodiment of the present invention use two adjustment units to respectively adjust the square wave signal output by the decider, and the data signal obtained by adjusting one adjustment unit is superimposed on the data signal received by the feedback equalizer as An input terminal of the determiner realizes voltage amplitude adjustment of the data signal; and another data signal obtained by adjusting the adjustment unit serves as another input end of the determiner, thereby realizing adjustment of the data edge of the data signal, thereby enabling adjustment The voltage amplitude and data edge jitter of the data signal. DRAWINGS
施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。 The drawings used in the examples or in the description of the prior art are briefly introduced, obviously, below The drawings in the description are only some of the embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative work.
图 1为本发明提供的判决反馈均衡器第一实施例的结构示意图； 图 2为图 1所示实施例中传输信道存在 ISI情况下的单位冲击响应； 图 3为本发明提供的判决反馈均衡器第二实施例的结构示意图； 图 4为本发明提供的判决反馈均衡器第三实施例的结构示意图； 图 5为本发明提供的判决反馈均衡器第四实施例的结构示意图； 图 6为本发明提供的判决反馈均衡器第五实施例的结构示意图； 图 7为本发明提供的接收机第一实施例的结构示意图。 具体实施方式 下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。  1 is a schematic structural diagram of a first embodiment of a decision feedback equalizer according to the present invention; FIG. 2 is a unit impulse response in the case where an ISI exists in a transmission channel in the embodiment shown in FIG. 1. FIG. 3 is a decision feedback equalization provided by the present invention. FIG. 4 is a schematic structural diagram of a third embodiment of a decision feedback equalizer according to the present invention; FIG. 5 is a schematic structural diagram of a fourth embodiment of a decision feedback equalizer according to the present invention; A schematic diagram of a structure of a fifth embodiment of a decision feedback equalizer provided by the present invention; FIG. 7 is a schematic structural diagram of a first embodiment of a receiver provided by the present invention. The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. example. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
图 1 为本发明提供的判决反馈均衡器第一实施例的结构示意图， 如图 1 所示， 该判决反馈均衡器包括： 接收端 11、 第一调整单元 12、 第二调整单元 13和判决器 14;  FIG. 1 is a schematic structural diagram of a first embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 1, the decision feedback equalizer includes: a receiving end 11, a first adjusting unit 12, a second adjusting unit 13, and a decider. 14;
接收端 11 , 用于接收第一数据信号， 将本地时钟与所述第一数据信号的 频率同步， 使得所述本地时钟的周期与所述第一数据信号的周期一致；  The receiving end 11 is configured to receive a first data signal, and synchronize a local clock with a frequency of the first data signal, so that a period of the local clock is consistent with a period of the first data signal;
第一调整单元 12, 用于对判决器 14输出的方波信号进行相位调整， 并 将相位调整后的方波信号与第一数据信号进行叠加， 得到第二数据信号， 并 将第二数据信号输入至判决器 14的第一输入端 141 ;  The first adjusting unit 12 is configured to perform phase adjustment on the square wave signal output by the decider 14, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and the second data signal Input to the first input 141 of the decider 14;
第二调整单元 13,用于对判决器 14输出的方波信号的数据沿进行调整， 并将调整后的方波信号作为第三数据信号输入至判决器 14 的第二输入端 142;  The second adjusting unit 13 is configured to adjust the data edge of the square wave signal output by the determiner 14, and input the adjusted square wave signal as the third data signal to the second input end 142 of the determiner 14;
判决器 14, 用于对第一输入端 141 输入的第二数据信号和第二输入端 142 输入的第三数据信号的电压幅值进行比较， 输出所述方波信号， 并将所 述方波信号分别输入至第一调整单元 12和第二调整单元 13。  a determiner 14 configured to compare a voltage amplitude of the second data signal input by the first input terminal 141 and the third data signal input by the second input terminal 142, output the square wave signal, and the square wave The signals are input to the first adjustment unit 12 and the second adjustment unit 13, respectively.
本发明实施例提供的判决反馈均衡器， 可以设置在多种光网络设备上， 例如： 可以设置在光网络终端（Optical Line Terminal, OLT ), 也可以设置在 光网络单元（Optical Network Unit, ONU ) 上， 还可以设置在光纤网络设备 ( Optical network terminal, ONT )。 该判决反馈均衡器可以对发送端发送的 数据信号的电压幅值和数据沿 （edge )进行调整。 The decision feedback equalizer provided by the embodiment of the present invention may be set on multiple optical network devices. For example, it can be set in an Optical Line Terminal (OLT), or in an Optical Network Unit (ONU), or in an Optical Network Terminal (ONT). The decision feedback equalizer can adjust the voltage amplitude and data edge of the data signal sent by the transmitting end.
本发明实施例提供的判决反馈均衡器中， 包括两个反馈回路， 其中， 判 决器 14的输出端和第一调整单元 12构成一个反馈回路， 用于对判决器 14 的输出端输出的方波信号的电压幅值进行调整； 判决器 14的输出端、第二调 整单元 13和判决器 14的第二输入端 142构成另一个反馈回路， 用于对判决 器 14的输出端输出的方波信号的数据沿进行调整。  The decision feedback equalizer provided by the embodiment of the present invention includes two feedback loops, wherein the output of the decider 14 and the first adjusting unit 12 form a feedback loop for outputting a square wave to the output of the decider 14. The voltage amplitude of the signal is adjusted; the output of the decider 14, the second adjusting unit 13 and the second input 142 of the decider 14 form another feedback loop for the square wave signal outputted to the output of the decider 14. The data is adjusted along the edge.
由于发送端发送的数据信号通常为方波信号， 而这些数据信号经过传输 链路的传输后， 接收端接收到的第一数据信号中会夹杂着干扰信号， 使得数 据信号失真， 例如： 数据信号的周期比较大， 数据信号的单位冲击响应的拖 尾（tailing ) 时间较长等。 经过第一调整单元 12的调整后， 判决器 14的输 出端输出的方波信号， 信道对所述方波信号的电压幅值的干扰已减小； 经过 第二调整单元 13的调整后， 判决器 14的输出端输出的方波信号， 所述方波 信号的数据沿的抖动已减小。  Since the data signals sent by the transmitting end are usually square wave signals, and the data signals are transmitted through the transmission link, the first data signal received by the receiving end is interspersed with the interference signal, so that the data signal is distorted, for example: data signal The period of the data is relatively large, and the tailing time of the unit impulse response of the data signal is long. After the adjustment by the first adjusting unit 12, the square wave signal outputted by the output end of the determiner 14 and the interference of the channel on the voltage amplitude of the square wave signal have been reduced; after the adjustment by the second adjusting unit 13, the decision is made. The square wave signal outputted from the output of the device 14 has a reduced jitter of the data edge of the square wave signal.
判决器 14可以采用现有的各种比较器来实现， 或者，还可以采用逻辑器 件构成的逻辑电路来实现。判决器 14对第二数据信号和第三数据信号的电压 幅值进行比较， 在一种实施场景下， 同一时刻的第二数据信号的电压幅值大 于第三数据信号的电压幅值， 则判决器 14可以输出高电平，如果第二数据信 号的电压幅值小于第三数据信号的电压幅值， 则判决器 14可以输出低电平。 或者， 同一时刻的第二数据信号的电压幅值大于第三数据信号的电压幅值， 则判决器 14可以输出低电平，如果第二数据信号的电压幅值小于第三数据信 号的电压幅值， 则判决器 14可以输出高电平。 判决器 14输出的高低电平组 成方波信号，该方波信号分别输入至第一调整单元 12和第二调整单元 13中。  The arbiter 14 can be implemented by using various existing comparators, or can be implemented by logic circuits composed of logic devices. The determiner 14 compares the voltage amplitudes of the second data signal and the third data signal. In an implementation scenario, the voltage amplitude of the second data signal at the same time is greater than the voltage amplitude of the third data signal, and then the decision is made. The device 14 can output a high level, and if the voltage amplitude of the second data signal is less than the voltage amplitude of the third data signal, the decider 14 can output a low level. Alternatively, if the voltage amplitude of the second data signal at the same time is greater than the voltage amplitude of the third data signal, the determiner 14 may output a low level if the voltage amplitude of the second data signal is less than the voltage amplitude of the third data signal. The value, then the decider 14 can output a high level. The high and low levels outputted by the decider 14 form a square wave signal, which is input to the first adjusting unit 12 and the second adjusting unit 13, respectively.
可选的， 第一调整单元 12可以具体用于： 对方波信号进行至少一次相位 延迟， 每次相位延迟所述本地时钟的整数倍个周期， 每次相位延迟得到一个 第一延迟信号， 因此， 进行多次相位延迟就得到多个第一延迟信号， 将多个 延迟信号与第一数据信号叠加得到第二数据信号。如果第一调整单元 12对方 波信号进行一次相位延迟， 就只得到一个第一延迟信号， 那么， 第二数据信 号就是第一延迟信号本身。 Optionally, the first adjusting unit 12 may be specifically configured to: perform at least one phase delay on the square wave signal, delay each phase by an integer multiple of the local clock, and obtain a first delay signal each time the phase delay, therefore, A plurality of first delay signals are obtained by performing a plurality of phase delays, and the plurality of delay signals are superimposed with the first data signals to obtain a second data signal. If the first adjustment unit 12 performs a phase delay on the square wave signal, only one first delay signal is obtained, then the second data signal The number is the first delayed signal itself.
可选的， 第二调整单元 3可以具体用于： 对方波信号进行至少一次相位 延迟， 每次相位延迟所述本地时钟的奇数倍个半周期， 每次相位延迟得到一 个第一延迟信号， 因此， 进行多次相位延迟就得到多个第二延迟信号， 将多 个第二延迟信号叠加得到第三数据信号。 如果第二调整单元 3对方波信号进 行一次相位延迟， 就只得到一个第二延迟信号， 那么， 第三数据信号就是第 二延迟信号本身。  Optionally, the second adjusting unit 3 is specifically configured to: perform at least one phase delay on the square wave signal, delay each phase by an odd multiple of a half cycle of the local clock, and obtain a first delay signal each time phase delay, And performing a plurality of phase delays to obtain a plurality of second delay signals, and superimposing the plurality of second delay signals to obtain a third data signal. If the second adjustment unit 3 performs a phase delay for the square wave signal, only one second delay signal is obtained, and then the third data signal is the second delay signal itself.
在发送端和接收端之间的传输信道空闲情况下， 输入方波测试信号， 获 得如图 2所示的单位冲击响应图， 图 2为发送端和接收端之间的传输信道存 在 ISI 情况下的单位冲击响应， 实曲线表示当前时刻的数据信号经过传输信 道在接收端产生的时域波形， 虚曲线表示前一时刻的数据信号在接收端产生 的时域波形。 从图 2可以看出， 对于数据信号的电压幅值而言， 除了当前数 据信号产生的电压幅值外， 还会叠加前一时刻， 甚至更早时刻的数据信号在 当前时刻产生的电压。 并且， 对当前数据信号的电压幅值产生影响的主要是 数据信号的整数倍个周期的时刻， 即， 0、 T、 2Τ ηΤ。 因此， 数据信 号在当前时刻的电压幅值可以表示为： α1*Τ+α2*2Τ+ ... ... +αη*ηΤ。其中， α1、 α2 αη为系数， a1、 a2 an的取值可以根据图 2计算获得， 例如： 可以选取单位冲击响应在当前采样时刻的值与单位冲击响应峰值的比值， 其 中， 当前采样时刻为数据信号的整数倍个周期。 据此， 第一调整单元 12可以 对方波信号进行多次相位延迟，每次相位延迟所述本地时钟的整数倍个周期， 得到多个第一延迟信号， 并将多个第一延迟信号与第一数据信号叠加， 得到 第二数据信号。 该第二数据信号中叠加了前一周期， 甚至更早周期的数据信 号， 因此， 消除了判决器 14输出的方波信号中的电压幅值干扰。  When the transmission channel between the transmitting end and the receiving end is idle, the square wave test signal is input to obtain a unit impulse response diagram as shown in FIG. 2, and FIG. 2 is the case where the transmission channel between the transmitting end and the receiving end has ISI. The unit impulse response, the solid curve represents the time domain waveform generated by the current time data signal through the transmission channel at the receiving end, and the dashed curve represents the time domain waveform generated by the data signal at the previous moment. It can be seen from Fig. 2 that, for the voltage amplitude of the data signal, in addition to the voltage amplitude generated by the current data signal, the voltage generated at the current time by the data signal at the previous moment or even earlier is superimposed. Moreover, the influence on the voltage amplitude of the current data signal is mainly the time of an integer multiple of the period of the data signal, that is, 0, T, 2 Τ η Τ. Therefore, the voltage amplitude of the data signal at the current time can be expressed as: α1*Τ+α2*2Τ+ ... +αη*ηΤ. Where α1 and α2 αη are coefficients, and the values of a1 and a2 an can be calculated according to Fig. 2, for example: The ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response can be selected, wherein the current sampling time is An integer multiple of the data signal. According to this, the first adjusting unit 12 can perform multiple phase delays on the square wave signal, and each phase is delayed by an integer multiple of the local clock to obtain a plurality of first delay signals, and the plurality of first delay signals and the first A data signal is superimposed to obtain a second data signal. The second data signal is superimposed with the data signal of the previous cycle, or even earlier, so that the voltage amplitude interference in the square wave signal output by the decider 14 is eliminated.
类似的， 对于数据信号的数据沿， 即， 数据信号的拖尾部分， 除了包括 当前数据信号产生的电压外， 还叠加前一时刻的数据信号， 甚至更前的数据 信号的拖尾在当前时刻产生的电压。 而对当前数据信号的数据沿产生影响的 主要是数据信号的奇数倍个半周期的时刻， 即， T/2、 3Τ/2 (2η+1 )Τ/2。 因 此 ， 数据 信 号 在 当 前 时 刻 的 数据 沿 可 以 表 示 为 ： 0.5-(β1 -0.5)*Τ/2-(β2-0.5)*3Τ/2- ...-(βη-0.5)*(2η+1 )Τ/2)。其中， β1、 β2 βη为系数， β1、 β2 βη的取值可以根据图 2计算获得， 例如： 可以选 取单位冲击响应在当前采样时刻的值与单位冲击响应峰值的比值， 其中， 当 前采样时刻可以为数据信号的奇数倍个半周期。据此， 第二调整单元 13可以 对方波信号进行多次相位延迟， 每次相位延迟所述本地时钟的奇数倍个半周 期， 得到多个第二延迟信号， 将所述多个第二延迟信号叠加得到第三数据信 号。 该第三数据信号中叠加了前半个周期， 甚至更早的半周期的数据信号， 因此， 消除了判决器 14输出的方波信号中的数据沿拖尾干扰。 Similarly, for the data edge of the data signal, that is, the trailing portion of the data signal, in addition to the voltage generated by the current data signal, the data signal of the previous moment is superimposed, and even the tail of the previous data signal is at the current moment. The voltage produced. The influence on the data edge of the current data signal is mainly the time of an odd multiple half cycle of the data signal, that is, T/2, 3Τ/2 (2η+1)Τ/2. Therefore, the data edge of the data signal at the current time can be expressed as: 0.5-(β1 -0.5)*Τ/2-(β2-0.5)*3Τ/2- ...-(βη-0.5)*(2η+1 ) Τ/2). Where β1, β2 βη are coefficients, and the values of β1 and β2 βη can be calculated according to Fig. 2, for example: The ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response is taken, wherein the current sampling moment may be an odd multiple of a half period of the data signal. According to this, the second adjusting unit 13 can perform multiple phase delays on the square wave signal, and each phase is delayed by an odd multiple of a half cycle of the local clock to obtain a plurality of second delayed signals, and the plurality of second delayed signals are obtained. Superimposed to obtain a third data signal. The data signal of the first half cycle, or even the earlier half cycle, is superimposed on the third data signal, thereby eliminating data edge misinterference in the square wave signal output by the decider 14.
本实施例提供的判决反馈均衡器， 采用两个调整单元分别对判决器输出 的方波信号进行相位调整， 一个调整单元调整后得到的数据信号叠加到反馈 均衡器接收的数据信号作为判决器的一个输入端， 实现对数据信号的电压幅 值调节； 另一个调整单元调整后得到的数据信号作为判决器的另一个输入端， 实现对数据信号的数据沿调节， 从而能够兼顾调整数据信号的电压幅度和数 据沿抖动。  In the decision feedback equalizer provided by the embodiment, two adjustment units respectively perform phase adjustment on the square wave signal output by the determiner, and the data signal obtained by adjusting one adjustment unit is superimposed on the data signal received by the feedback equalizer as a decider. One input terminal realizes voltage amplitude adjustment of the data signal; the other adjusted data unit is used as the other input end of the determiner, thereby realizing adjustment of the data edge of the data signal, thereby being able to adjust the voltage of the data signal Amplitude and data edge jitter.
图 3为本发明提供的判决反馈均衡器第二实施例的结构示意图， 如图 3 所示， 作为一种可行的结构， 第一调整单元 12可以包括： 第一时延模块 21、 第一系数模块 22和叠加器 23;  FIG. 3 is a schematic structural diagram of a second embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 3, the first adjustment unit 12 may include: a first delay module 21 and a first coefficient. Module 22 and adder 23;
第一时延模块 21 , 用于对方波信号进行一次相位延迟， 延迟所述本地时 钟的整数倍个周期得到第三延迟信号， 并将第三延迟信号输入至第一系数模 块 22;  The first delay module 21 is configured to perform a phase delay for the square wave signal, delay the integer multiple of the local clock to obtain a third delay signal, and input the third delay signal to the first coefficient module 22;
第一系数模块 22, 用于对第一时延模块 21输入的第三延迟信号的电压 幅值进行调整， 得到第一延迟信号， 并将第一延迟信号输入至叠加器 23; 叠加器 23, 用于将第一系数模块 22输入的第一延迟信号与第一数据信 号叠加， 将得到的第二数据信号输入至判决器 14的第一输入端 141。  The first coefficient module 22 is configured to adjust a voltage amplitude of the third delay signal input by the first delay module 21 to obtain a first delay signal, and input the first delay signal to the adder 23; the adder 23, The first delay signal input by the first coefficient module 22 is superimposed with the first data signal, and the obtained second data signal is input to the first input terminal 141 of the decider 14.
基于前面描述的数据信号当前时刻的电压幅值可以表示为：  The voltage amplitude based on the current time of the data signal described above can be expressed as:
α1 *Τ+α2*2Τ+…… +αη*ηΤ。  11 *Τ+α2*2Τ+...... +αη*ηΤ.
可以在第一调整单元 12可以设置多个第一时延模块 21 , 这些第一时延 模块 21可以分别用于对方波信号进行一次相位延迟，分别得到方波信号延迟 A plurality of first delay modules 21 may be disposed in the first adjusting unit 12, and the first delay modules 21 may respectively perform a phase delay for the square wave signal to obtain a square wave signal delay respectively.
Τ、 2Τ ηΤ后得到的多个第三延迟信号。 即， 每个第一时延模块 21 延 迟的相位可以不同， 多个第一时延模块 21可以分别用于将方波信号延迟丁、 2Τ ηΤ。 多个, 2Τ ηΤ obtained a plurality of third delayed signals. That is, the phase of the delay of each first delay module 21 may be different, and the plurality of first delay modules 21 may be used to delay the square wave signal by D, 2 Τ η, respectively.
相应的， 可以在第一调整单元 12可以设置多个第一系数模块 22, 每个 第一系数模块 22可以与一个第一时延模块 21相对应， 例如： 一个第一系数 模块 22可以与用于将方波信号延迟 T的第一时延模块 21相对应， 可以用于 将经过该第一时延模块 21延迟调整后得到的第三延迟信号的电压幅值调整， 例如乘以 α1 , 得到第一延迟信号； 另一个第一系数模块 22可以与用于将方 波信号延迟 2Τ的第一时延模块 21相对应， 可以用于将经过该第一时延模块 21 延迟调整后得到的第三延迟信号的幅值调整， 例如乘以 α2, 得到第一延 迟信号； ... ...一个第一系数模块 22可以与用于将方波信号延迟 ηΤ的第一时 延模块 21相对应， 可以用于将经过该第一时延模块 21延迟调整后得到的第 三延迟信号的幅值调整， 例如乘以 an, 得到第一延迟信号。 Correspondingly, a plurality of first coefficient modules 22 may be disposed in the first adjusting unit 12, each The first coefficient module 22 may correspond to a first delay module 21, for example: a first coefficient module 22 may correspond to the first delay module 21 for delaying the square wave signal T, and may be used to pass The first delay module 21 delays the voltage amplitude adjustment of the third delayed signal obtained after the adjustment, for example, by multiplying α1 to obtain a first delayed signal; and the other first coefficient module 22 can be used to delay the square wave signal by 2Τ. Corresponding to the first delay module 21, which can be used to adjust the amplitude of the third delay signal obtained after the delay adjustment of the first delay module 21, for example, by multiplying α2, to obtain a first delay signal; A first coefficient module 22 may be associated with the first delay module 21 for delaying the square wave signal by η , and may be used for delaying the third delay signal obtained after the first delay module 21 is delayed. The amplitude adjustment, for example multiplied by an, yields the first delayed signal.
叠加器 23可以采用例如加法器等器件， 用于与第一系数模块 22连接， 将第一系数模块 22输入的第一延迟信号与第一数据信号叠加，将得到的第二 数据信号输入至判决器 14的第一输入端 141。  The adder 23 may be connected to the first coefficient module 22 by using a device such as an adder, superimposing the first delayed signal input by the first coefficient module 22 with the first data signal, and inputting the obtained second data signal to the decision. The first input 141 of the device 14.
为了简化第一调整单元 12 的结构， 作为一种可行的实施方式， 如图 3 所示， 第一调整单元 12中的多第一时延模块 21可以串联设置， 每个第一系 数模块 22的输入端可以与一个第一时延模块 21的输出端连接， 每个第一系 数模块 22的输出端与叠加器 23的输入端连接。 在该实施场景下， 每个第一 时延模块 21对方波信号的延迟时间可以相等，例如：均可以延迟一个周期 T。  In order to simplify the structure of the first adjusting unit 12, as a possible implementation manner, as shown in FIG. 3, the multiple first delay modules 21 in the first adjusting unit 12 may be arranged in series, each of the first coefficient modules 22 The input can be coupled to the output of a first delay module 21, and the output of each first coefficient module 22 is coupled to the input of the adder 23. In this implementation scenario, the delay time of the first wave delay signal of each first delay module 21 may be equal, for example, one cycle T may be delayed.
可选的， 相邻第一系数模块 22之间的第一时延模块 21的个数相等， 如 图 3所示， 相邻第一系数模块 22之间均可以设置一个第一时延模块 21， 从 而使第一调整单元 12 能够把当前时刻数据信号的各个前整数倍周期的数据 信号都叠加到当前时刻数据信号上， 实现在消除当前时刻数据信号的各个前 整数倍个周期的数据信号的电压幅值对当前数据信号电压幅值的影响。  Optionally, the number of the first delay modules 21 between the adjacent first coefficient modules 22 is equal. As shown in FIG. 3, a first delay module 21 may be disposed between the adjacent first coefficient modules 22. So that the first adjusting unit 12 can superimpose the data signals of the respective previous integer multiples of the current time data signal on the current time data signal, thereby realizing the data signals of the previous integer multiple times of the current data signal. The effect of the voltage amplitude on the current data signal voltage amplitude.
图 4为本发明提供的判决反馈均衡器第三实施例的结构示意图， 如图 4 所示， 作为一种可行的结构， 第二调整单元 13可以包括： 第二时延模块 31 和第二系数模块 32;  4 is a schematic structural diagram of a third embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 4, as a feasible structure, the second adjusting unit 13 may include: a second delay module 31 and a second coefficient. Module 32;
第二时延模块 31 , 用于对方波信号进行一次相位延迟， 延迟所述本地时 钟的奇数倍个半周期得到第四延迟信号， 并将第四延迟信号输入至第二系数 模块 32;  The second delay module 31 is configured to perform a phase delay for the square wave signal, delay the odd multiple times of the local clock to obtain a fourth delay signal, and input the fourth delay signal to the second coefficient module 32;
第二系数模块 32, 用于对第二时延模块 31输入的第四延迟信号的电压 幅值进行调整，得到第二延迟信号， 并将第二延迟信号输入至判决器 14的第 二输入端 142。 The second coefficient module 32 is configured to adjust a voltage amplitude of the fourth delay signal input by the second delay module 31 to obtain a second delay signal, and input the second delay signal to the determiner 14 Two inputs 142.
第二时延模块 31可以用于对方波信号进行相位延迟，可以得到方波信号 延迟 172、 或者 3T/2 或者 (2n+1 )T/2后得到的一个第四延迟信号。  The second delay module 31 can be used for phase delay of the square wave signal, and can obtain a fourth delay signal obtained after the square wave signal delay 172, or 3T/2 or (2n+1)T/2.
相应的， 第二系数模块 32可以用于将经过该第二时延模块 31延迟调整 后得到的第四延迟信号的电压幅值调整， 得到一个第二延迟信号。 其中， 第 二系数模块 32的电压幅值调整幅度可以根据随着第二时延模块 31延迟时间 的不同而不同。  Correspondingly, the second coefficient module 32 can be configured to adjust a voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 to obtain a second delay signal. The magnitude of the voltage amplitude adjustment of the second coefficient module 32 may be different according to the delay time of the second delay module 31.
可选的， 若第二时延模块 31 将方波信号延迟 Τ/2, 则第二系数模块 32 可以将经过该第二时延模块 31 延迟调整后得到的第四延迟信号的电压幅值 调整， 例如乘以（β1-0.5), 得到一个第二延迟信号； 或者， 若第二时延模块 31将方波信号延迟 3Τ/2,则第二系数模块 32可以将经过该第二时延模块 31 延迟调整后得到的第四延迟信号的电压幅值调整， 例如乘以 (β2-0.5), 得到一 个第二延迟信号； ……或者， 第二时延模块 31 将方波信号延迟 (2η+1 )Τ/2, 则第二系数模块 32可以将经过该第二时延模块 31延迟调整后得到的第四延 迟信号的电压幅值调整， 例如乘以 (βη-0.5), 得到一个第二延迟信号。  Optionally, if the second delay module 31 delays the square wave signal by Τ/2, the second coefficient module 32 may adjust the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31. For example, multiplying (β1-0.5) to obtain a second delay signal; or, if the second delay module 31 delays the square wave signal by 3Τ/2, the second coefficient module 32 may pass the second delay module. 31 The voltage amplitude adjustment of the fourth delayed signal obtained after the delay adjustment, for example, multiplied by (β2-0.5), to obtain a second delayed signal; ... or, the second delay module 31 delays the square wave signal (2η+ 1) Τ/2, the second coefficient module 32 may adjust the voltage amplitude of the fourth delayed signal obtained by delay adjustment of the second delay module 31, for example, multiplying (βη-0.5) to obtain a second Delay signal.
本实施例中， 由于第二调整单元 13得到的一个第二延迟信号， 因此， 该 第二延迟信号本身即为第三数据信号，第二系数模块 32将得到的第二时延信 号 （即第三数据信号 )输入至判决器 14的第二输入端 142中。  In this embodiment, due to a second delay signal obtained by the second adjusting unit 13, the second delayed signal itself is the third data signal, and the second coefficient module 32 obtains the obtained second delay signal (ie, the first The three data signals are input to the second input 142 of the decider 14.
图 5为本发明提供的判决反馈均衡器第四实施例的结构示意图， 如图 5 所示， 作为一种可行的结构， 第二调整单元 13可以包括： 第二时延模块 31、 第二系数模块 32和减法器 33;  FIG. 5 is a schematic structural diagram of a fourth embodiment of a decision feedback equalizer according to the present invention. As shown in FIG. 5, as a feasible structure, the second adjusting unit 13 may include: a second delay module 31 and a second coefficient. Module 32 and subtractor 33;
第二时延模块 31 , 用于对方波信号进行一次相位延迟， 延迟所述本地时 钟的奇数倍个半周期得到第四延迟信号， 并将第四延迟信号输入至第二系数 模块 32;  The second delay module 31 is configured to perform a phase delay for the square wave signal, delay the odd multiple times of the local clock to obtain a fourth delay signal, and input the fourth delay signal to the second coefficient module 32;
第二系数模块 32, 用于对第二时延模块 31输入的第四延迟信号的电压 幅值进行调整， 得到第二延迟信号， 并将第二延迟信号输入至减法器 33; 减法器 33, 用于将第二系数模块 32输入的第二延迟信号进行叠加， 将 得到的第三数据信号输入至判决器 14的第二输入端 142。  The second coefficient module 32 is configured to adjust a voltage amplitude of the fourth delay signal input by the second delay module 31 to obtain a second delay signal, and input the second delay signal to the subtractor 33; the subtractor 33, The second delay signal input by the second coefficient module 32 is superimposed, and the obtained third data signal is input to the second input terminal 142 of the decider 14.
可选的， 多个第二时延模块 31可以串联设置， 每个第二系数模块 32的 输入端与一个第二时延模块 31的输出端连接， 每个第二系数模块 32的输出 端与减法器 33的输入端连接。 Optionally, the plurality of second delay modules 31 may be disposed in series, and the input end of each second coefficient module 32 is connected to the output end of a second delay module 31, and the output of each second coefficient module 32 is The terminal is connected to the input of the subtractor 33.
基于前面描述的数据信号当前时刻的数据沿可以表示为：  The data edge based on the current time of the data signal described above can be expressed as:
0.5-(β1 -0.5)*Τ/2-(β2-0.5)*3Τ/2- ... -(βη-0.5)*(2η+1 )Τ/2)。  0.5-(β1 -0.5)*Τ/2-(β2-0.5)*3Τ/2- ... -(βη-0.5)*(2η+1)Τ/2).
多个第二时延模块 31 , 可以分别用于对方波信号进行相位延迟， 分别得 到方波信号延迟 Τ/2、 3Τ/2 (2η+1 )Τ/2后得到的多个第四延迟信号。 即， 每个第二时延模块 31延迟的相位可以不同， 多个第一时延模块 21可以分别 用于将方波信号延迟 Τ/2、 3Τ/2 (2η+1 )Τ/2。  The plurality of second delay modules 31 can be respectively used for phase delay of the square wave signal, and respectively obtain a plurality of fourth delayed signals obtained by delaying the square wave signal by Τ/2, 3Τ/2 (2η+1)Τ/2. . That is, the phase delayed by each second delay module 31 may be different, and the plurality of first delay modules 21 may be respectively used to delay the square wave signal by Τ/2, 3Τ/2 (2η+1) Τ/2.
相应的， 每个第二系数模块 32可以与一个第二时延模块 31相对应， 例 如： 一个第二系数模块 32可以与用于将方波信号延迟 Τ/2的第二时延模块 31相对应， 可以用于将经过该第二时延模块 31延迟调整后得到的第四延迟 信号的电压幅值调整， 例如乘以 (β1-0.5), 得到一个第二延迟信号； 另一个第 二系数模块 32可以与用于将方波信号延迟 3Τ/2的第二时延模块 31相对应， 可以用于将经过该第二时延模块 31 延迟调整后得到的第四延迟信号的电压 幅值调整， 例如乘以 (β2-0.5), 得到一个第二延迟信号； ……一个第二系数模 块 32可以与用于将方波信号延迟 (2η+1 )Τ/2的第二时延模块 31相对应， 可 以用于将经过该第二时延模块 31 延迟调整后得到的第四延迟信号的电压幅 值调整， 例如乘以 (βη-0.5), 得到一个第二延迟信号。  Correspondingly, each second coefficient module 32 can correspond to a second delay module 31, for example: a second coefficient module 32 can be associated with the second delay module 31 for delaying the square wave signal by Τ/2. Correspondingly, the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 can be adjusted, for example, multiplied by (β1-0.5) to obtain a second delay signal; another second coefficient The module 32 can be associated with the second delay module 31 for delaying the square wave signal by 3 Τ/2, and can be used to adjust the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31. For example, multiplying by (β2-0.5), a second delay signal is obtained; ... a second coefficient module 32 can be associated with the second delay module 31 for delaying the square wave signal by (2η+1) Τ/2 Correspondingly, the voltage amplitude of the fourth delay signal obtained by delay adjustment of the second delay module 31 can be adjusted, for example, multiplied by (βη-0.5) to obtain a second delayed signal.
减法器 33, 可以用于与多个第二系数模块 32连接， 将多个第二系数模 块 32输入的多个第二延迟信号叠加， 将得到第三数据信号输入至判决器 14 的第二输入端 142。  The subtracter 33 is configured to be connected to the plurality of second coefficient modules 32, superimposing the plurality of second delay signals input by the plurality of second coefficient modules 32, and inputting the third data signal to the second input of the decider 14. End 142.
为了简化第一调整单元 13 的结构， 作为一种可行的实施方式， 如图 5 所示， 第一调整单元 13中的多个第二时延模块 31可以串联设置， 每个第二 系数模块 32的输入端可以与一个第二时延模块 31的输出端连接， 每个第二 系数模块 32的输出端与减法器 33的输入端连接。 在该实施场景下， 每个第 二时延模块 31对方波信号的延迟时间可以相等， 例如： 均可以延迟半个周期 12。  In order to simplify the structure of the first adjusting unit 13, as a possible implementation manner, as shown in FIG. 5, a plurality of second delay modules 31 in the first adjusting unit 13 may be arranged in series, and each second coefficient module 32 The input terminal can be connected to the output of a second delay module 31, and the output of each second coefficient module 32 is coupled to the input of the subtractor 33. In this implementation scenario, the delay time of the second wave delay signal of each second delay module 31 may be equal, for example: a half cycle 12 may be delayed.
可选的， 相邻第二系数模块 32之间的第二时延模块 31的个数相等， 如 图 5所示， 相邻第二系数模块 32之间均可以设置一个第二时延模块 31 , 从 而使第二调整单元 13 能够把当前时刻数据信号的各个前奇数倍半周期的数 据信号都叠加到当前时刻数据信号上， 实现在消除当前时刻数据信号的各个 前奇数倍个半周期的数据信号的数据沿对当前数据信号数据沿的影响。 Optionally, the number of the second delay modules 31 between the adjacent second coefficient modules 32 is equal. As shown in FIG. 5, a second delay module 31 may be disposed between the adjacent second coefficient modules 32. So that the second adjusting unit 13 can superimpose the data signals of the previous odd-numbered half-cycles of the current time data signal on the current time data signal, thereby realizing the elimination of the current time data signals. The influence of the data edge of the data signal of the previous odd-numbered half-cycle on the data edge of the current data signal.
在图 3和图 5所示的判决反馈均衡器的实施例的基础上， 为了进一步简 化的判决反馈均衡器的结构， 如图 6所示， 可选的， 第二调整单元 13中的每 两个串联的第二时延调整 31模块， 可以作为第一调整单元 12中的一个第一 时延调整模块 21。  On the basis of the embodiment of the decision feedback equalizer shown in FIG. 3 and FIG. 5, in order to further simplify the structure of the decision feedback equalizer, as shown in FIG. 6, optionally, each of the second adjustment units 13 The second delay adjustment 31 module in series may be used as a first delay adjustment module 21 in the first adjustment unit 12.
图 6所示的实施例中，每个第二时延调整 31模块的延时时间可以为半周 期， 串联的多个第二时延调整 31分别属于由第一调整单元 12和第二调整单 元 13构成的两个反馈回路， 属于第一调整单元 12的反馈回路的时延为整数 倍个周期， 属于第二调整单元 13的反馈回路的反馈时延为奇数倍个半周期。 判决器 14的第一输入端 141输入的信号为： 当前数据信号和整数倍个周期 延时后的数据信号， 可以通过表达式 α1 *Τ+α2*2Τ+ ... ... +αη*ηΤ来表达； 判 决器 14的第二输入端 142输入的信号为： 奇数倍个半周期延时后的数据信 号，可以通过表达式： 0.5-(β1 -0.5)*Τ/2-(β2-0.5)*3Τ/2- ...-(βη-0.5)*(2η+1 )172) 来表达。  In the embodiment shown in FIG. 6, the delay time of each second delay adjustment 31 module may be a half cycle, and the plurality of second delay adjustments 31 connected in series belong to the first adjustment unit 12 and the second adjustment unit, respectively. The two feedback loops formed by the first feedback unit 12 have a delay of an integer multiple of the period, and the feedback delay of the feedback loop belonging to the second adjustment unit 13 is an odd multiple of a half period. The signal input by the first input terminal 141 of the decider 14 is: the current data signal and the data signal after an integer multiple period delay, which can be expressed by the expression α1 *Τ+α2*2Τ+... +αη* ηΤ is expressed; the signal input by the second input terminal 142 of the arbiter 14 is: an odd-numbered half-cycle delay data signal, which can be expressed by the expression: 0.5-(β1 -0.5)*Τ/2-(β2- 0.5) *3Τ/2- ...-(βη-0.5)*(2η+1)172) to express.
本实施例提供的判决反馈均衡器，由判决器 14的输出端和第一调整单元 The decision feedback equalizer provided by this embodiment is provided by the output end of the decider 14 and the first adjusting unit
12构成一个反馈回路能够对判决器 14输出的方波信号的电压幅值进行调整， 由判决器 14的输出端、 第二调整单元 13和判决器 14的第二输入端 142构 成的反馈回路能够对判决器 14输出方波信号的数据沿进行调整，能够实现兼 顾调整数据信号的电压幅值和数据沿。 12 constitutes a feedback loop capable of adjusting the voltage amplitude of the square wave signal output by the decider 14, and the feedback loop formed by the output of the determiner 14, the second adjusting unit 13 and the second input 142 of the decider 14 can The data edge of the output square wave signal is adjusted by the decider 14, so that the voltage amplitude and the data edge of the adjustment data signal can be achieved.
图 7为本发明提供的接收机第一实施例的结构示意图， 如图 7所示， 该 接收机包括： 光电转换器 41、 判决反馈均衡器 42和时钟数据恢复模块 43; 光电转换模块 41 , 用于将接收的光信号转换为电信号， 并将电信号作为 第一数据信号输入至判决反馈均衡器；  FIG. 7 is a schematic structural diagram of a receiver according to a first embodiment of the present invention. As shown in FIG. 7, the receiver includes: a photoelectric converter 41, a decision feedback equalizer 42 and a clock data recovery module 43; and a photoelectric conversion module 41. For converting the received optical signal into an electrical signal, and inputting the electrical signal as a first data signal to the decision feedback equalizer;
该判决反馈均衡器 42可以为以上实施例揭示的判决反馈均衡器;可以包 括： 接收端、 第一调整单元、 第二调整单元和判决器； 接收端， 用于接收第 一数据信号； 第一调整单元， 用于对判决器输出的方波信号进行相位调整， 并将相位调整后的方波信号与第一数据信号进行叠加 , 得到第二数据信号 , 并将第二数据信号输入至判决器的第一输入端； 第二调整单元， 用于对判决 器输出的方波信号的数据沿进行相位调整， 并将调整后的方波信号作为第三 数据信号输入至判决器的第二输入端； 判决器， 用于对第一输入端输入的第 二数据信号和第二输入端输入的第三数据信号的幅值进行比较， 输出方波信 号， 并将方波信号分别输入至第一调整单元和第二调整单元； The decision feedback equalizer 42 may be the decision feedback equalizer disclosed in the above embodiment; and may include: a receiving end, a first adjusting unit, a second adjusting unit, and a decider; and a receiving end, configured to receive the first data signal; The adjusting unit is configured to perform phase adjustment on the square wave signal output by the determiner, and superimpose the phase-adjusted square wave signal and the first data signal to obtain a second data signal, and input the second data signal to the determiner a first input end; a second adjusting unit, configured to perform phase adjustment on a data edge of the square wave signal output by the decider, and input the adjusted square wave signal as a third data signal to the second input end of the determiner a decider for inputting the first input Comparing the amplitudes of the two data signals and the third data signal input by the second input terminal, outputting a square wave signal, and inputting the square wave signals to the first adjusting unit and the second adjusting unit respectively;
时钟恢复模块 43 , 用于接收判决均衡器的判决器输出的方波信号 , 并将 本地时钟与方波信号进行同步。具体的， 时钟恢复模块 43对本地时钟进行同 步处理， 使得本地时钟与接收到的方波信号的相位和频率一致， 以便于采样 准确。  The clock recovery module 43 is configured to receive a square wave signal output by the decider of the decision equalizer, and synchronize the local clock with the square wave signal. Specifically, the clock recovery module 43 synchronizes the local clock so that the local clock and the received square wave signal have the same phase and frequency, so that the sampling is accurate.
本发明实施例提供的接收机，可以是 OLT、 ONU或 ONT等光网络设备， 其中的判决反馈均衡器的结构及其功能可以参考本发明图 1-图 6提供的判决 反馈均衡器实施例， 在此不再赘述。  The receiver provided by the embodiment of the present invention may be an optical network device such as an OLT, an ONU, or an ONT. The structure of the decision feedback equalizer and its function may refer to the decision feedback equalizer embodiment provided in FIG. 1 to FIG. 6 of the present invention. I will not repeat them here.
本领域普通技术人员可以理解： 实现上述各方法实施例的全部或部分步 骤可以通过程序指令相关的硬件来完成。 前述的程序可以存储于计算机可读 取存储介质中。 该程序在执行时， 执行包括上述各方法实施例的步骤； 而前 述的存储介质包括： ROM、 RAM, 磁碟或者光盘等各种可以存储程序代码的 介质。  One of ordinary skill in the art will appreciate that all or a portion of the steps to implement the various method embodiments described above can be accomplished by hardware associated with the program instructions. The aforementioned program can be stored in a computer readable storage medium. The program, when executed, performs the steps including the above-described method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.
最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对其 限制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通技术 人员应当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或 者对其中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技 术方案的本质脱离本发明各实施例技术方案的精神和范围。  It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

权 利 要求 Rights request
1、 一种判决反馈均衡器， 其特征在于， 包括： 接收端、 第一调整单元、 第二调整单元和判决器； 1. A decision feedback equalizer, characterized in that it includes: a receiving end, a first adjustment unit, a second adjustment unit and a decider;
所述接收端， 用于接收第一数据信号， 将本地时钟与所述第一数据信号 的频率同步， 使得所述本地时钟的周期与所述第一数据信号的周期一致； 所述第一调整单元， 用于对所述判决器输出的方波信号进行相位调整， 并将相位调整后的方波信号与所述第一数据信号进行叠加 , 得到第二数据信 号 , 并将所述第二数据信号输入至所述判决器的第一输入端； The receiving end is used to receive the first data signal and synchronize the local clock with the frequency of the first data signal so that the period of the local clock is consistent with the period of the first data signal; the first adjustment Unit, configured to perform phase adjustment on the square wave signal output by the determiner, superimpose the phase-adjusted square wave signal with the first data signal, obtain a second data signal, and combine the second data The signal is input to the first input terminal of the decision device;
所述第二调整单元， 用于对所述判决器输出的所述方波信号的数据沿进 行调整， 并将调整后的方波信号作为第三数据信号输入至所述判决器的第二 输入端； The second adjustment unit is used to adjust the data edge of the square wave signal output by the determiner, and input the adjusted square wave signal as a third data signal to the second input of the determiner. end;
所述判决器， 用于对所述第一输入端输入的所述第二数据信号和所述第 二输入端输入的所述第三数据信号的电压幅值进行比较，输出所述方波信号 , 并将所述方波信号分别输入至所述第一调整单元和所述第二调整单元。 The determiner is used to compare the voltage amplitude of the second data signal input to the first input terminal and the voltage amplitude of the third data signal input to the second input terminal, and output the square wave signal , and input the square wave signal to the first adjustment unit and the second adjustment unit respectively.
2、根据权利要求 1所述的判决反馈均衡器， 其特征在于， 所述第一调整 单元具体用于： 对所述方波信号进行至少一次相位延迟， 每次相位延迟所述 本地时钟的整数倍个周期， 得到至少一个第一延迟信号， 将所述至少一个延 迟信号与所述第一数据信号叠加得到所述第二数据信号； 2. The decision feedback equalizer according to claim 1, characterized in that, the first adjustment unit is specifically configured to: perform at least one phase delay on the square wave signal, and each phase delay is an integer of the local clock. times the period, to obtain at least one first delay signal, and superpose the at least one delay signal and the first data signal to obtain the second data signal;
所述第二调整单元具体用于： 对所述方波信号进行至少一次相位延迟， 每次相位延迟所述本地时钟的奇数倍个半周期，得到至少一个第二延迟信号， 如果第二延迟信号有多个， 将所述多个第二延迟信号进行叠加得到所述第三 数据信号， 如果第二延迟信号只有一个， 第二延迟信号本身就是所述第三数 据信号。 The second adjustment unit is specifically configured to: perform at least one phase delay on the square wave signal, delay each phase by an odd multiple of half cycles of the local clock, and obtain at least one second delayed signal. If the second delayed signal There are multiple second delay signals, and the third data signal is obtained by superimposing the plurality of second delay signals. If there is only one second delay signal, the second delay signal itself is the third data signal.
3、根据权利要求 2所述的判决反馈均衡器， 其特征在于， 所述第一调整 单元包括： 第一时延模块、 第一系数模块和叠加器； 3. The decision feedback equalizer according to claim 2, characterized in that the first adjustment unit includes: a first delay module, a first coefficient module and an adder;
所述第一时延模块， 用于对所述方波信号进行相位延迟， 延迟所述本地 时钟的整数倍个周期得到第三延迟信号 , 并将所述第三延迟信号输入至所述 第一系数模块； The first delay module is used to phase-delay the square wave signal, delay an integer multiple of the local clock cycles to obtain a third delay signal, and input the third delay signal to the first delay module. coefficient module;
所述第一系数模块， 用于对所述第一时延模块输入的所述第三延迟信号 的电压幅值进行调整， 得到所述第一延迟信号， 并将所述第一延迟信号输入 至所述叠加器； The first coefficient module is used to adjust the voltage amplitude of the third delay signal input by the first delay module, obtain the first delay signal, and input the first delay signal to the stacker;
所述叠加器， 用于将所述第一系数模块输入的第一延迟信号与所述第一数 据信号叠加，将得到的所述第二数据信号输入至所述判决器的所述第一输入端。 The superpositioner is used to superimpose the first delay signal input by the first coefficient module and the first data signal, and input the obtained second data signal to the first input of the decision device. end.
4、根据权利要求 3所述的判决反馈均衡器， 其特征在于， 所述第一系数 模块， 用于对所述第三延迟信号的电压幅值乘以 an , an 的取值为单位冲击 响应在当前采样时刻的值与单位冲击响应峰值的比值， 其中， n 为所述本地 时钟的整数倍个周期的数值， n 为整数， 当前采样时刻为所述本地时钟的 n 倍个周期。 4. The decision feedback equalizer according to claim 3, characterized in that, the first coefficient module is used to multiply the voltage amplitude of the third delayed signal by an, and the value of an is the unit impulse response. The ratio of the value at the current sampling time to the unit impulse response peak value, where n is a value that is an integer multiple of cycles of the local clock, n is an integer, and the current sampling time is n times a cycle of the local clock.
5、根据权利要求 3或 4所述的判决反馈均衡器， 其特征在于， 多个第一 时延模块串联， 每个所述第一系数模块的输入端与一个所述第一时延模块的 输出端连接， 每个所述第一系数模块的输出端与所述叠加器的输入端连接。 5. The decision feedback equalizer according to claim 3 or 4, characterized in that a plurality of first delay modules are connected in series, and the input end of each first coefficient module is connected to an input end of one of the first delay modules. The output terminal is connected, and the output terminal of each first coefficient module is connected with the input terminal of the adder.
6、 根据权利要求 3-5中任一项所述的判决反馈均衡器， 其特征在于， 每 个所述第一时延模块对所述第一输出信号的延时时间相等， 相邻所述第一系 数模块之间的所述第一时延模块的个数相等。 6. The decision feedback equalizer according to any one of claims 3 to 5, characterized in that the delay time of each first delay module to the first output signal is equal, and the delay time of the adjacent first delay modules is equal to that of the first output signal. The number of first delay modules between the first coefficient modules is equal.
7、 根据权利要求 2-6任一项所述的判决反馈均衡器， 其特征在于， 所述 第二调整单元包括： 第二时延模块和第二系数模块； 7. The decision feedback equalizer according to any one of claims 2 to 6, characterized in that the second adjustment unit includes: a second delay module and a second coefficient module;
所述第二时延模块， 用于对所述方波信号进行一次延迟， 延迟所述本地 时钟的奇数倍个半周期得到第四延迟信号 , 并将所述第四延迟信号输入至所 述第二系数模块； The second delay module is used to delay the square wave signal once, delay an odd multiple of the local clock by half cycles to obtain a fourth delay signal, and input the fourth delay signal to the third delay signal. Two-coefficient module;
所述第二系数模块， 用于对所述第二时延模块输入的所述第四延迟信号 的电压幅值进行调整， 得到所述第二延迟信号， 并将所述第二延迟信号输入 至所述判决器的第二输入端。 The second coefficient module is used to adjust the voltage amplitude of the fourth delay signal input by the second delay module to obtain the second delay signal, and input the second delay signal to The second input terminal of the decision device.
8、根据权利要求 7所述的判决反馈均衡器， 其特征在于， 所述第二系数 模块， 用于对所述第四延迟信号的电压幅值乘以 (βΓΠ-0.5), βΓ Ί的取值为单位 冲击响应在当前采样时刻的值与单位冲击响应峰值的比值， 其中， m为所述 本地时钟的奇数倍个半周期的数值， m为奇数， 当前采样时刻为所述本地时 钟的 m倍个半周期。 8. The decision feedback equalizer according to claim 7, characterized in that the second coefficient module is used to multiply the voltage amplitude of the fourth delayed signal by (βΓΠ-0.5), βΓΊ The value is the ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response, where m is the value of an odd multiple of half cycles of the local clock, m is an odd number, and the current sampling time is m of the local clock. times half cycle.
9、 根据权利要求 2-6中任一项所述的判决反馈均衡器， 其特征在于， 所 述第二调整单元包括第二时延模块、 第二系数模块和减法器， 9. The decision feedback equalizer according to any one of claims 2 to 6, characterized in that the second adjustment unit includes a second delay module, a second coefficient module and a subtractor,
所述第二时延模块， 用于对所述方波信号进行一次延迟， 延迟所述本地 时钟的奇数倍个半周期得到第四延迟信号， 并将所述第四延迟信号输入至所 述第二系数模块； The second delay module is used to delay the square wave signal once, delaying the local Obtain a fourth delay signal at odd multiples of half cycles of the clock, and input the fourth delay signal to the second coefficient module;
所述第二系数模块， 用于对所述第二时延模块输入的所述第四延迟信号 的电压幅值进行调整， 得到所述第二延迟信号， 并将所述第二延迟信号输入 至所述减法器； The second coefficient module is used to adjust the voltage amplitude of the fourth delay signal input by the second delay module to obtain the second delay signal, and input the second delay signal to the subtractor;
所述减法器用于将所述第二系数模块输入的第二延迟信号进行叠加， 并 将得到的所述第三数据信号输入至所述判决器的第二输入端。 The subtractor is used to superpose the second delay signal input by the second coefficient module, and input the obtained third data signal to the second input terminal of the decision device.
10、 根据权利要求 9所述的判决反馈均衡器， 其特征在于， 所述第二系 数模块， 用于对所述第四延迟信号的电压幅值乘以 (βΓΠ-0.5), βΓ Ί的取值为单 位冲击响应在当前采样时刻的值与单位冲击响应峰值的比值， 其中， m为所 述本地时钟的奇数倍个半周期的数值， m为奇数， 当前采样时刻为所述本地 时钟的 m倍个半周期。 10. The decision feedback equalizer according to claim 9, characterized in that the second coefficient module is used to multiply the voltage amplitude of the fourth delayed signal by (βΓΠ-0.5), and the value of βΓΊ is The value is the ratio of the value of the unit impulse response at the current sampling time to the peak value of the unit impulse response, where m is the value of an odd multiple of half cycles of the local clock, m is an odd number, and the current sampling time is m of the local clock. times half cycle.
11、 根据权利要求 7-10中任一项所述的判决反馈均衡器， 其特征在于， 多个第二时延模块串联， 每个所述第二系数模块的输入端与一个所述第二时 延模块的输出端连接， 每个所述第二系数模块的输出端与所述减法器的输入 端连接。 11. The decision feedback equalizer according to any one of claims 7-10, characterized in that a plurality of second delay modules are connected in series, and the input end of each second coefficient module is connected to one of the second delay modules. The output end of the delay module is connected, and the output end of each second coefficient module is connected to the input end of the subtractor.
12、 根据权利要求 7-10中任一项所述的判决反馈均衡器， 其特征在于， 每个所述第二时延模块对所述第一输出信号的延时时间相等， 相邻所述第二 系数模块之间的所述第二时延模块的个数相等。 12. The decision feedback equalizer according to any one of claims 7-10, characterized in that the delay time of each second delay module to the first output signal is equal, and the delay time of the adjacent second delay modules is equal to that of the first output signal. The number of second delay modules between the second coefficient modules is equal.
13、 根据权利要求 11或 12所述的判决反馈均衡器， 其特征在于， 所述 第二调整单元中的每两个串联的所述第二时延调整模块， 作为所述第一调整 单元中的一个所述第一时延调整模块。 13. The decision feedback equalizer according to claim 11 or 12, characterized in that, every two second delay adjustment modules in the second adjustment unit connected in series, as one of the first adjustment units one of the first delay adjustment modules.
14、 一种接收机， 其特征在于， 包括： 光电转换器、 如权利要求 1 -13中 任一项所述的判决反馈均衡器和时钟数据恢复模块； 14. A receiver, characterized in that it includes: a photoelectric converter, a decision feedback equalizer as claimed in any one of claims 1 to 13, and a clock data recovery module;
所述光电转换模块， 用于将接收的光信号转换为电信号， 并将所述电信 号作为第一数据信号输入至所述判决反馈均衡器； The photoelectric conversion module is used to convert the received optical signal into an electrical signal, and input the electrical signal as a first data signal to the decision feedback equalizer;
所述时钟恢复模块，用于接收所述判决均衡器中判决器输出的方波信号， 并将本地时钟与所述方波信号进行同步。 The clock recovery module is used to receive the square wave signal output by the decision unit in the decision equalizer, and synchronize the local clock with the square wave signal.
15、 根据权利要求 14 所述的接收机， 其特征在于， 所述接收机为光网 络终端 OLT、 光网络单元 ONU或光纤网络设备 ONT。 15. The receiver according to claim 14, characterized in that the receiver is an optical network terminal OLT, an optical network unit ONU or an optical fiber network equipment ONT.
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