CN111989771A - 制造玻璃框架扇出型封装的***和方法 - Google Patents

制造玻璃框架扇出型封装的***和方法 Download PDF

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CN111989771A
CN111989771A CN201880089382.6A CN201880089382A CN111989771A CN 111989771 A CN111989771 A CN 111989771A CN 201880089382 A CN201880089382 A CN 201880089382A CN 111989771 A CN111989771 A CN 111989771A
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die
cte
frame member
frame structure
carrier substrate
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沈明皓
杜晓明
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Chengdu Yisiwei System Integrated Circuit Co ltd
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Didro Technology Bvi Co ltd
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Abstract

公开了一种制造半导体器件的方法，该半导体器件包括被支撑框架包围的半导体管芯，该支撑框架用于相比于现有器件而言增强半导体器件。将框架构件与管芯一起粘附至载体基板，其中管芯定位在框架构件中的通孔内。框架构件和管芯被密封在模制化合物内。然后移除载体基板，并且在管芯上形成RDL。然后沿着框架结构的一些部分将所得结构切割成各个半导体器件，留下框架结构的一些部分处于适当的位置并且作为支撑框架包围管芯。

Description

制造玻璃框架扇出型封装的***和方法
相关申请的交叉引用
本申请要求2018年2月19日提交的题为“玻璃框架扇出型封装”的美国临时申请No.62/632,162的优先权，所述临时申请通过引用全部并入本文。
技术领域
本公开涉及半导体封装技术。
背景技术
半导体器件普遍存在于现代电子产品中。半导体器件中的电子部件数量和密度各不相同。离散半导体器件通常包含一种类型的电子部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包含数百至数百万个电子部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池和数字微镜器件(DMD)。
半导体器件执行多种功能，例如信号处理，高速计算，发送和接收电磁信号，控制电子器件，将太阳光转换成电以及为电视显示器创建可视投影。半导体器件应用在娱乐、通信、功率转换、网络、计算机和消费产品领域中。半导体器件还应用于军事应用、航空、汽车、工业控制器和办公设备。
半导体器件利用半导体材料的电气特性。半导体材料的原子结构允许通过施加电场或基极电流或通过掺杂过程来控制其导电性。掺杂将杂质引入半导体材料中，以操控和控制半导体器件的导电性。
半导体器件包含有源电气结构和无源电气结构。有源结构(包括双极型和场效应晶体管)控制电流的流动。通过改变掺杂水平以及施加电场或基极电流，晶体管可以促进或限制电流的流动。无源结构(包括电阻器、电容器和电感器)在执行各种电气功能所需的电压和电流之间建立关系。无源结构和有源结构被电连接以形成电路，所述电路使半导体器件能够执行高速计算和其他有用功能。
半导体器件通常使用两个复杂的制造工艺来制造，即，前端制造和后端制造，每个制造工艺均可能涉及数百个步骤。前端制造涉及在半导体晶圆的表面上形成多个管芯。每个半导体管芯通常是相同的，并且包含通过电连接有源部件和无源部件而形成的电路。后端制造涉及从完成的晶圆中分离出单个半导体管芯，并封装管芯以提供结构支持和环境隔离。
在整个说明书中，术语“管芯”、“半导体芯片”和“半导体管芯”可互换使用。本文中使用的术语“晶圆”包括根据本发明的具有在其上沉积层例如以形成电路结构的暴露表面的任何结构。
半导体制造技术的进步导致较小的微电子部件，并且此类部件内的电路越来越密集。为了减小这种部件的尺寸，用于封装这些部件并与电路板组装的结构必须变得更紧凑。采用这种技术的一种方法涉及使用扇出型晶圆级封装(FOWLP)，这是一种封装工艺，其中半导体管芯的触点通过再分布层(RDL)重新分布在较大的区域上。
例如，图1示出了典型的FOWLP晶圆级封装100的示意性截面图。如图所示，半导体管芯102被密封在模制化合物104中。管芯102可以包括根据已知工艺形成的多个半导体器件结构(未示出)。在模制化合物104和管芯102的表面上方形成RDL 106，并且随后在RDL106上方形成球栅阵列(BGA)球108。RDL 106和BGA 108允许管芯102与具有较宽松的占位区的外部电路之间的电连通。这种再分布通常包括薄膜聚合物(例如BCB，PI或其他有机聚合物)和金属化物(例如Al或Cu)，以将***焊盘重新布线为面积阵列配置。
在晶圆级封装中，晶圆和管芯由于热膨胀系数(CTE)不匹配而容易翘曲。众所周知，晶圆翘曲仍然是令人担忧的问题。由于无法保持管芯和晶圆的耦合，翘曲会阻止管芯-晶圆堆叠体的成功组装。翘曲问题尤其是在大尺寸晶圆中是严重的，并且已经对要求精细间距RDL工艺的晶圆级半导体封装工艺产生了障碍。
本公开提供导致减少的翘曲或其他缺陷的新颖、改进的封装方法。
发明内容
根据本公开的制造半导体器件的方法包括将框架构件粘附至载体基板的支撑表面，其中框架构件包括多个框架结构，所述多个框架结构限定穿过框架构件的多个通孔。然后，在框架构件的相应通孔内将多个管芯粘附至载体基板的支撑表面，使得每个管芯都具有相应的有源表面和至少一个相应的集成电路区域。接下来，将框架构件和所述多个管芯密封在模制化合物内。然后，在管芯上形成再分布层(RDL)，并且将所得结构沿着框架结构的一些部分切成各个半导体器件。所得器件包括被框架结构的一些部分包围的管芯。然后，框架结构用作每个器件中的管芯的支撑框架，从而与没有这种支撑框架的现有器件相比，增强了所得半导体器件。
在一些实施例中，载体基板和/或框架构件的热膨胀系数(CTE)可以与所述多个管芯的CTE基本匹配。
在一个实施例中，一种半导体器件包括：管芯，其具有有源表面和至少一个集成电路区域；邻近管芯的框架结构；密封剂，其至少部分地密封管芯和框架结构；以及在管芯上、框架结构上和密封剂上的再分布层(RDL)，其中RDL电连接到管芯。在一个实施例中，框架结构的热膨胀系数(CTE)与管芯的CTE基本匹配。
在另一个实施例中，半导体器件的管芯是硅。在一些实施例中，框架结构的热膨胀系数(CTE)与硅的CTE基本匹配。在其他实施例中，框架结构是玻璃。在一些示例中，RDL至少包括介电层和在介电层中的金属特征。
在一个实施例中，一种制造半导体器件的方法包括：提供具有框架结构的框架构件，该框架结构限定穿过框架构件的多个通孔，然后将框架构件粘附至载体基板的支撑表面。然后，在框架构件的相应通孔内将多个管芯粘附至载体基板的支撑表面，其中每个管芯都具有相应的有源表面和至少一个相应的集成电路区域。在替代实施例中，上述两个粘附步骤可以相反地执行。
在一个实施例中，制造半导体器件的方法的下一步骤包括将框架构件和所述多个管芯密封在密封剂内，从而得到多管芯密封层，然后从多管芯密封层中移除载体基板。该方法进一步包括在多管芯密封层的管芯上形成再分布层(RDL)，从而得到多管芯面板。在另一个实施例中，可以进一步对多管芯面板进行切割步骤，由此可以沿着所述多个框架结构将多层面板单片化以获得单独的半导体器件。
在一些实施例中，载体基板的热膨胀系数(CTE)可以与所述多个管芯的CTE基本匹配。同样地，框架构件的热膨胀系数(CTE)与所述多个管芯和/或载体基板的CTE基本匹配。
在一些实施例中，所述多个框架结构中的第一框架结构能够沿着载体基板的支撑表面在所述多个管芯中的第一管芯和第二管芯之间延伸。在其他实施例中，对多层面板的切割包括沿着第一框架结构对多层面板进行切割，使得第一框架结构的至少第一部分保持与第一管芯相邻，并且第一框架结构的至少第二部分保持与第二管芯相邻。
在一个实施例中，所述多个管芯的每一个都包括硅。在另一个实施例中，框架构件的热膨胀系数(CTE)与硅的CTE基本匹配。
在一个实施例中，一种制造半导体器件的方法包括：将框架构件粘附至载体基板的支撑表面，其中框架构件限定穿过框架构件的第一通孔和第二通孔，并且其中框架构件包括置于第一通孔和第二通孔之间的框架结构；在框架构件的相应的第一通孔和第二通孔内将第一管芯和第二管芯粘附至载体基板的支撑表面，其中第一管芯和第二管芯中的每一个都具有相应的有源表面和至少一个相应的集成电路区域；将框架构件以及第一管芯和第二管芯密封在密封剂内，从而得到多管芯密封层；从多管芯密封层中移除载体基板；在多管芯密封层的第一管芯和第二管芯上形成再分布层(RDL)，从而得到多管芯面板；以及沿着框架结构对多层面板进行切割，以获得第一半导体器件和第二半导体器件。
在一个实施例中，载体基板的热膨胀系数(CTE)与第一管芯和第二管芯的CTE基本匹配。在另一个实施例中，框架构件的热膨胀系数(CTE)与第一管芯和第二管芯的CTE和/或载体基板的CTE基本匹配。
在一个实施例中，框架结构沿着载体基板的支撑表面在第一管芯和第二管芯之间延伸。在一些实施例中，对多层面板的切割包括沿着框架结构对多层面板进行切割，使得第一框架结构的至少第一部分保持与第一管芯相邻，并且第一框架结构的至少第二部分保持与第二管芯相邻。
在一个实施例中，第一管芯和第二管芯中的每一个都包括硅。在另一个实施例中，框架构件的热膨胀系数(CTE)与硅的CTE基本匹配。
附图说明
图1示出了典型的FOWLP晶圆级封装的示意性截面图。
图2A至图2E示出了根据本公开的实施例的用于制造半导体器件的示例性方法的示意性截面图。
图3A至3B分别示出了根据本公开的实施例的框架构件的平面图和截面图。
图4A至4B分别示出了根据本公开的实施例的框架构件和载体基板的平面图和截面图。
图5是示出根据本公开的制造半导体器件的示例性方法的工艺流程图。
具体实施方式
本公开涉及晶圆级封装工艺。例如，在半导体晶圆封装工艺中，晶圆可以是其上具有数千个芯片的半导体晶圆或器件晶圆。薄晶圆，特别是超薄晶圆(厚度小于60微米或者甚至小于30微米)非常不稳定，并且比传统的厚晶圆更容易受到应力的影响。在加工过程中，薄晶圆和管芯容易破裂和翘曲。因此，临时结合到刚性支撑载体基板上可以减少晶圆损坏的风险。载体基板可以是正方形或矩形的面板，由玻璃、蓝宝石、金属或其他刚性材料制成以增加芯片体积。在一种管芯封装方法中，将管芯暂时地放置在临时的粘合剂涂覆载体基板上，密封在诸如环氧模制化合物之类的密封剂材料内。然后，用期望的半导体封装操作来加工密封的管芯，包括RDL形成和切成各个芯片。
在本发明的以下详细描述中，对附图进行了参照，这些附图构成本发明的一部分，并且在附图中通过说明的方式示出了可以实践本发明的特定实施例。对这些实施例进行了足够详细的描述，以使本领域技术人员能够实施本发明。在不脱离本发明的范围的情况下，可以利用其他实施例并且可以进行结构改变。
因此，以下详细描述不应被理解为限制性的，并且本发明的范围仅由所附权利要求以及这些权利要求所赋予的等同物的全部范围来限定。
现在将参照附图描述本发明的一个或多个实施方式，其中，贯穿全文，相似的附图标记用于指代相似的元件，并且其中所示的结构不是一定按比例绘制。
图2A至图2E示出了示意性截面图，图示了根据本公开的用于制造半导体器件的示例性方法。
如图2A所示，准备载体基板204。载体基板204可以包括可离型的基板材料。粘合剂层205设置在载体基板204的顶表面上。在一个实施例中，载体基板204可以是玻璃基板，但是可以替代地是具有与被加工的管芯206的CTE相匹配的CTE的任何其他材料。例如，载体基板204也可以是陶瓷、蓝宝石或石英。粘合剂层205可以是胶带，或者替代地可以是经由旋涂工艺等施加到载体基板204上的胶水或环氧树脂。
随后，可以通过粘合剂层205将半导体管芯206和框架构件202安装在载体基板204的支撑表面上。组装顺序可以变化；换句话说，框架构件202可以在放置管芯206之前、期间或之后被放置。而且，尽管示出了两个管芯206和通孔，但是替代实施例可以包括任何数量的管芯206和通孔。
例如，图3A和3B分别示出了示例性框架构件202的平面图和截面图，并且图4A和4B分别示出了安装在载体基板204上的示例性框架构件202的平面图和截面图。如图所示，框架构件202限定了多个通孔，这些通孔的尺寸和形状设计成允许各个管芯206定位在其中，如图2A至2E所示。在一些实施例中，框架构件202也被称为增强材料。在其他实施例中，框架构件202可以由玻璃、陶瓷、蓝宝石、石英或CTE至少与载体基板204和/或半导体管芯206的CTE基本匹配的其他合适的材料形成。
在一些实施例中，所述多个通孔的尺寸可以与相应的管芯206相同，或者可以比相应的管芯206的尺寸稍大。此外，虽然框架构件202被示出为在图3A和4A所示的平面图中是圆形的，但框架构件202的替代实施例可以具有任何期望的形状，例如正方形或矩形。同样，尽管载体基板204被示出为圆形，但是它也可以具有任何期望的形状，例如正方形或矩形。可以通过使用任何常规的表面安装技术(但不限于这些技术)将管芯206和框架构件202安装在载体基板204上。
在一些实施例中，载体基板204的厚度可以与相应的管芯206的厚度相同。换言之，玻璃基板204的厚度可以与半导体管芯206的厚度相同。
如图2B所示，在将管芯206和框架构件202安装在载体基板204上之后，施加密封剂，例如模制化合物208。模制化合物208覆盖附接的管芯206和框架构件202。模制化合物208还可以填充管芯206和框架构件202之间可能存在的任何间隙。然后可以对模制化合物208进行固化处理。
根据图示的实施例，模制化合物208可以例如在转移模压机中使用热固性模制化合物形成。可以使用其他分配模制化合物的方式。可以使用在高温下为液体或在环境温度下为液体的环氧树脂、树脂和化合物。模制化合物208可以是电绝缘体，并且可以是导热体。可以添加不同的填料以增强模制化合物208的导热性、刚度或粘附性。
接下来转向图2C至图2E，注意，图示的结构被翻转成使得如图2A至2B所示的顶侧成为图2C至图2E所示的底侧。如图2C所示，在形成模制化合物208之后，移除或剥离载体基板204和粘合剂层205以暴露管芯206和框架构件202。可以通过已知技术进行移除过程。
如图2D所示，随后，可以使用已知的RDL形成技术来制造RDL 210。另外，为了提供RDL 210与其他电路之间的电连接，形成多个凸块214，例如微凸块或铜柱。可选地，可以执行热处理以使凸块214回流。
如图2E所示，可以沿着切口区域执行切割或锯切工艺以将各个管芯206分离成相应的半导体器件200。值得注意的是，在切割工艺之后，各个半导体器件200包括框架结构的邻近管芯206的部分212a和212b。在切割之后保留的框架结构的部分212将优选地围绕管芯206。结果，框架部分212用作增强件，以增强器件200的机械强度。框架部分212的CTE可以与管芯206的CTE密切地匹配，从而显著减小翘曲。应当理解，附图中描绘的截面结构仅用于说明目的。
在一个实施例中，具有如图2E所示的封装结构的各个半导体器件206可以通过上述加工步骤来制造。在该实施例中，半导体器件200包括：具有有源表面和至少一个集成电路区域的管芯206；邻近管芯的框架结构212a、212b；密封剂208，其至少部分地密封管芯和框架结构；以及在管芯上、框架结构上和密封剂上的再分布层(RDL)210，其中RDL电连接到管芯。在一个实施例中，框架结构的热膨胀系数(CTE)与管芯和/或载体基板的CTE基本匹配。
在另一个实施例中，半导体器件200的管芯是硅。在一些实施例中，框架结构的热膨胀系数(CTE)与硅的CTE基本匹配。在其他实施例中，框架结构是玻璃。在一些示例中，RDL至少包括介电层和在介电层中的金属特征。
图5是示出根据本公开的制造半导体器件的示例性方法的工艺流程图。在该实施例中，制造半导体器件的方法起始于步骤510，即，提供具有框架结构的框架构件，该框架结构限定了穿过框架构件的多个通孔。在一个实施例中，下一步骤530涉及将框架构件粘附至载体基板的支撑表面。在另一实施例中，下一步骤520涉及在框架构件的相应通孔内将多个管芯粘附至载体基板的支撑表面，其中每个管芯具有相应的有源表面和至少一个相应的集成电路区域。在替代实施例中，可以以相反的顺序执行步骤520和530，例如先执行步骤520，然后是步骤530。下一步骤530涉及将框架构件和所述多个管芯密封在密封剂内，从而得到多管芯密封层，然后是从多管芯密封层移除载体基板的加工步骤550。该方法的下一步骤560包括在多管芯密封层的管芯上形成再分布层(RDL)，从而得到多管芯面板。在一个实施例中，可以进一步对多管芯面板进行切割步骤570，由此可以沿着多个框架结构将多层面板单片化以获得单独的半导体器件。
在一些实施例中，在以上讨论的方法中，载体基板的热膨胀系数(CTE)可以与所述多个管芯的CTE基本匹配。同样地，框架构件的热膨胀系数(CTE)可以与所述多个管芯和/或载体基板的CTE基本匹配。
例如，封装模制化合物可以具有大于约7ppm/K的CTE，而半导体硅管芯可以具有约3ppm/K的CTE。这种差异可能导致在传统的FOWLP加工过程中引起翘曲，并且还带来后续加工挑战，包括随后通过表面安装技术安装到印刷电路板(PCB)。框架构件如玻璃可以具有约2ppm/K至约10ppm/K范围内的CTE。因此，框架构件可以与硅基板在材料方面匹配，以减少翘曲，提高工艺良率并降低产品成本。
在一些实施例中，所述多个框架结构中的第一框架结构能够沿着载体基板的支撑表面在所述多个管芯中的第一管芯和第二管芯之间延伸。在其他实施例中，对多层面板的切割包括沿着第一框架结构对多层面板进行切割，使得第一框架结构的至少第一部分保持与第一管芯相邻，并且第一框架结构的至少第二部分保持与第二管芯相邻。
在一个实施例中，所述多个管芯中的每一个都包括硅。在另一个实施例中，框架构件的热膨胀系数(CTE)与硅的CTE基本匹配。
]在一个实施例中，一种制造半导体器件的方法包括：将框架构件粘附至载体基板的支撑表面，其中框架构件限定穿过框架构件的第一通孔和第二通孔，并且其中框架构件包括置于第一通孔和第二通孔之间的框架结构；在框架构件的相应的第一通孔和第二通孔内将第一管芯和第二管芯粘附至载体基板的支撑表面，其中第一管芯和第二管芯中的每一个都具有相应的有源表面和至少一个相应的集成电路区域；将框架构件以及第一管芯和第二管芯密封在密封剂内，从而得到多管芯密封层；从多管芯密封层中移除载体基板；在多管芯密封层的第一管芯和第二管芯上形成再分布层(RDL)，从而得到多管芯面板；以及沿着框架结构对多层面板进行切割，以获得第一半导体器件和第二半导体器件。
在一个实施例中，载体基板的热膨胀系数(CTE)与第一管芯和第二管芯的CTE基本匹配。在另一个实施例中，框架构件的热膨胀系数(CTE)与第一管芯和第二管芯的CTE和/或载体基板的CTE基本匹配。
在一个实施例中，框架结构沿着载体基板的支撑表面在第一管芯和第二管芯之间延伸。在一些实施例中，对多层面板的切割包括沿着框架结构对多层面板进行切割，使得第一框架结构的至少第一部分保持与第一管芯相邻，并且第一框架结构的至少第二部分保持与第二管芯相邻。
在一个实施例中，第一管芯和第二管芯中的每一个都包括硅。在另一个实施例中，框架构件的热膨胀系数(CTE)与硅的CTE基本匹配。
在操作中，与传统方法相比，当前公开的实施例能够生产更大的半导体封装尺寸。例如，当前公开的实施例能够完成大于约5×5平方毫米的封装、或大于约6×6平方毫米的封装、或大于约7×7平方毫米的封装、或大于约8×8平方毫米的封装的封装尺寸。在其他实施例中，封装可以是矩形的(例如，大于5×8平方毫米的封装或大于6×8平方毫米的封装)或其他多边形的封装。
本领域技术人员将容易地观察到，在保持本发明的教导的同时，可以对设备和方法进行多种修改和改变。因此，以上公开内容应被解释为仅由所附权利要求书的边界和界限来限定。

Claims (20)

1.一种制造半导体器件的方法，包括：
将框架构件粘附至载体基板的支撑表面，其中所述框架构件包括多个框架结构，所述多个框架结构限定穿过所述框架构件的多个通孔；
在所述框架构件的相应通孔内将多个管芯粘附至所述载体基板的所述支撑表面，其中每个管芯都具有相应的有源表面和至少一个相应的集成电路区域；
将所述框架构件和所述多个管芯密封在密封剂内，从而得到多管芯密封层；
从所述多管芯密封层中移除所述载体基板；
在所述多管芯密封层的管芯上形成再分布层(RDL)，从而得到多管芯面板；以及
沿着所述多个框架结构对所述多层面板进行切割，以获得单独的半导体器件。
2.根据权利要求1所述的方法，其中，所述载体基板的热膨胀系数(CTE)与所述多个管芯的CTE基本匹配。
3.根据权利要求1所述的方法，其中，所述框架构件的热膨胀系数(CTE)与所述多个管芯的CTE基本匹配。
4.根据权利要求1所述的方法，其中，所述多个框架结构中的第一框架结构沿着所述载体基板的所述支撑表面在所述多个管芯中的第一管芯和第二管芯之间延伸。
5.根据权利要求4所述的方法，其中，对所述多层面板的切割包括沿着所述第一框架结构对所述多层面板进行切割，使得所述第一框架结构的至少第一部分保持与所述第一管芯相邻，并且所述第一框架结构的至少第二部分保持与所述第二管芯相邻。
6.根据权利要求1所述的方法，其中，所述多个管芯的每一个都包括硅。
7.根据权利要求6所述的方法，其中，所述框架构件的热膨胀系数(CTE)与硅的CTE基本匹配。
8.一种制造半导体器件的方法，包括：
将框架构件粘附至载体基板的支撑表面，其中所述框架构件限定穿过所述框架构件的第一通孔和第二通孔，并且其中所述框架构件包括置于所述第一通孔和所述第二通孔之间的框架结构；
在所述框架构件的相应的所述第一通孔和所述第二通孔内将第一管芯和第二管芯粘附至所述载体基板的所述支撑表面，其中所述第一管芯和所述第二管芯中的每一个都具有相应的有源表面和至少一个相应的集成电路区域；
将所述框架构件以及所述第一管芯和所述第二管芯密封在密封剂内，从而得到多管芯密封层；
从所述多管芯密封层中移除所述载体基板；
在所述多管芯密封层的所述第一管芯和所述第二管芯上形成再分布层(RDL)，从而得到多管芯面板；以及
沿着所述框架结构对所述多层面板进行切割，以获得第一半导体器件和第二半导体器件。
9.根据权利要求8所述的方法，其中，所述载体基板的热膨胀系数(CTE)与所述第一管芯和所述第二管芯的CTE基本匹配。
10.根据权利要求8所述的方法，其中，所述框架构件的热膨胀系数(CTE)与所述第一管芯和所述第二管芯的CTE基本匹配。
11.根据权利要求8所述的方法，其中，所述框架结构沿着所述载体基板的所述支撑表面在所述第一管芯和所述第二管芯之间延伸。
12.根据权利要求8所述的方法，其中，对所述多层面板的切割包括沿着所述框架结构对所述多层面板进行切割，使得所述第一框架结构的至少第一部分保持与所述第一管芯相邻，并且所述第一框架结构的至少第二部分保持与所述第二管芯相邻。
13.根据权利要求8所述的方法，其中，所述第一管芯和所述第二管芯中的每一个都包括硅。
14.根据权利要求13所述的方法，其中，所述框架构件的热膨胀系数(CTE)与硅的CTE基本匹配。
15.一种半导体器件，包括：
管芯，所述管芯包括有源表面和至少一个集成电路区域；
邻近所述管芯的框架结构；
密封剂，所述密封剂至少部分地密封所述管芯和所述框架结构；以及
在所述管芯上、所述框架结构上和所述密封剂上的再分布层(RDL)，其中所述RDL电连接到所述管芯。
16.根据权利要求15所述的半导体器件，其中，所述框架结构的热膨胀系数(CTE)与所述管芯的CTE基本匹配。
17.根据权利要求15所述的半导体器件，其中，所述管芯包括硅。
18.根据权利要求17所述的半导体器件，其中，所述框架结构的热膨胀系数(CTE)与硅的CTE基本匹配。
19.根据权利要求18所述的半导体器件，其中，所述框架结构包括玻璃。
20.根据权利要求15所述的半导体器件，其中，所述RDL至少包括介电层和在所述介电层中的金属特征。
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