CN102738119A - 用于半导体衬底的贯穿硅通孔及其生产方法 - Google Patents

用于半导体衬底的贯穿硅通孔及其生产方法 Download PDF

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CN102738119A
CN102738119A CN2012101041851A CN201210104185A CN102738119A CN 102738119 A CN102738119 A CN 102738119A CN 2012101041851 A CN2012101041851 A CN 2012101041851A CN 201210104185 A CN201210104185 A CN 201210104185A CN 102738119 A CN102738119 A CN 102738119A
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dielectric liner
opening
etch
rate
semiconductor element
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CN102738119B (zh
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余振华
张正宏
廖鄂斌
余佳霖
王湘仪
张俊华
黄立贤
郭智维
吴仓聚
邱文智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体元件包括具有顶面的半导体衬底。开口从顶面延伸至半导体衬底中。该开口包括内表面。具有第一压缩应力的第一介电衬里设置在开口的内表面上。具有拉伸应力的第二介电衬里设置在第一介电衬里上。具有第二压缩应力的第三介电衬里设置在第二介电衬里上。金属阻挡层设置在第三介电衬里上。导电材料设置在金属阻挡层上并填充开口。本发明还提供了一种用于半导体衬底的贯穿硅通孔及其生产方法。

Description

用于半导体衬底的贯穿硅通孔及其生产方法
技术领域
本公开大体上涉及了一种半导体器件，尤其涉及用于形成贯穿硅通孔的结构和方法。
背景技术
自从集成电路发明后，由于不断改进各种电子元件(即晶体管、二极管、电阻器和电容器等)的集成密度半导体产业经历了持续快速增长。就绝大部分而言，这种集成密度方面的改进是由于最小部件尺寸的不断减小，使得在给定的芯片面积上集成更多元件。
这些集成改进本质上基本属于二维(2D)的，此处集成元件所占的体积基本在半导体晶圆的表面上。虽然在光刻方面的显著改进导致了2D集成电路形成中的显著改进，但是在二维方面能够达到的密度存在物理限制。这些限制之一为需要将元件制作成最小尺寸。另外，将更多器件放在一个芯片上时需要更复杂的设计。
另一个限制来自于随着器件数量的增加器件之间的互连的数量和长度将会显著增加当互连的数量和长度增加时，电路RC延迟和能量消耗都将增加。
在用于解决上述限制的努力中，通常使用三维集成电路(3D IC)和堆叠管芯。因此3D IC和堆叠芯片中使用贯穿硅通孔(TSVs)连接管芯。这种情况下，TSVs经常用于连接管芯上的集成电路和管芯背面的集成电路。另外，TSVs也可用于为通过管芯背面接地的集成电路提供短的接地路径，管芯的背面可能被接地金属薄膜所覆盖。
TSVs的形成需要更多的工艺步骤。因此集成电路的形成变得更加复杂，因而问题也会随之产生。因此，形成TSVs的新方法就是要不断改进TSV的形成工艺。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是根据本发明的实施例制造贯穿硅通孔的方法的流程图。
图2至图9是根据图1在生产的各个阶段形成贯穿硅通孔的横截面视图。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体元件，包括：半导体衬底，所述半导体衬底具有顶面；开口，所述开口从所述顶面延伸至所述半导体衬底中，其中所述开口包括内表面；具有第一压缩应力的第一介电衬里，所述第一介电衬里设置在所述开口的所述内表面上；具有拉伸应力的第二介电衬里，所述第二介电衬里设置在所述第一介电衬里上；具有第二压缩应力的第三介电衬里，所述第三介电衬里设置在所述第二介电衬里上；金属阻挡层，所述金属阻挡层设置在所述第三介电衬里上；以及导电材料，所述导电材料设置在所述金属阻挡层上并填充所述开口。
在该半导体元件中，其中所述第一介电衬里和所述第三介电衬里包括相同的介电材料。
在该半导体元件中，其中所述第一介电衬里和所述第三介电衬里包括不同的介电材料。
在该半导体元件中，其中所述第一压缩应力和所述第二压缩应力相同。
在该半导体元件中，其中所述第一压缩应力和所述第二压缩应力彼此不同。
在该半导体元件中，其中所述第一压缩应力和所述第二压缩应力的至少之一在100MPa至400MPa的范围内。
在该半导体元件中，其中所述拉伸应力在50MPa至300MPa的范围内。
在该半导体元件中，其中所述第一介电衬里在HF溶液中具有第一蚀刻速率，第二介电衬里在HF溶液中具有第二蚀刻速率，且所述第一蚀刻速率小于所述第二蚀刻速率。
在该半导体元件中，其中所述第一介电衬里在HF溶液中具有第一蚀刻速率，第二介电衬里在HF溶液中具有第二蚀刻速率，且所述第一蚀刻速率小于所述第二蚀刻速率，且其中所述第三介电衬里在HF溶液中具有第三蚀刻速率，且所述第三蚀刻速率小于所述第二蚀刻速率。
根据本发明的另一方面，提供了一种半导体元件包括：半导体衬底，所述半导体衬底具有顶面；具有内表面的开口，所述开口从所述顶面延伸至所述半导体衬底中，其中所述开口具有顶部和底部；第一介电衬里，所述第一介电衬里设置在所述开口的所述内表面上，所述第一介电衬里具有在所述顶部上的厚度T1和在所述底部上的厚度T2，其中R1是T1与T2的比值；第二介电衬里，所述第二介电衬里设置在所述第一介电衬里上，所述第二介电衬里具有在所述顶部上的厚度T3和在所述底部上的厚度T4，其中R2是T3与T4的比值，且R1大于R2；第三介电衬里，所述第三介电衬里设置在所述第二介电衬里上，所述第三介电衬里具有在所述顶部上的厚度T5和在所述底部上的厚度T6，其中T5大于T6；金属阻挡层，所述金属阻挡层设置在所述第三介电衬里上；以及导电材料，所述导电材料设置在所述金属阻挡层上并填充所述开口。
在该半导体元件中，其中所述比值R1是约5至约20。
在该半导体元件中，其中所述比值R2是约1至约5。
在该半导体元件中，其中T5与T6的比值R3是约5至约20。
在该半导体元件中，其中所述第一介电衬里在HF溶液中具有第一蚀刻速率，所述第二介电衬里在HF溶液中具有第二蚀刻速率，且所述第一蚀刻速率小于所述第二蚀刻速率。
在该半导体元件中，其中所述第一介电衬里在HF溶液中具有第一蚀刻速率，所述第二介电衬里在HF溶液中具有第二蚀刻速率，且所述第一蚀刻速率小于所述第二蚀刻速率，且其中所述第三介电衬里在HF溶液中具有第三蚀刻速率，且所述第三蚀刻速率小于所述第二蚀刻速率。
在该半导体元件中，其中所述第一介电衬里具有第一压缩应力以及所述第三介电衬里具有第二压缩应力，且所述第一压缩应力和所述第二压缩应力的至少之一在100MPa至400MPa的范围内。
在该半导体元件中，其中所述第二介电衬里具有拉伸应力。
在该半导体元件中，其中所述第二介电衬里具有拉伸应力，且其中所述拉伸应力在50MPa至300MPa的范围内。
根据本发明的又一方面，提供一种用于形成半导体元件的方法，包括：提供具有顶面的半导体衬底；形成具有内表面的开口，所述开口从所述顶面延伸至所述半导体衬底中，其中所述开口具有顶部和底部；通过等离子体增强型化学汽相沉积(PECVD)在所述内表面上沉积第一介电衬里；通过共形沉积在所述第一介电衬里上沉积第二介电衬里；通过PECVD在所述第二介电衬里上沉积第三介电衬里；在所述第三介电衬里上沉积金属阻挡层；以及在三种介电衬里和所述金属阻挡层沉积之后用导电材料填充留下的开口。
在该方法中，其中所述第二介电衬里具有在顶部上的厚度T3和在底部上的厚度T4，且T3与T4的比值R2是约1至约5。
具体实施方式
据了解为了实施本公开的不同部件，以下公开提供了许多不同的实施例或示例。以下描述元件和布置的特定示例以简化本公开。当然这些仅仅是示例并不打算限定。再者，以下描述中第一部件形成在第二部件上方，之上，或上面可包括其中第一部件和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成***到第一部件和第二部件中的实施例，使得第一部件和第二部件不直接接触。为了简明和清楚，可以任意地以不同的尺寸绘制各个部件。
图1根据本公开的实施例示出用于制造带有贯穿硅通孔的半导体元件的方法11的流程图。图2至图9根据一个或多个依照图1的实施例示出制造带有贯穿硅通孔的半导体元件100的过程中各阶段的横截面视图。应该注意到为了简明和清楚，本文仅简要描述某些工艺。因此，应该理解可以在图1的方法11之前，之中，和之后提供其他工艺。
现参考图1，用于制造带有贯穿硅通孔的半导体元件的方法11从操作步骤13开始。在操作步骤13中，提供半导体衬底。在半导体衬底上制造多个管芯。半导体衬底上的管芯通过管芯之间的切割槽分割。本文中的术语“半导体衬底”通常指其上可以或可以不形成各种层和器件结构的半导体块状衬底。在一些实施例中，半导体块状衬底包括硅或化合物半导体，诸如GaAx、InP、Si/Ge或SiC。这些层的实例包括介电层、掺杂层、多晶硅层或导电层等。器件结构的实例包括晶体管、电阻器和/或电容器，其可以或可以不通过互连层互连其他有源电路。
然后，方法11继续进行到操作15其中图案化半导体衬底从而在该半导体衬底上形成开口。
参照图2，，提供了带有半导体衬底101的半导体元件100的一部分的放大视图。该半导体衬底101具有顶面102。形成多个开口103，其通过顶面102延伸至半导体衬底101的预定深度。在这一实例中，出于说明的目的仅示出一个开口103。在至少一个实施例中，开口103包括在约μm至150μm范围内的深度，在约1μm至20μm范围内的宽度。开口103包括部分内表面105，该内表面由侧壁和开口103的底表面106组成。开口103还包括顶部107和底部109。顶部107紧邻开口103的最顶端且也邻近半导体衬底101的顶面102。底部109紧邻开口103的最底部且也邻近开口103的底表面106。
在一个实施例中，开口103可以采用干式蚀刻工艺形成。另外，开口103可以采用激光打孔形成。在一个实施例中，在半导体衬底101上形成图案化的掩模层(未示出)以覆盖未移除的区域和暴露部分半导体衬底101从而实现开口103的形成。掩模层可以是采用工艺诸如化学汽相沉积(CVD)形成的包括氮化硅、氧化物或氮氧化物的硬掩模。一旦形成后，采用合适的光刻和刻蚀工艺图案化掩模层以暴露出半导体衬底101的将要形成开口103的那些部分。然后，采用刻蚀或激光打孔移除暴露的半导体衬底101而形成开口103。在另一个实施例中，图案化的和显影的光阻可以可选地用于保护半导体衬底101的未移除区域而同时将衬底101的将要移除的部分暴露以形成开口103。再参考图1，方法11继续进行到操作17其中在开口的内表面上通过等离子体增强化学汽相沉积(PECVD)沉积第一介电衬里。
图3示出操作17阶段其中提供了半导体元件100的横截面视图。第一介电衬里111形成在开口103的内表面105上。第一介电衬里111在开口103的顶部107上具有T1厚度，在开口103的底部109上具有T2厚度。厚度T1在约
Figure BDA0000151911610000061
至约
Figure BDA0000151911610000062
范围内，厚度T2在约
Figure BDA0000151911610000063
至
Figure BDA0000151911610000064
范围内。第一介电衬里111从顶部107至底部109逐渐变薄。厚度T1和厚度T2的比率R1为约5至约20。第一介电衬里111可以包括氧化硅、氮化硅、氮氧化硅或PSG等。
在一个实施例中，第一介电衬里111通过PECVD形成。在这一实例中，在包括O3和TEOS的等离子环境内氧化硅层形成为第一介电衬里。O3和TEOS的流速分别在约5000标准立方厘米每分钟(sccm)至约10000sccm范围内，和约500毫克每分钟(mgm)至约3000mgm范围内。等离子环境的操作功率采用在13.56MHz下设定为约300W至约500W的高频RF功率，以及在350kHz下设定为约50W至约150W的低频RF功率。等离子环境的操作压力是约2托至约8托。半导体元件100的衬底101的操作温度是约150℃至约450℃。在上述条件下，第一介电衬里111用约100MPa至约400MPa范围内的第一压缩应力形成。第一介电衬里111在以1000∶1的比率稀释的HF溶液中具有约
Figure BDA0000151911610000065
至约
Figure BDA0000151911610000066
的第一蚀刻速率。本公开不限定用于形成第一介电衬里111的上述条件，而且产生上述压缩应力或上述蚀刻速率的不同条件均在本公开的范围内。
PECVD使用射频(RF)功率产生辉光放电以将能量转移至反应气体中，使得开口103的内表面105及半导体衬底101的顶面102上的沉积处于较低的温度。据相信在用于开口103形成的操作15中在PECVD的等离子体中带有高能量的自由基修复受损的内表面105。内表面105上的悬空键和缺陷均被移除。较常规方法，第一介电衬里111和内表面105之间的界面具有较少缺陷。因此，产生出沉积的第一介电衬里111的理想性能诸如良好的附着力、低针孔密度和充足的电性能。
再参考图1，方法11继续进行到操作19其中通过共形沉积在第一介电衬里上沉积第二介电衬里。
图4示出操作19阶段其中第二介电衬里113形成在第一介电衬里111上。第二介电衬里113具有在开口103的顶部107上的厚度T3和在开口103的底部109上的厚度T4。厚度T3在约
Figure BDA0000151911610000071
至约
Figure BDA0000151911610000072
的范围内且厚度T4在约
Figure BDA0000151911610000073
至约的范围内。在一个实施例中，第二介电衬里113可以是完全共形的衬里，据发现第二衬里厚度的共形性中的一些变化具有有益效果。厚度T3与厚度T4的比值R2是约1至约5。在比值R2的范围内，第二介电衬里113仍然保持共形性的有益效果。
在一个实施例中，通过使用基于O3/TEOS的低于大气压的化学汽相沉积工艺的高纵横比工艺(HARP)形成第二介电衬里113。在这个实例中，氧化层形成为第二介电衬里。O3和TEOS的流速分别在约10000标准立方厘米每分钟(sccm)至约20000sccm的范围内，和约500mgm至约3500mgm的范围内。操作压力是约400托至约650托。半导体元件100的操作温度是约200℃至约450℃。在无等离子体的操作温度下加热反应物并沉积在第一介电衬里111上。在上述条件下，第二介电衬里113在约50MPa至约300MPa范围内的拉伸应力下形成。第二介电衬里113在以1000∶1的比率稀释的HF溶液中具有约至
Figure BDA0000151911610000076
的第二蚀刻速率。另外，第二介电衬里113可以使用共形沉积技术形成，诸如原子层沉积(ALD)或旋涂涂覆电介质法(SOD)(例如硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)或全氢-聚硅氮烷(PSZ))。
本公开不限于以上用于形成第二介电衬里113，且产生以上压缩应力或以上蚀刻速率的不同条件均在本公开的范围内。
根据以上描述，比率R1大于比率R2。第二介电衬里113具有比第一介电衬里111更好的共形性。第二介电衬里113缓解衬里111和衬里113的组合层的厚度变化。第一蚀刻速率小于第二蚀刻速率。因此，第一介电衬里111具有比第二介电衬里113低的针孔密度。第一介电衬里111提供保护，防止湿气或污染从半导体衬底101扩散至第二介电衬里113。
再参考图1，方法11继续进行到操作21其中第三介电衬里通过等离子体增强化学气体沉积(PECVD)在第二介电衬里上沉积。
图5示出操作21阶段其中提供了半导体元件100的横截面视图。第三介电衬里115在第二介电衬里113上形成。第三介电衬里115在开口103的顶部107上具有厚度T5，且在开口103的底部109上具有厚度T6。厚度T5在约
Figure BDA0000151911610000081
至约的范围内，厚度T6在约
Figure BDA0000151911610000083
至约的范围内。第三介电衬里115的厚度从顶部107至底部109逐渐变薄。厚度T5与厚度T6的比R3是约5至约20。第三介电衬里115可以包括氧化硅、氮化硅、氮氧化硅或PSG。
在一个实施例中，第三介电衬里115由PECVD形成。在这一实例中，在包括O3和TEOS的等离子环境中氧化硅层形成为第三介电衬里。O3和TEOS的流速分别在约5000标准立方厘米每分钟(sccm)至约10000sccm范围内，以及约500mgm至约3000mgm范围内。等离子环境的操作功率使用在13.56MHz下设定为约300W至约500W的高频RF功率，以及在350kHz下设定为约50W至约150W的低频RF功率。等离子环境的操作压力是约2托至约8托。半导体元件100的操作温度是约150℃至约450℃。在上述操作条件下，第三介电衬里115在第二压缩应力在约100MPa至约400MPa范围内的情况下形成。第三介电衬里115在以1000∶1的比率稀释的HF溶液中具有约
Figure BDA0000151911610000085
至约
Figure BDA0000151911610000086
的第三蚀刻速率。
本公开不限于用于形成第三介电衬里115的以上条件，且产生以上压缩应力或以上蚀刻速率的其他条件均在本公开的范围内。
在一个实施例中，第一介电衬里111和第三介电衬里115包括相同的介电材料。第一介电衬里111的第一压缩应力和第三介电衬里115的第二压缩应力等同。在另一个实施例中，第一介电衬里111和第三介电衬里115包括不同的的介电材料。第一介电衬里111的第一压缩应力和第三介电衬里115的第二压缩应力不同。第一压缩应力和第二压缩应力的至少之一在约100MPa至约400MPa的范围内。
根据以上描述，第三蚀刻速率小于第二蚀刻速率。第三介电衬里115具有比第二介电衬里113低的针孔密度。第三介电衬里115形成在第二介电衬里113和稍后形成的金属阻挡层117之间(如图6所示)。第三介电衬里115提供包括，防止污染从稍后形成的金属阻挡层117和导电材料119扩散至半导体衬底101。提供了半导体元件100的耐用电性能。
再参考图1，方法11继续进行到操作23其中第三介电衬里上沉积金属阻挡层。
图6示出操作23阶段其中提供了半导体元件100的横截面视图。在第三介电衬里115上形成金属阻挡层117。金属阻挡层117可以提供保护，防止金属离子、污染从稍后形成的导电材料119扩散至半导体衬底101。金属阻挡层117包括氮化钽，也可以选择性地使用其他材料，例如钽、钛、氮化钛、这些的组合。金属阻挡层117的形成方法包括ALD、PECVD或物理汽相沉积(PVD)工艺等。
再参考图1，方法11继续进行到操作25其中用导电材料填充在三种介电衬里和金属阻挡层沉积之后留下的开口。
参考图7，用导电材料119填充在三种介电衬里和金属阻挡层117沉积之后留下的开口。导电材料119可以过量填充留下的开口103和金属阻挡层117。导电材料119可以包括铜或铜合金。尽管如此，也可使用其他金属如铝、银、金及其组合。可能的形成方法包括化学电镀，或其他通用沉积方法如溅射、洗印、电镀和化学汽相沉积(CVD)。
再参考图1，方法11继续进行到操作27其中选择性地移除在开口103外部的过量导电材料119、金属阻挡层117和三种介电衬里。
图8示出操作27阶段其中提供了半导体元件100的横截面视图。开口103外部的过量材料通过合适的工艺移除，例如化学机械抛光(CMP)，蚀刻、或抛光和蚀刻的组合。移除工艺优选移除位于金属阻挡层117和三种介电衬里111、113和115上的任何导电材料119，因此过量材料的移除将为进一步的工艺步骤暴露半导体元件101的顶面102。在开口103中填充了导电材料119的情况下形成了贯穿硅通孔102。
在一些实施例中，在操作27之后可选地具有进一步的工艺步骤。在衬底101的顶面102上可以形成金属化层(未示出)，设计金属化层以连接半导体元件100中的器件结构从而形成功能电路，同时也可通过TSV120与衬底101的相对面形成连接。金属化层可以由介电材料和导电材料的交替层形成且可以通过任何合适的工艺(如沉积、双镶嵌)形成。
再参考图1，方法11继续进行到操作29其中在衬底背面进行减薄工艺以暴露TSV。
图9示出操作29步骤其中提供了半导体元件100的横截面视图。移除半导体衬底101的背面的一部分以暴露位于开口103内的导电材料119从而完成TSV120。可以使用研磨工艺例如化学机械抛光(CMP)实施移除，尽管可以选择使用其他合适工艺，如蚀刻。可以继续移除衬底101的背面直到衬底101的厚度在约10μm至约200μm之间。因此，TSV120从衬底101背面暴露出来。贯通硅通孔(TSV)120提供衬底101上形成的半导体元件与其他元件的电连接。
本发明的各种实施例可以用于改进常规的贯穿硅通孔结构。例如，在各种实施例中通过PECVD形成的第一介电衬里111修复开口103的受损的内表面105。第一介电衬里111提供保护，防止污染从衬底101扩散至第二介电衬里113和内层115、117及119。具有共形厚度的第二介电衬里113缓解衬里111、113和115的组合层的厚度变化。第一介电衬里和第三介电衬里的压缩应力与第二介电衬里的拉伸应力结合，调整TSV120中的整体应力。从而显著增加终产品的漏电流、器件性能和产量。
虽然根据本公开的各种实施例描述了带有贯穿硅通孔的半导体元件及其制造方法，但是在不背离本公开精神的情况下可以存在其他选择、替代或修改。
本公开的实施例提供了一种半导体元件。该半导体元件包括具有顶面的半导体衬底。开口从顶面延伸至半导体衬底中。开口包括内表面。具有第一压缩应力的第一介电衬里沉积在开口的内表面上。具有拉伸应力的第二介电衬里沉积在第一介电衬里上。具有第二压缩应力的第三介电衬里沉积在第二介电衬里上。金属阻挡层沉积在第三介电衬里上。导电材料沉积在金属阻挡层上且填充开口。
本公开也提供了半导体元件的另一个实施例。该半导体元件包括具有顶面的半导体衬底。具有内表面的开口从顶面延伸至半导体衬底。开口具有顶部和底部。第一介电衬里设置在开口的内表面上。第一介电衬里在顶部上的厚度为T1，在底部的厚度为T2。R1为T1与T2的比值。第二介电衬里设置在第一介电衬里上。第二介电衬里在顶部的厚度为T3，在底部的厚度为T4。R2为T3与T4的比，且R1大于R2。第三介电衬里设置在第二介电衬里上。第三介电衬里在顶部的厚度为T5，在底部的厚度为T6。T5大于T6。金属阻挡层设置在第三介电衬里上。导电材料设置在金属阻挡层上并填充开口。
本公开也提供了形成半导体元件的方法的另一个实施例。该方法包括提供具有顶面的半导体衬底。形成具有内表面的从顶面延伸至半导体衬底的开口。开口具有顶部和底部。通过等离子体增强化学汽相沉积(PECVD)将第一介电衬里沉积在内表面上。通过共形沉积将第二介电衬里沉积在第一介电衬里上。通过PECVD将第三介电衬里沉积在第二介电衬里上。金属阻挡层沉积在第三介电衬里上。在三种介电衬里和金属阻挡层沉积之后用导电材料填充留下的开口。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种半导体元件包括：
半导体衬底，所述半导体衬底具有顶面；
开口，所述开口从所述顶面延伸至所述半导体衬底中，其中所述开口包括内表面；
具有第一压缩应力的第一介电衬里，所述第一介电衬里设置在所述开口的所述内表面上；
具有拉伸应力的第二介电衬里，所述第二介电衬里设置在所述第一介电衬里上；
具有第二压缩应力的第三介电衬里，所述第三介电衬里设置在所述第二介电衬里上；
金属阻挡层，所述金属阻挡层设置在所述第三介电衬里上；以及导电材料，所述导电材料设置在所述金属阻挡层上并填充所述开口。
2.根据权利要求1所述的半导体元件，其中所述第一压缩应力和所述第二压缩应力的至少之一在100MPa至400MPa的范围内。
3.根据权利要求1所述的半导体元件，其中所述拉伸应力在50MPa至300MPa的范围内。
4.根据权利要求1所述的半导体元件，其中所述第一介电衬里在HF溶液中具有第一蚀刻速率，第二介电衬里在HF溶液中具有第二蚀刻速率，且所述第一蚀刻速率小于所述第二蚀刻速率。
5.根据权利要求1所述的半导体元件，其中所述第二介电衬里在HF溶液中具有第二蚀刻速率，且其中所述第三介电衬里在HF溶液中具有第三蚀刻速率，且所述第三蚀刻速率小于所述第二蚀刻速率。
6.一种半导体元件包括：
半导体衬底，所述半导体衬底具有顶面；
具有内表面的开口，所述开口从所述顶面延伸至所述半导体衬底中，其中所述开口具有顶部和底部；
第一介电衬里，所述第一介电衬里设置在所述开口的所述内表面上，所述第一介电衬里具有在所述顶部上的厚度T1和在所述底部上的厚度T2，其中R1是T1与T2的比值；
第二介电衬里，所述第二介电衬里设置在所述第一介电衬里上，所述第二介电衬里具有在所述顶部上的厚度T3和在所述底部上的厚度T4，其中R2是T3与T4的比值，且R1大于R2；
第三介电衬里，所述第三介电衬里设置在所述第二介电衬里上，所述第三介电衬里具有在所述顶部上的厚度T5和在所述底部上的厚度T6，其中T5大于T6；
金属阻挡层，所述金属阻挡层设置在所述第三介电衬里上；以及
导电材料，所述导电材料设置在所述金属阻挡层上并填充所述开口。
7.根据权利要求6所述的半导体元件，其中所述比值R1是约5至约20。
8.根据权利要求6所述的半导体元件，其中所述比值R2是约1至约5。
9.根据权利要求6所述的半导体元件，其中所述第一介电衬里在HF溶液中具有第一蚀刻速率，所述第二介电衬里在HF溶液中具有第二蚀刻速率，且所述第一蚀刻速率小于所述第二蚀刻速率，且其中所述第三介电衬里在HF溶液中具有第三蚀刻速率，且所述第三蚀刻速率小于所述第二蚀刻速率。
10.根据权利要求6所述的半导体元件，其中所述第一介电衬里具有第一压缩应力以及所述第三介电衬里具有第二压缩应力，且所述第一压缩应力和所述第二压缩应力的至少之一在100MPa至400MPa的范围内，或者其中所述第二介电衬里具有拉伸应力，且其中所述拉伸应力在50MPa至300MPa的范围内。
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