CN102651370B - 一种tft阵列基板、制造方法及显示装置 - Google Patents

一种tft阵列基板、制造方法及显示装置 Download PDF

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CN102651370B
CN102651370B CN201210001279.6A CN201210001279A CN102651370B CN 102651370 B CN102651370 B CN 102651370B CN 201210001279 A CN201210001279 A CN 201210001279A CN 102651370 B CN102651370 B CN 102651370B
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resin bed
passivation layer
array substrate
tft
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CN102651370A (zh
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曹占锋
童晓阳
姚琪
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BOE Technology Group Co Ltd
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Abstract

本发明提供了一种TFT阵列基板、制造方法及显示装置，涉及显示装置制造领域，以解决在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题。TFT阵列基板制造方法包括：在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线；利用刻蚀工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。本发明实施例用于制造TFT-LCD以及OLED显示装置。

Description

一种TFT阵列基板、制造方法及显示装置
技术领域
本发明涉及显示装置制造领域，尤其涉及一种TFT阵列基板、制造方法及显示装置。
背景技术
对于TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器)及OLED(Organic Light-Emitting Diode，有机发光半导体)显示装置而言，TFT阵列基板的质量尤为重要。
在现有的TFT阵列基板制造方法中，需要在已经形成TFT结构的基板上先沉积一层钝化层，通常为了进一步提高产品的开口率，还需要在钝化层表面涂覆一层树脂层，再在TFT的漏电极上方利用构图工艺形成过孔以连接像素电极。由于工艺的原因，如图1所示，在形成过孔之后，由于树脂层12刻蚀的速率比钝化层11的刻蚀速率小的多，因而钝化层11的横向刻蚀距离要比树脂层12的横向刻蚀距离大，使得刻蚀后的树脂层12与钝化层11之间形成内阶梯状的倒钩角(如图1中A区域所示)，这将导致在后续工序中，沉积像素电极层时，会使像素电极断裂。
可见，现有的TFT阵列基板制造方法尚难以解决在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，从而导致像素电极断裂，产品良率的下降。
发明内容
本发明的实施例提供一种TFT阵列基板、制造方法及液晶显示装置，以解决在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，提供一种TFT阵列基板的制造方法，包括：
在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔。
对所述树脂层过孔下方的钝化层进行刻蚀形成贯穿所述树脂层薄膜和所述钝化层薄膜的过孔，以暴露出所述TFT的漏极或引线。
利用刻蚀工艺处理所述过孔，使所述过孔的树脂层侧壁和钝化层侧壁平缓衔接。
另一方面，提供一种利用上述的方法制作的TFT阵列基板，包括：形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板，在所述TFT阵列基板上形成有贯穿所述钝化层薄膜以及树脂层薄膜的过孔。
所述过孔的树脂层侧壁和钝化层侧壁平缓衔接。
另一方面，提供一种显示装置，包括：如上所述的TFT阵列基板。
本发明实施例提供的TFT阵列基板、制造方法及显示装置，一种TFT阵列基板的制造方法包括：在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线；利用刻蚀工艺或灰化工艺处理该过孔，优选的，使用灰化工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。采用这样一种方法，通过刻蚀工艺或灰化工艺处理过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接，从而解决了现有技术在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题，从而大大提高了显示装置的质量。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的过孔结构示意图；
图2为本发明实施例提供的一种TFT阵列基板制造方法流程图；
图3为本发明实施例提供的另一TFT阵列基板制造方法流程图；
图4为本发明实施例提供的又一TFT阵列基板制造方法流程图；
图5为本发明实施例提供的一种TFT阵列基板的过孔结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种TFT阵列基板制造方法，如图2所示，包括：
S201、在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔。
S202、对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线。
S203、利用刻蚀工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。
本发明实施例提供的TFT阵列基板制造方法。包括：在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线；利用刻蚀工艺处理该过孔，优选的，使用灰化工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。采用这样一种方法，通过刻蚀工艺处理过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接，从而解决了现有技术在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题，从而大大提高了显示装置的质量。
本发明另一实施例提供了一种TFT阵列基板制造方法，如图3所示，包括：
S301、在透明基板上依次形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层；其中，栅金属层包括：栅线以及TFT的栅电极，源漏金属层包括：数据线、以及TFT的源电极和漏电极。
具体的，在透明基板上依次形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层的过程可以参照现有技术，利用构图工艺，通过曝光、显影、刻蚀工序依次形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层。
S302、在源漏金属层上制作钝化层薄膜以及树脂层薄膜。
具体的，可以采用化学气相沉积法在已形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层的透明基板上沉积形成钝化层薄膜，其材料通常是氮化硅、氧化硅或透明的有机树脂材料。在已沉积钝化层薄膜的透明基板上涂覆树脂形成树脂层薄膜。其中，树脂层薄膜可以为感光树脂，或不感光的一般透明树脂材料，优选的使用感光树脂材料。
S303、当树脂层采用感光树脂材料时，利用构图工艺对树脂层曝光显影形成树脂层过孔。
S304、利用灰化工艺处理该树脂层过孔处的残留树脂。
具体的，可以在含氟气体和氧气的环境中利用灰化工艺将树脂层过孔中的残留树脂去除，其中，含氟气体的流量可以在20-100sccm之间，氧气的流量可以在500-1000sccm之间，氧气和含氟气体的质量比可以在8∶1-12∶1之间。
采用这样一种方法，通过将树脂层过孔中的残留树脂去除，可以使得树脂层过孔下方的钝化层完全去除，使得像素电极层与过孔底部的TFT的漏极或引线良好贴合。从而解决了现有技术在过孔刻蚀过程中产生刻蚀残留，导致像素电极层与过孔底部的TFT的漏极或引线接触不良的问题。
S305、对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线。
具体的，可以在含氟气体和氧气的环境中利用构图工艺处理树脂层过孔以暴露出TFT的漏极或引线，形成过孔，其中，含氟气体的流量可以在300-600sccm之间，氧气的流量可以在300-800sccm之间，氧气和含氟气体的质量比可以在1∶3-1∶1之间。当需要设置过孔处位于像素区域时，过孔的底部为TFT的漏极；当需要设置过孔处位于***引线区域时，过孔的底部为栅线引线或数据线引线。
S306、利用刻蚀工艺处理该过孔，使树脂层侧壁和钝化层侧壁平缓衔接。
具体的，可以在含氟气体和氧气的环境中利用灰化工艺处理过孔，使树脂层侧壁和钝化层侧壁平缓衔接，其中，含氟气体的流量在20-200sccm之间，氧气的流量可以在500-2000sccm之间，氧气和含氟气体的质量比可以在15∶1-25∶1之间。
本发明实施例提供的TFT阵列基板制造方法。包括：在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线；利用刻蚀工艺处理该过孔，优选的，使用灰化工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。采用这样一种方法，通过刻蚀工艺处理过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接，从而解决了现有技术在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题，从而大大提高了显示装置的质量。另一方面，通过将树脂层过孔中的残留树脂去除，可以使得树脂层过孔下方的钝化层完全去除，从而使像素电极层与过孔底部的TFT的漏极或引线良好贴合。从而解决了现有技术在过孔刻蚀过程中产生刻蚀残留，导致像素电极层与过孔底部的TFT的漏极或引线接触不良的问题。
本发明又一实施例提供了一种TFT阵列基板制造方法，如图4所示，包括：
S401、在透明基板上依次形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层；其中，栅金属层包括：栅线以及TFT的栅电极，源漏金属层包括：数据线、以及TFT的源电极和漏电极。
具体的，在透明基板上依次形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层的过程可以参照现有技术，利用构图工艺，通过曝光、显影、刻蚀工序依次形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层。
S402、在源漏金属层上制作钝化层薄膜以及树脂层薄膜。
具体的，可以采用化学气相沉积法在已形成栅金属层、栅绝缘层薄膜、有源层、源漏金属层的透明基板上沉积形成钝化层薄膜，其材料通常是氮化硅、氧化硅或透明的有机树脂材料。在已沉积钝化层薄膜的透明基板上涂覆树脂形成树脂层薄膜。其中，树脂层薄膜可以为感光树脂，或不感光的一般透明树脂材料，优选的使用感光树脂材料。
S403、当树脂层采用非感光树脂材料时，利用构图工艺刻蚀形成树脂层过孔。
具体的，当树脂层采用非感光树脂材料时，可以直接利用灰化工艺刻蚀形成树脂层过孔。
S404、对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线。
具体的，可以在含氟气体和氧气的环境中利用构图工艺处理树脂层过孔以暴露出TFT的漏极或引线，形成过孔，其中，含氟气体的流量在300-600sccm之间，氧气的流量在300-800sccm之间，氧气和含氟气体的质量比在1∶3-1∶1之间。当需要设置过孔处位于像素区域时，过孔的底部为TFT的漏极；当需要设置的过孔处位于***引线区域时，过孔的底部为栅线引线和数据线引线。
S405、利用刻蚀工艺处理该过孔，使树脂层侧壁和钝化层侧壁平缓衔接。
具体的，可以在含氟气体和氧气的环境中利用灰化工艺处理过孔，使树脂层侧壁和钝化层侧壁平缓衔接，其中，含氟气体的流量在20-200sccm之间，氧气的流量在500-2000sccm之间，氧气和含氟气体的质量比为15∶1-25∶1。
本发明实施例提供的TFT阵列基板制造方法。包括：在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线；利用刻蚀工艺处理该过孔，优选的，使用灰化工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。采用这样一种方法，通过刻蚀工艺处理过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接，从而解决了现有技术在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题，从而大大提高了显示装置的质量。
本发明实施例提供了一种利用上述方法制作的TFT阵列基板，如图5所示，包括：
形成有钝化层薄膜51以及树脂层薄膜52的TFT阵列基板，在TFT阵列基板上形成有贯穿树脂层薄膜52以及钝化层薄膜51的过孔53。
过孔53的树脂层侧壁531和钝化层侧壁532平缓衔接。
本发明实施例提供的TFT阵列基板，其制造方法包括：在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线；利用刻蚀工艺处理该过孔，优选的，使用灰化工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。采用这样一种方法，通过刻蚀工艺处理过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接，从而解决了现有技术在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题，从而大大提高了显示装置的质量。
进一步地，过孔53的底部533为TFT的漏极或栅线引线或数据线引线。
需要说明的是，过孔53可以是位于像素区域的过孔，也可以是位于***引线区域的过孔。当过孔53是位于像素区域的过孔时，过孔53的底部533为TFT的漏极；当过孔53是位于***引线区域时，过孔53的底部533为栅线引线或数据线引线。
这样一来，通过将树脂层过孔中的残留树脂去除，可以使得树脂层过孔下方的钝化层完全去除，使得像素电极层与过孔底部的TFT的漏极或引线良好贴合。从而解决了现有技术在过孔刻蚀过程中产生刻蚀残留，导致像素电极层与过孔底部的TFT的漏极或引线接触不良的问题。
本发明实施例提供了一种显示装置，该显示装置可以是TFT-LCD或OLED显示装置。该显示装置中包括如上所述的TFT阵列基板。
阵列基板的结构在之前已做过较为详尽的描述，故在此不再赘述。
本发明实施例提供的显示装置，包括TFT-LCD或OLED显示装置。其TFT阵列基板的制造方法包括：在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；对该树脂层过孔下方的钝化层进行刻蚀形成贯穿树脂层薄膜和钝化层薄膜的过孔，以暴露出TFT的漏极或引线；利用刻蚀工艺处理该过孔，优选的，使用灰化工艺处理该过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接。采用这样一种方法，通过刻蚀工艺处理过孔，使该过孔的树脂层侧壁和钝化层侧壁平缓衔接，从而解决了现有技术在形成过孔后，过孔的树脂层侧壁与钝化层侧壁之间形成内阶梯状的倒钩角，导致像素电极断裂，产品良率下降的问题，从而大大提高了显示装置的质量。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (5)

1.一种TFT阵列基板的制造方法，其特征在于，包括：
在形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板上通过构图工艺去除需要设置过孔处的树脂，形成树脂层过孔；
对所述树脂层过孔下方的钝化层进行刻蚀形成贯穿所述树脂层薄膜和所述钝化层薄膜的过孔，以暴露出所述TFT的漏极或引线；
利用刻蚀工艺处理所述过孔，使所述过孔的树脂层侧壁和钝化层侧壁平缓衔接；其中，所述树脂层采用感光树脂材料；
所述形成树脂层过孔包括：利用构图工艺对所述树脂层曝光显影形成所述树脂层过孔；
利用灰化工艺处理所述树脂层过孔处的残留树脂；
所述利用灰化工艺处理所述树脂层过孔处的残留树脂包括：
在含氟气体和氧气的环境中利用灰化工艺将所述树脂层过孔中的残留树脂去除，其中，所述含氟气体的流量在20-100sccm之间，所述氧气的流量在500-1000sccm之间，氧气和含氟气体的质量比在为8∶1-12∶1之间；
对所述树脂层过孔下方的钝化层进行刻蚀包括：
在含氟气体和氧气的环境中对所述树脂层过孔下方的钝化层进行刻蚀；其中，所述含氟气体的流量在300-600sccm之间，所述氧气的流量在300-800sccm之间，氧气和含氟气体的质量比在1∶3-1∶1之间；
利用刻蚀工艺处理所述过孔，使所述过孔的树脂层侧壁和钝化层侧壁平缓衔接包括：
在含氟气体和氧气的环境中利用灰化工艺处理所述过孔，使所述过孔的树脂层侧壁和钝化层侧壁平缓衔接，其中，所述含氟气体的流量在20-200sccm之间，所述氧气的流量在500-2000sccm之间，氧气和含氟气体的质量比在15∶1-25∶1之间。
2.根据权利要求1所述的方法，其特征在于，当所述需要设置过孔处位于像素区域时，所述过孔的底部为TFT的漏极；当所述需要设置过孔处位于***引线区域时，所述过孔的底部为栅线引线或数据线引线。
3.一种利用权利要求1或2所述的方法制作的TFT阵列基板，包括：形成有钝化层薄膜以及树脂层薄膜的TFT阵列基板，在所述TFT阵列基板上形成有贯穿所述钝化层薄膜以及树脂层薄膜的过孔，其特征在于，
所述过孔的树脂层侧壁和钝化层侧壁平缓衔接。
4.根据权利要求3所述的TFT阵列基板，其特征在于，所述过孔的底部为所述TFT的漏极或栅线引线或数据线引线。
5.一种显示装置，其特征在于，包括：如权利要求3或4所述的TFT阵列基板。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW531794B (en) * 2001-02-02 2003-05-11 Ibm Thin film transistor, method for manufacturing the same and display device including the same
CN101015042A (zh) * 2004-09-07 2007-08-08 兰姆研究公司 脱除衬底上光刻胶的方法
US7268366B2 (en) * 2000-12-29 2007-09-11 Lg.Philips Lcd Co., Ltd. Method of fabricating X-ray detecting device
CN101866877A (zh) * 2009-04-14 2010-10-20 中芯国际集成电路制造(上海)有限公司 通孔形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4961820A (en) * 1988-06-09 1990-10-09 Fujitsu Limited Ashing method for removing an organic film on a substance of a semiconductor device under fabrication
US6465159B1 (en) 1999-06-28 2002-10-15 Lam Research Corporation Method and apparatus for side wall passivation for organic etch
US6440864B1 (en) * 2000-06-30 2002-08-27 Applied Materials Inc. Substrate cleaning process
US7309448B2 (en) * 2003-08-08 2007-12-18 Applied Materials, Inc. Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material
US7119411B2 (en) * 2004-02-17 2006-10-10 Au Optronics Corp. Interconnect structure for TFT-array substrate and method for fabricating the same
JP4925314B2 (ja) * 2007-05-30 2012-04-25 カシオ計算機株式会社 窒化シリコン膜のドライエッチング方法および薄膜トランジスタの製造方法
KR101570482B1 (ko) 2009-10-15 2015-11-20 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN102651370B (zh) 2012-01-04 2014-12-10 京东方科技集团股份有限公司 一种tft阵列基板、制造方法及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268366B2 (en) * 2000-12-29 2007-09-11 Lg.Philips Lcd Co., Ltd. Method of fabricating X-ray detecting device
TW531794B (en) * 2001-02-02 2003-05-11 Ibm Thin film transistor, method for manufacturing the same and display device including the same
CN101015042A (zh) * 2004-09-07 2007-08-08 兰姆研究公司 脱除衬底上光刻胶的方法
CN101866877A (zh) * 2009-04-14 2010-10-20 中芯国际集成电路制造(上海)有限公司 通孔形成方法

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