CN102468227A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN102468227A CN102468227A CN2010105514751A CN201010551475A CN102468227A CN 102468227 A CN102468227 A CN 102468227A CN 2010105514751 A CN2010105514751 A CN 2010105514751A CN 201010551475 A CN201010551475 A CN 201010551475A CN 102468227 A CN102468227 A CN 102468227A
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- photoresist
- plain conductor
- semiconductor structure
- hard mask
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Abstract
The invention provides a method for manufacturing a semiconductor structure. The method comprises the following steps of: comprising providing semiconductor substrates, wherein the semiconductor substrates are provided with metal conducting wire grooves of which plugs are exposed outside, and silicon nitride hard mask layers are covered on the semiconductor substrates arranged at two sides of the metal conducting wire grooves; coating photoresist on the semiconductor substrates,, wherein the metal conducting wire grooves in the semiconductor substrate are filled with the photoresist and the hard mask layers on the surfaces of the semiconductor substrates are totally covered; removing the photoresist on a titanium nitride hard mask layer and retaining the photoresist in the metal conducting wire grooves; removing the titanium nitride hard mask layer; and removing the photoresist in the metal conducting wire grooves. The silicon nitride hard mask layer is removed when the metal conducting wire grooves are subjected to dry etching, so that the depth-to-width ratio of the metal conducting wire grooves is reduced, the electroplating cavity generated in the subsequent copper electroplating process is avoided, and the reliability and the yield of the CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more concrete, the present invention relates to a kind of manufacturing approach of semiconductor structure.
Background technology
Along with complementary metal oxide semiconductors (CMOS) (CMOS; Complementary Metal OxideSemiconductor) process node is reduced to 45nm even littler; Its semiconductors, for example the etching of plain conductor groove in the back-end process is difficult to through traditional method control.In dry etch process, in order to obtain better advanced low-k materials etching selection property, usually utilize thickness be titanium nitride about 200 nanometers as the hard mask layer, form the plain conductor groove of semiconductor device through dry etching method.
Generally; Wet-cleaned is difficult under the situation that does not influence the dielectric constant values of ultra-low dielectric constant material in the Semiconductor substrate; Remove the etch residue in titanium nitride, SiCOH and the dry etching processes such as copper or tungsten, and these residues directly affect the formation of copper metal interconnecting wires in the subsequent technique.Utilize main component to be fluoride, amine, H
2O
2Can well address this problem with the HCX1206-1 solvent of deionized water, it can effectively remove the etch residue that in dry etching semiconductor device metal lead groove process, produces.Because the HCX1206-1 solvent is zero to the etching rate of titanium nitride hardmask, therefore in the removal process of whole etch residue to the ultralow dielectric constant layer the titanium nitride hard mask layer under between the dielectric constant of dielectric layer influence very little.
In existing technology of making semiconductor structure, usually etch the plain conductor groove with the titanium nitride hard mask layer and in nitrogen, semiconductor annealed after directly carry out the deposition and the electro-coppering metal interconnecting wires of barrier layer, inculating crystal layer.Yet along with the process node of cmos device drops to 40nm or even 32nm, the plain conductor groove of semiconductor device also can diminish accordingly.At this moment; In the dry etching process, form the depth-to-width ratio that hard mask layer can increase the plain conductor groove; This will produce bigger influence to the deposition of barrier layer in the subsequent technique and inculating crystal layer; Cause the barrier layer and the inculating crystal layer of deposition protruding, and then influence the subsequent copper electroplating technology, produce and electroplate the cavity at plain conductor groove opening place.
At publication number is the Chinese patent of CN1449015A, discloses manyly to improve copper and electroplate empty method through improving in the semiconductor structure depositing operation on barrier layer and inculating crystal layer.But this thickness through thinning barrier layer and inculating crystal layer improves the barrier layer and inculating crystal layer difference in thickness method can produce discrete point because of tectal bad again when deposition, causes in the subsequent copper electroplating technology, forming and electroplates the cavity.
Therefore, a kind of manufacturing approach of new semiconductor structure need be provided, reduce the depth-to-width ratio of the plain conductor groove of semiconductor device, prevent in the subsequent copper electroplating technology, to produce the cavity.
Summary of the invention
The problem that the present invention solves has provided a kind of manufacturing approach of semiconductor structure, through reducing the depth-to-width ratio of semiconductor device metal lead groove, produces when preventing to make the copper metal interconnecting wires and electroplates the cavity.
The manufacturing approach of semiconductor structure provided by the invention; Basic step comprises: Semiconductor substrate is provided; Have the plug metal of exposing lead groove on the said Semiconductor substrate, be coated with silicon nitride hardmask layer on the Semiconductor substrate of said plain conductor groove both sides; On Semiconductor substrate, be coated with photoresist, said photoresist fills up the plain conductor groove in the Semiconductor substrate and covers the hard mask layer on the semiconductor substrate surface fully; Remove the photoresist on the titanium nitride hard mask layer, keep photoresist in the plain conductor groove; Remove the titanium nitride hard mask layer; Remove the photoresist in the plain conductor groove.
Optional, said plain conductor groove adopts dry etching to form, and the etch residue utilization behind the dry etching includes fluoride, amine, H
2O
2HCX1206-1 removal of solvents with deionized water.
Optional, said coating photoresist adopts spin coating method.Said coating photoresist time range is 10 seconds to 20 seconds, and the rotating speed of photoresist coating machine is 100 rpms to 1400 rpms.
Optional, the thickness of said photoresist on the titanium nitride hard mask layer is less than 500 dusts.
Optional, photoresist adopts the deionized water of saturated ozone content to remove on the said titanium nitride hard mask layer.
Optional, the deionized water of said saturated ozone content includes ozone and deionized water, and wherein the mass ratio of ozone and deionized water is 10ppm to 20ppm, and be 1 to 2 minute the action time of the deionized water of saturated ozone content.
Optional, said titanium nitride hard mask layer adopts the SC1 solution removal.
Optional, said SC1 solution temperature scope is 50 to 60 degrees centigrade, NH in the SC1 solution
4OH: H
2O
2: H
2The volume ratio of O is 1: 1: 5 to 1: 1: 30.
Optional, the photoresist in the said plain conductor groove adopts single ethylether propane diols or propylene glycol methyl ether acetate to remove.
Optional, when adopting single ethylether propane diols or propylene glycol methyl ether acetate to remove the photoresist in the plain conductor groove, rotating said Semiconductor substrate, rotating speed is 300 to 500 rpms, rotational time is 20 seconds to 50 seconds.
Optional, also be included in the nitrogen after the photoresist in the removal plain conductor groove Semiconductor substrate is annealed.
Optional, the temperature range of said n 2 annealing is 280 to 320 degrees centigrade, time range is 8 to 15 minutes.
Compared with prior art; The present invention has the following advantages: the hard mask layer during through removal dry etching plain conductor groove; Reduced the depth-to-width ratio of plain conductor groove; Prevent when the depositing operation node from being barrier layer and the inculating crystal layer of 40nm even the following cmos device of 32nm that the barrier layer of deposition is protruding with inculating crystal layer at plain conductor groove opening place, avoid in the subsequent copper electroplating technology, producing and electroplate emptyly, improved the reliability and the yields of cmos device.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacturing approach of technology semiconductor structure of the present invention;
Fig. 2 to Fig. 9 shows each stage semiconductor structure generalized section of one embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part; In the manufacture craft of prior art semiconductor structure; Through after forming the plain conductor groove with the titanium nitride for the hard mask layer dry etching and in nitrogen, Semiconductor substrate being annealed, directly the plain conductor groove is carried out the deposition and the electro-coppering metal interconnecting wires of barrier layer, inculating crystal layer.Yet; When being reduced to 40nm or even 32nm along with the cmos device process node; Because the depth-to-width ratio of plain conductor groove is too big, causes the barrier layer of deposition and inculating crystal layer protruding, and then influence the subsequent copper electroplating technology at plain conductor groove opening place; Produce and electroplate the cavity, influenced the reliability and the yields of COMS device.
To the problems referred to above; Inventor of the present invention provides a kind of method that reduces plain conductor groove depth-to-width ratio through the hard mask layer in the removal dry etching process; Avoided the barrier layer and the inculating crystal layer of plain conductor groove opening place deposition protruding, formed copper and electroplate the cavity.
Referring to Fig. 1, show the flow chart of semiconductor structure manufacturing approach of the present invention, specifically comprise:
Execution in step S201 provides Semiconductor substrate, has the plain conductor groove that exposes connector on the said Semiconductor substrate, is coated with silicon nitride hardmask layer on the Semiconductor substrate of said plain conductor groove both sides;
Execution in step S202 is coated with photoresist on Semiconductor substrate, said photoresist fills up the plain conductor groove in the Semiconductor substrate and covers the hard mask layer on the semiconductor substrate surface fully;
Execution in step S203 removes the photoresist on the titanium nitride hard mask layer, keeps photoresist in the plain conductor groove;
Execution in step S204 removes the titanium nitride hard mask layer;
Execution in step S205 removes the photoresist in the plain conductor groove;
Execution in step S206 anneals to Semiconductor substrate in nitrogen.
The plain conductor groove depth-to-width ratio of the semiconductor structure that the above step of process forms is little; Avoid the barrier layer and the inculating crystal layer of plain conductor groove opening place deposition protruding; Prevent in follow-up copper electroplating technology, to form the cavity, improved the reliability and the yields of COMS device.
Below in conjunction with the specific embodiment of making semiconductor structure, the manufacturing approach of semiconductor structure of the present invention is further specified.
Referring to Fig. 2 to Fig. 9, show each the stage cross-sectional view that adopts semiconductor structure manufacturing approach of the present invention to make an embodiment of semiconductor structure.
As shown in Figure 2, Semiconductor substrate is provided, have the plain conductor groove that exposes connector 201 on the said Semiconductor substrate, be coated with silicon nitride hardmask layer 205 on the Semiconductor substrate of said plain conductor groove both sides.
Said Semiconductor substrate comprises silicon carbide barrier layer (NDC) 202, ultralow dielectric dielectric layer 203, silica protective layer 204 and the titanium nitride hard mask layer 205 that dielectric layer 200 between ultralow dielectric constant layer, nitrogen mix from top to bottom successively.The material of said connector 201 is copper or tungsten, usually with connecting the inner MOS device of metal interconnecting layer and Semiconductor substrate.
For dielectric layer 200, ultralow dielectric dielectric layer 203 between said ultralow dielectric constant layer; Common used material comprises the silica (Black Diamond) of SiOCH film, fluorine silex glass (FSG), carbon doping and the carborundum (BLOK) of nitrogen doping etc., is generally used for the insulating barrier of metal interconnecting wires.The silicon carbide barrier layer 202 that said nitrogen mixes is used for preventing the inter-level diffusion between substrate and the material that deposits subsequently.Said silica protective layer 204 is for being the silicon dioxide that the silicon source makes with tetraethoxysilane (TEOS).The hard mask layer of said titanium nitride when making dry etching plain conductor groove in the semiconductor structure process.Etch residue behind the dry etching plain conductor groove can be through including fluoride, amine, H
2O
2HCX1206-1 removal of solvents with deionized water.
As an embodiment, adopting HCX1206-1 removal of solvents etch polymers time range is 40 seconds to 90 seconds, and temperature range is 25 degrees centigrade to 40 degrees centigrade.
As shown in Figure 3, coating photoresist 206 on Semiconductor substrate, said photoresist fills up the plain conductor groove in the Semiconductor substrate and covers the hard mask layer on the semiconductor substrate surface fully.
Photoresist 206 adopts the methods coating of spin coatings usually, and said photoresist is divided into photoresist 206a and the photoresist 206b two parts in the plain conductor groove on the titanium nitride hard mask layer, and wherein the thickness of the photoresist 206a on the titanium nitride hard mask layer is less than 500 dusts.
As an embodiment, the time range of said photoresist coating is 10 seconds to 20 seconds, and the rotating speed of photoresist coating machine is 100 rpms to 1400 rpms.
As shown in Figure 4, remove the photoresist 206b on the titanium nitride hard mask layer, keep photoresist 206a in the plain conductor groove.
Remove on the said titanium nitride hard mask layer after the photoresist 206a, the photoresist 206b in the residual metallic lead groove can protect copper or the tungsten plug 201 in the Semiconductor substrate when chemical etching titanium nitride hard mask layer.
As an embodiment; The deionized water of photoresist 206a saturated ozone content capable of using is removed on the said hard mask layer; Include ozone and deionized water in the deionized water of said saturated ozone content; Wherein the mass ratio of ozone and deionized water is 10ppm to 20ppm, and be 1 to 2 minute the action time of the deionized water of saturated ozone content.
As shown in Figure 5, remove titanium nitride hard mask layer 205.
Remove the depth-to-width ratio that said titanium nitride hard mask layer 205 can effectively reduce plain conductor groove in the semiconductor structure, barrier layer of avoiding in the subsequent technique being deposited and inculating crystal layer are protruding at plain conductor groove opening place, prevent that copper from electroplating the generation in cavity.
As an embodiment, said titanium nitride hard mask layer 205 adopts the SC1 solution removal.SC1 is the abbreviation of stand clean 1 solution, and the mixed solution that it is made up of deionized water, hydrogen peroxide solution and ammoniacal liquor can be removed titanium nitride hard mask layer 205 effectively under the situation that does not influence ultralow dielectric dielectric layer 203 and silica protective layer 204.Said SC1 solution temperature scope is 50 to 60 degrees centigrade, NH in the SC1 solution
4OH: H
2O
2: H
2The volume ratio of O is 1: 1: 5 to 1: 1: 30.
As shown in Figure 6, remove the photoresist 206b in the plain conductor groove.
Photoresist 206b in the said plain conductor groove adopts the single ethylether propane diols or the propylene glycol methyl ether acetate that are easy to volatilize to remove.In concrete embodiment, when adopting single ethylether propane diols or propylene glycol methyl ether acetate to remove the photoresist in the plain conductor groove, rotate said Semiconductor substrate, rotating speed is 300 to 500 rpms, rotational time is 20 seconds to 50 seconds.
Then, in nitrogen, Semiconductor substrate is annealed.
Wherein, nitrogen is as the protective gas in the annealing process, and said annealing can make the dielectric constant of ultra-low dielectric constant material in the Semiconductor substrate recover, and makes the volatilization of single ethylether propane diols residual in the plain conductor groove or propylene glycol methyl ether acetate simultaneously.In specific embodiment, the temperature range of said n 2 annealing is 280 to 320 degrees centigrade, and time range is 8 to 15 minutes.
At last, to shown in Figure 9, deposited barrier layer 208, inculating crystal layer 209 and electro-coppering metal interconnecting wires 210 in the plain conductor groove form the empty semiconductor structure of electroless plating like Fig. 7.
Said barrier layer 208 is the double-deck barrier layer of tantalum nitride/tantalum; Specifically can at first carry out the tantalum nitride membrane deposition; Carry out the metal tantalum thin film deposition again, be used to stop that the copper metal contacts with the direct of dielectric material, and play the transition cementation between dielectric material and the copper metal.The method deposition of physical vapour deposition (PVD) is adopted on said barrier layer 208, also can carry out through other method.Said inculating crystal layer 209 is deposited as the subsequent copper electroplating technology conductive layer is provided.The deposition of said barrier layer 208 and inculating crystal layer 209 and the electroplating technology of copper metal interconnecting wires 210 be as those skilled in the art's known technology, do not do at this and give unnecessary details.
Semiconductor structure based on above-mentioned formation method made is shown in figure 10, comprising: dielectric layer 200 and be formed at copper between the dielectric layer or tungsten plug 201 between ultralow dielectric constant layer between ultralow dielectric constant layer; The silicon carbide barrier layer 202 that nitrogen mixes is positioned between ultralow dielectric constant layer on the dielectric layer 200; Ultralow dielectric dielectric layer 203 is positioned on the silicon carbide barrier layer 202 of nitrogen doping; Silica protective layer 204 is positioned on the ultralow dielectric dielectric layer 203; Barrier layer 208 is covered in plain conductor flute surfaces in the Semiconductor substrate; Inculating crystal layer 209 is covered on the barrier layer 209; Copper metal interconnecting wires 210 is filled in the full whole plain conductor groove that has covered behind barrier layer 208 and the inculating crystal layer 209.
Compared with prior art; Hard mask layer when the manufacturing approach of said semiconductor structure is passed through to remove dry etching plain conductor groove; Reduced the depth-to-width ratio of plain conductor groove; Prevent when the depositing operation node from being barrier layer and the inculating crystal layer of 40nm even the following cmos device of 32nm that the barrier layer of deposition is protruding with inculating crystal layer at plain conductor groove opening place, avoid in the subsequent copper electroplating technology, producing and electroplate emptyly, improved the reliability and the yields of cmos device.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1. the manufacturing approach of a semiconductor structure is characterized in that, comprising:
Semiconductor substrate is provided, has the plain conductor groove that exposes connector on the said Semiconductor substrate, be coated with silicon nitride hardmask layer on the Semiconductor substrate of said plain conductor groove both sides;
On Semiconductor substrate, be coated with photoresist, said photoresist fills up the plain conductor groove in the Semiconductor substrate and covers the hard mask layer on the semiconductor substrate surface fully;
Remove the photoresist on the titanium nitride hard mask layer, keep photoresist in the plain conductor groove;
Remove the titanium nitride hard mask layer;
Remove the photoresist in the plain conductor groove.
2. the manufacturing approach of semiconductor structure as claimed in claim 1 is characterized in that, said plain conductor groove adopts dry etching to form, and the etch residue utilization behind the dry etching includes fluoride, amine, H
2O
2HCX1206-1 removal of solvents with deionized water.
3. the manufacturing approach of semiconductor structure as claimed in claim 1; It is characterized in that; Said coating photoresist adopts spin coating method, and the time range of said coating photoresist is 10 seconds to 20 seconds, and the rotating speed of photoresist coating machine is 100 rpms to 1400 rpms.
4. the manufacturing approach of semiconductor structure as claimed in claim 1 is characterized in that, the thickness of said photoresist on the titanium nitride hard mask layer is less than 500 dusts.
5. the manufacturing approach of semiconductor structure as claimed in claim 1 is characterized in that, the photoresist on the said titanium nitride hard mask layer adopts the deionized water of saturated ozone content to remove.
6. the manufacturing approach of semiconductor structure as claimed in claim 5; It is characterized in that; The deionized water of said saturated ozone content includes ozone and deionized water; Wherein the mass ratio of ozone and deionized water is 10ppm to 20ppm, and be 1 to 2 minute the action time of the deionized water of saturated ozone content.
7. the manufacturing approach of semiconductor structure as claimed in claim 1 is characterized in that, said titanium nitride hard mask layer adopts the SC1 solution removal.
8. the manufacturing approach of semiconductor structure as claimed in claim 7 is characterized in that, said SC1 solution temperature scope is 50 to 60 degrees centigrade, NH in the SC1 solution
4OH: H
2O
2: H
2The volume ratio of O is 1: 1: 5 to 1: 1: 30.
9. the manufacturing approach of semiconductor structure as claimed in claim 1 is characterized in that, the photoresist in the said plain conductor groove adopts single ethylether propane diols or propylene glycol methyl ether acetate to remove.
10. the manufacturing approach of semiconductor structure as claimed in claim 9; It is characterized in that; When adopting single ethylether propane diols or propylene glycol methyl ether acetate to remove the photoresist in the plain conductor groove; Rotate said Semiconductor substrate, rotating speed is 300 to 500 rpms, and rotational time is 20 seconds to 50 seconds.
11. the manufacturing approach of semiconductor structure as claimed in claim 1 is characterized in that, the photoresist of removing in the plain conductor groove also comprises afterwards: in nitrogen, Semiconductor substrate is annealed.
12. the manufacturing approach of semiconductor structure as claimed in claim 11 is characterized in that, the temperature range of said annealing is 280 to 320 degrees centigrade, and time range is 8 to 15 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105514751A CN102468227A (en) | 2010-11-19 | 2010-11-19 | Method for manufacturing semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105514751A CN102468227A (en) | 2010-11-19 | 2010-11-19 | Method for manufacturing semiconductor structure |
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|---|---|
| CN102468227A true CN102468227A (en) | 2012-05-23 |
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| CN2010105514751A Pending CN102468227A (en) | 2010-11-19 | 2010-11-19 | Method for manufacturing semiconductor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952721A (en) * | 2014-03-31 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Post-processing method for removing photoresist and manufacture method of interconnection layer structure |
| WO2020135012A1 (en) * | 2018-12-28 | 2020-07-02 | 芯创智（北京）微电子有限公司 | Preparation method for accurate pattern of integrated circuit |
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| US6294451B1 (en) * | 1995-11-10 | 2001-09-25 | Nippon Steel Corporation | Semiconductor device and method for manufacturing the same |
| CN1728358A (en) * | 2004-07-29 | 2006-02-01 | 三星电子株式会社 | The manufacture method of dual damascene interconnection |
| CN1812074A (en) * | 2004-12-08 | 2006-08-02 | 三星电子株式会社 | Methods for forming interconnecting structure and semiconductor devices |
| US20090140307A1 (en) * | 2007-11-29 | 2009-06-04 | Peter Baars | Conductive line comprising a capping layer |
| CN101488472A (en) * | 2007-12-22 | 2009-07-22 | 东部高科股份有限公司 | Method for manufacturing metal line of semiconductor device |
-
2010
- 2010-11-19 CN CN2010105514751A patent/CN102468227A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294451B1 (en) * | 1995-11-10 | 2001-09-25 | Nippon Steel Corporation | Semiconductor device and method for manufacturing the same |
| CN1728358A (en) * | 2004-07-29 | 2006-02-01 | 三星电子株式会社 | The manufacture method of dual damascene interconnection |
| CN1812074A (en) * | 2004-12-08 | 2006-08-02 | 三星电子株式会社 | Methods for forming interconnecting structure and semiconductor devices |
| US20090140307A1 (en) * | 2007-11-29 | 2009-06-04 | Peter Baars | Conductive line comprising a capping layer |
| CN101488472A (en) * | 2007-12-22 | 2009-07-22 | 东部高科股份有限公司 | Method for manufacturing metal line of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952721A (en) * | 2014-03-31 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Post-processing method for removing photoresist and manufacture method of interconnection layer structure |
| CN104952721B (en) * | 2014-03-31 | 2018-03-23 | 中芯国际集成电路制造(上海)有限公司 | The preparation method for removing the post-processing approach and interconnection layer structure of photoresist |
| WO2020135012A1 (en) * | 2018-12-28 | 2020-07-02 | 芯创智（北京）微电子有限公司 | Preparation method for accurate pattern of integrated circuit |
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Application publication date: 20120523 |