CN104952721A - Post-processing method for removing photoresist and manufacture method of interconnection layer structure - Google Patents
Post-processing method for removing photoresist and manufacture method of interconnection layer structure Download PDFInfo
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Abstract
The invention provides a post-processing method for removing a photoresist and a manufacture method of an interconnection layer structure. In the post-processing method, a photoresist is etched and removed by using an NMP solution. The post-processing method comprises the following steps that ozone water is used to carry out fist time of cleaning on a semiconductor device with the removal of the photoresist, and deionized water is used to carry out second time of cleaning on the semiconductor device with the first time of cleaning. According to the post-processing method, firstly the organic residue and derived residual defects at the surface of the semiconductor device are stripped through the oxidative decomposition effect of the ozone water, then the stripped organic residue and derived residual defects are cleaned by using the deionized water, and thus the organic residue and the derived residual defects at the surface of the semiconductor device are removed to improve the stable performance of a semiconductor.
Description
Technical field
The present invention relates to the technical field of semiconductor integrated circuit, particularly relate to and a kind ofly remove the post-processing approach of photoresist and the manufacture method of interconnect layer structure.
Background technology
In the manufacture craft process of integrated circuit, usually need to deposit on the semiconductor device and cover one deck photoresist, then carry out follow-up technological operation to the semiconductor device not covering photoresist, such as etching, ion implantation, deposition etc., remove photoresist afterwards again.At present, the method for common removal photoresist comprises dry process and wet processing.In dry process, for the ashing dry process of oxygen plasma, it is the object being realized removing photoresist by plasma collision photoresist.Such dry process can cause infringement to a certain degree to semiconductor device usually.In wet processing, normally reacted by reagent and photoresist and realize removing the object of photoresist, this wet processing by optionally chemical reaction to remove photoresist, avoid the infringement to semiconductor device, become the method for the removal photoresist that range of application is the widest in production of integrated circuits field.
At present, the reagent that the most frequently used wet method removes photoresist (especially having the photoresist compared with heavy thickness) is N-methyl 2-pyrrolones (NMP), its concrete technical process is: be evenly sprayed on the photoresist on chip by techniques such as spin coatings by N-methyl 2-pyrrolones, react with photoresist at the temperature of 70 ~ 80 DEG C, the reaction time is 30-120 second; Then adopt washed with de-ionized water chip, remove residual photoresist and other organic substances.But; after N-methyl 2-pyrrolones etching removes photoresist, usually can produce organic substance residues on the chip surface, and then form residual defects; existing deionization cleaning chip technology can not effectively remove these residual defects, and these residual defects may affect the stability of semiconductor equipment.
Summary of the invention
The application aims to provide and a kind ofly removes the post-processing approach of photoresist and the manufacture method of interconnect layer structure, removes to solve existing nmp solution the problem semiconductor device surface that exists in photoresist process producing residual defects.
In order to solve the problem, the one side of the application there are provided a kind of post-processing approach removing photoresist, this photoresist adopts nmp solution to remove, and this post-processing approach comprises: adopt Ozone Water to carry out first time cleaning to the semiconductor device after removal photoresist; Deionized water is adopted to carry out second time cleaning to the semiconductor device after first time cleaning.
Further, in above-mentioned post-processing approach, O in Ozone Water
3content be 10 ~ 80ppm.
Further, in above-mentioned post-processing approach, the temperature that first time cleans is 25 ~ 45 DEG C, and the time is 20 ~ 120 seconds.
Further, in above-mentioned post-processing approach, the temperature of second time cleaning is 25 ~ 45 DEG C, and the time is 20 ~ 120 seconds.
Further, above-mentioned post-processing approach comprises further: the semiconductor device after adopting nitrogen to dry up second time cleaning.
The another aspect of the application there are provided a kind of manufacture method of interconnect layer structure.This manufacture method comprises: form inner first interconnection layer with the first metallic region; First interconnection layer is formed and has the second interconnection layer of the second through hole and have the hard mask of the first through hole, wherein the first through hole and the second through hole and the first metallic region position match; Photoresist layer is formed in the second through hole; Adopt the photoresist layer in nmp solution etching removal first metallic region; The post-processing approach of the above-mentioned removal photoresist of the application is adopted to clean the first metallic region; The second metallic region is formed in the second through hole.
Further, in above-mentioned manufacture method, before the step adopting the photoresist layer in nmp solution etching removal first metallic region, also comprise and outwards eat-back hard mask along the first through-hole wall, form the step with the hard mask of third through-hole, wherein the cross-sectional area of third through-hole is greater than the cross-sectional area of the first through hole.
Further, in above-mentioned manufacture method, form the inner step with the first interconnection layer of the first metallic region to comprise: form the first etching barrier layer and the first dielectric layer successively, to form the first interconnection layer on the surface in semiconductor device district along the direction away from semiconductor device district; Etch the first dielectric layer and the first etching barrier layer successively, in the first interconnection layer, form the first raceway groove; The first metallic region is formed in the first raceway groove.
Further, in above-mentioned manufacture method, the step that first interconnection layer is formed second interconnection layer with the second through hole and the hard mask with the first through hole comprises: form the second etching barrier layer and the second dielectric layer successively, to form the second interconnection layer at the first interconnect layer surfaces along the direction away from the first interconnection layer; Second interconnection layer forms hard mask, and etches hard mask, in hard mask, form the first through hole; The second dielectric layer and the second etching barrier layer is etched downwards, to form the second through hole making the first metallic region upper surface exposed along the first through hole.
Further, in above-mentioned manufacture method, the step forming photoresist layer comprises: formed and cover on hard mask and the photoresist preparation layers be filled in the first through hole and the second through hole; Etching is removed and is arranged on hard mask in photoresist preparation layers and is positioned at the photoresist of the first through hole, forms the photoresist layer being arranged in the second through hole.
The technical scheme of application the application, after adopting nmp solution etching to remove the photoresist on semiconductor device, first by the organic substance residues on the oxygenolysis stripping semiconductor device surface of Ozone Water and the residual defects that derives, and then the organic substance residues utilizing washed with de-ionized water to peel off and the residual defects that derives, thus the organic substance residues eliminated on semiconductor device surface and the residual defects that derives, to improve the stability of semiconductor.
Accompanying drawing explanation
The accompanying drawing forming a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 shows the schematic flow sheet of the post-processing approach of the removal photoresist provided according to the execution mode of the application;
Fig. 2 shows the schematic flow sheet of the manufacture method of the interconnect layer structure provided according to the execution mode of the application;
Fig. 3 shows in the manufacture method of the interconnect layer structure that the application's execution mode provides, and formation inside has the cross-sectional view of the matrix after the first interconnection layer of the first metallic region;
Fig. 4 shows the cross-sectional view of the matrix to form second interconnection layer with the second raceway groove and the hard mask with the first through hole on the first interconnection layer shown in Fig. 3 after;
Fig. 5 shows along etching the second interconnection layer 30 downwards of the first through hole 41 shown in Fig. 4, forms the cross-sectional view of the matrix after having the second interconnection layer 30 of the second through hole 37;
Fig. 6 shows to be formed and to cover on the hard mask shown in Fig. 5 and the cross-sectional view of matrix after being filled in the photoresist preparation layers in the first through hole and the second through hole;
Fig. 7 shows and is arranged on hard mask in etching removal photoresist preparation layers and is positioned at the photoresist preparation layers of the first through hole, forms the cross-sectional view of the matrix after being arranged in the photoresist layer of the second through hole;
Fig. 8 shows and outwards eat-backs hard mask along the first through-hole wall shown in Fig. 7, forms the cross-sectional view of the matrix after third through-hole;
Fig. 9 shows and adopts nmp solution etching to remove photoresist layer in the first metallic region shown in Fig. 8, and the cross-sectional view of matrix after the first metallic region is cleaned; And
Figure 10 shows the cross-sectional view of the matrix form the second metallic region in the second through hole shown in Fig. 9 after.
Embodiment
Below in conjunction with the embodiment of the application, the technical scheme of the application is described in detail, but following embodiment is only understand the application, and the application can not be limited, embodiment in the application and the feature in embodiment can combine mutually, and the multitude of different ways that the application can be defined by the claims and cover is implemented.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
From background technology, organic substance residues on the semiconductor device surface existed in existing nmp solution removal photoresist process can form the problem of residual defects, present inventor studies for the problems referred to above, propose a kind of post-processing approach removing photoresist, wherein photoresist adopts nmp solution etching to remove.As shown in Figure 1, this post-processing approach comprises: adopt Ozone Water to carry out first time cleaning to the semiconductor device after removal photoresist; Deionized water is adopted to carry out second time cleaning to the semiconductor device after first time cleaning again.Preferably, said method comprises further: the semiconductor device after adopting nitrogen to dry up second time cleaning.
In the method for above-mentioned removal photoresist, after employing N-methyl 2-pyrrolones etching removes photoresist, Ozone Water is first adopted to clean the semiconductor device after etching, owing to having very active, that there is strong oxidation antozone in Ozone Water, can by the organic substance residues on oxidation Decomposition stripping semiconductor device surface and the residual defects that derives; And then the organic substance residues utilizing washed with de-ionized water to peel off and the residual defects that derives, thus eliminate on semiconductor device surface and the object of residual defects that derives, avoid the impact of residual defects on electron transfer in semiconductor device, improve the stability of semiconductor device.
According to the instruction of the application's such scheme, those skilled in the art have the ability to select suitable process conditions to carry out above-mentioned post-processing approach.In a kind of preferred implementation of the application, in the method for above-mentioned removal photoresist, O in Ozone Water
3content be preferably 10 ~ 80ppm.In the another kind of preferred implementation of the application, in the step of first time cleaning, cleaning temperature is 25 ~ 45 DEG C, and the time is 20 ~ 120 seconds.In another preferred implementation of the application, in the step of second time cleaning, cleaning temperature is 25 ~ 45 DEG C, and the time is 20 ~ 120 seconds.Wherein particularly preferably adopt above-mentioned preferred parameter scope simultaneously.
Above-mentioned first time cleaning and second time cleaning can be infusion method and rotary spray method.In a kind of preferred implementation that the application provides, by spray process, first time cleaning is carried out to the semiconductor device after removal photoresist, comprising: O
3content be 10 ~ 80ppm, control the temperature of Ozone Water at 25 ~ 45 DEG C, clean the residual defects on semiconductor device, the time of cleaning is 20 ~ 120 seconds.In another embodiment that the application provides, by rotary spray method, second time cleaning is carried out to the semiconductor device after first time cleaning, its concrete steps comprise: sprayed to by deionized water on the semiconductor device after first time cleaning, and make deionized water be uniformly distributed on the chip surface by low speed rotation (300 ~ 500rpm), under temperature is 25 ~ 45 DEG C of conditions, carry out second time cleaning to the semiconductor device after first time cleaning, the time of cleaning is 20 ~ 120 seconds.In semiconductor technology below 28nm processing procedure, rotary spray method is preferably adopted to carry out above-mentioned cleaning to semiconductor device.
Meanwhile, present invention also provides a kind of manufacture method of interconnection structure.As shown in Figure 2, this manufacture method comprises: form inner first interconnection layer with the first metallic region; First interconnection layer is formed and has the second interconnection layer of the second through hole and have the hard mask of the first through hole, wherein the first through hole and the second through hole and the first metallic region position match; Photoresist layer is formed in the second through hole; Adopt the photoresist layer in nmp solution etching removal first metallic region; The post-processing approach of the above-mentioned removal photoresist of the application is adopted to clean the first metallic region; The second metallic region is formed in the second through hole.
In the interconnect layer structure manufacturing process that the application provides, the photoresist layer in the first metallic region is removed by the wet etching method adopting nmp solution and photoresist to react, avoid the infringement to the first metallic region surface, simultaneously, by adopting Ozone Water again, the semiconductor device after etching is cleaned, by the oxygenolysis of Ozone Water by the organic substance residues in the first metallic region and the other defect that derives peel off, and utilize washed with de-ionized water overburden, thus the organic substance residues reached on removal first metallic region surface and the object of other defect that derives.Namely can not produce the loss of interconnecting metal in the interconnection structure that the method provided according to the application prepares, also can not produce residual defects on the surface of interconnecting metal, thus provide the stability of semiconductor device.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Fig. 3 to 10 shows in the interconnect layer structure manufacturing process that the application provides, the cross-sectional view obtained after each step.Below in conjunction with Fig. 3 to 10, explain interconnect layer structure manufacture method provided by the present invention further.
First, first form inner first interconnection layer 20 with the first metallic region 25, its structure as shown in Figure 3.In a kind of preferred implementation of the application, the first interconnection layer 20 comprises the first etching barrier layer 21 and the first dielectric layer 23, and preferably, the material of the first etching barrier layer 21 includes but not limited to Si
3n
4; First dielectric layer 23 is the dielectric material of low-k (dielectric constant < 3), includes but not limited to SiCOH, porous Si.The use of dielectric materials under the condition not reducing wiring density, can reduce interconnection capacitance value effectively, makes the quickening of chip operation speed, lower power consumption.Preferably, form the inner step with the first interconnection layer 20 of the first metallic region 25 to comprise: form the first etching barrier layer 21, first dielectric layer 23 from lower to upper successively on the surface in semiconductor device district; First dielectric layer 23 and the first etching barrier layer 21 are etched, forms the first raceway groove; The first metallic region 25 is formed in the first raceway groove.In a preferred embodiment, semiconductor device district comprises dielectric layer 10 and contact metal layer 11(as shown in Figure 3).
In a kind of preferred implementation of the application, the step etching the first dielectric layer 23 and the first etching barrier layer 21 can adopt dry etch process.In a kind of preferred implementation of the application, adopt plasma etching industrial to etch the first dielectric layer 23 and the first etching barrier layer 21, processing step comprises: put on the carrier of reactor by chip to be etched, regulates the distance of focusing ring and substrate; Open heating power supply, wherein sputtering power is 400 ~ 1200 watts, makes oxygen and helium that ionization occur and forms plasma; Plasma is by part Si
3n
4bombard out with SiCOH.Wherein, etching temperature is 25 ~ 50 DEG C, and etch period is 30 ~ 90 seconds.
In a kind of preferred implementation of the application, the step forming the first metallic region 25 in the first raceway groove comprises: plated metal in the first raceway groove, then carries out planarization to metal.Preferably, above-mentioned metal includes but not limited to Cu or Al etc.Depositing operation includes but not limited to physical vapour deposition (PVD), chemical vapour deposition (CVD), plating, chemical plating, and flatening process includes but not limited to chemico-mechanical polishing.Above-mentioned technique is state of the art, does not repeat them here.
Complete formed inner there is the step of the first interconnection layer 20 of the first metallic region 25 after, first interconnection layer 20 is formed second interconnection layer 30 with the second through hole 37 and the hard mask 40 with the first through hole 41, and wherein the first through hole 41 and the second through hole 37 and the first metallic region 25 position match.In a preferred embodiment, in order to fill the second metal better, usually conform to the cross-sectional area of the first metallic region 25 near the cross-sectional area of the part of the first metallic region 25 in the second through hole 37 formed in the second interconnection layer 30, and be greater than the cross-sectional area of the first metallic region 25 away from the cross-sectional area of the part of the first metallic region 25.
The step of the second interconnection layer 30 that preparation has the second through hole 37 of said structure and the hard mask 40 with the first through hole 41 comprises: form the second etching barrier layer 31, second dielectric layer 33 on the first interconnection layer 20 surface from lower to upper successively and have the hard mask layer 40 of elementary through hole, the second dielectric layer 33 is etched downwards along elementary through hole, form the second raceway groove 35 ' that cross-sectional area conforms to the cross-sectional area of the first metallic region 25, and eat-back hard mask 40, elementary via area is made to become large, form the first through hole 41, and then form structure as shown in Figure 4; Along the first through hole 41, etching the second interconnection layer 30 to the first metallic region 25 upper surface is exposed downwards, the cross-sectional area formed near the part of the first metallic region 25 conforms to the cross-sectional area of the first metallic region 25, and be greater than the second through hole 37 of the cross-sectional area of the first metallic region 25 away from the cross-sectional area of the part of the first metallic region 25, and then form basal body structure as shown in Figure 5.
In order to improve the bonding force between above-mentioned hard mask 40 and the second interconnection layer 30, in a preferred embodiment, between above-mentioned hard mask 40 and the second interconnection layer 30, adhesion layer 50(is formed as shown in Figure 4 and Figure 5).This adhesion layer includes but not limited to adopt SiO
2.This adhesion layer 50 has the adhesion layer through hole matched with the first through hole 41 in hard mask 40.What now the application provided eat-backs in hard masking method, formed in the step of photoresist layer 60 in the second through hole, the upper surface of photoresist layer 60 lower than the upper surface (as shown in Figure 7) of second dielectric layer 33, or higher than second dielectric layer 33 upper surface and be equal to or less than the upper surface (not marking in figure) of this adhesion layer 50.
Those skilled in the art it should be explicitly made clear at this point, the method forming above-mentioned second interconnection layer 30 with the second through hole 37 and the hard mask 40 with the first through hole 41 has a lot, is not limited in above-mentioned preferred implementation.In the another kind of preferred implementation of the application, the step forming second interconnection layer 30 with the second through hole 37 and the hard mask 40 with the first through hole 41 comprises: form the second etching barrier layer 31, second dielectric layer 33 on the first interconnection layer 20 surface from lower to upper successively and have the hard mask 40 of the first through hole 41; Along the first through hole 41 etching the second dielectric layer 33 and the second etching barrier layer 31 downwards, formed and make the second through hole 37 that the first metallic region 25 upper surface is exposed.It should be noted that in view of those skilled in the art can realize this preferred implementation completely according to instruction of the present invention, not providing the structure chart of this preferred implementation in the accompanying drawings to saving space.
In above-mentioned two kinds of preferred implementations, the structure of the second interconnection layer 30 and hard mask 40 can be arranged according to prior art.Preferably, the second interconnection layer 30 comprises the second etching barrier layer 31 and the second dielectric layer 33.Preferably, the second etching barrier layer 31 material includes but not limited to Si
3n
4; Second dielectric layer 33 is the dielectric material of low-k (dielectric constant < 3), includes but not limited to SiCOH, porous Si.Hard mask 40 includes but not limited to TiN, Si
3n
4or one or more in SiON.The technique forming above-mentioned second interconnection layer 30 and hard mask 40 includes but not limited to spin coating proceeding, CVD technique, and above-mentioned technique is the state of the art, does not repeat them here.
The step etching above-mentioned hard mask 40 and the second interconnection layer 30 can adopt dry etch process.More preferably adopt plasma etching industrial, adopt the process conditions of plasma etching industrial to comprise: sputtering power is 400 ~ 1200 watts, and etching temperature is 25 ~ 50 DEG C, and etch period is 30 ~ 120 seconds.
Complete form second interconnection layer 30 with the second through hole 37 and the step of hard mask 40 with the first through hole 41 on the first interconnection layer 20 after, in the second through hole 37, form photoresist layer 60.In this kind of preferred implementation, the step forming photoresist layer 60 comprises: formed and cover on hard mask 40, and be filled in the photoresist preparation layers 60 ' in the first through hole 41 and the second through hole 37, and then forms structure as described in Figure 6; Etching is removed in photoresist preparation layers 60 ' and is positioned on hard mask 40, and is arranged in the photoresist preparation layers 60 ' of the first through hole 41, forms the photoresist layer 60 being arranged in the second through hole 37, and then forms basal body structure as shown in Figure 7.The process window of the second metallic region 70 is formed in order to increase subsequent deposition, in a preferred embodiment, after forming the step of above-mentioned photoresist layer 60, hard mask 40 is outwards eat-back along the first through hole 41 inwall, form the third through-hole 43 that cross-sectional area is greater than the cross-sectional area of the first through hole 41, and then form basal body structure as shown in Figure 8.
The method forming above-mentioned photoresist preparation layers 60 ' includes but not limited to the technique such as spin coating, deposition; The step of above-mentioned etching photoresist preparation layers 60 ' comprising: adopt N-methyl 2-pyrrolones to carry out wet etching to photoresist preparation layers 60 ', wet etching can adopt infusion method and rotary spray method.In a kind of preferred implementation that the application provides, etch above-mentioned photoresist preparation layers 60 ' by rotary spray method, preferably etch technological condition is: by the temperature of N-methyl 2-pyrrolones solution at 70 DEG C ~ 80 DEG C, the time of etching is 30 ~ 120 seconds.
The step of eat-backing above-mentioned hard mask 40 can adopt the mode of wet etching, and wherein the reagent of wet etching is preferably H
2o
2solution or SC1 solution.Preferably, wet etching temperature is 25 ~ 45 DEG C, and etch period is 60 ~ 300 seconds.H is used in above-mentioned wet etching
2o
2during solution, preferably NH in this SC1 solution
4oH, H
2o
2and H
2the volume ratio of O is 1:1 ~ 4:50 ~ 200; Etching temperature is 25 ~ 45 DEG C; Etch period is 60 ~ 300 seconds.In above-mentioned steps; because the second through hole 37 be arranged in below hard mask 40 forms photoresist layer 60; therefore when etching hard mask layer 40; photoresist layer 60 can be protected the second through hole 37; thus avoid etching liquid damage is caused to the device bottom hard mask 40, improve the stability of chip.
Eat-back in the step of above-mentioned hard mask 40, etch back process can adopt infusion method or rotary spray method.In a preferred embodiment, the concrete steps of eat-backing hard mask layer 40 by infusion method comprise: by H
2o
2or SC1 solution is placed in etching groove, control the temperature of cleaning reagent in etching groove at 25 ~ 45 DEG C, the silicon chip then comprising hard mask 40 is placed in H
2o
2or in SC1 solution, hard mask 40 is etched, the time of etching is 60 ~ 300 seconds.In another embodiment, the concrete steps of being eat-back hard mask layer 40 by rotary spray method are comprised: H
2o
2or SC1 liquid spray to comprise hard mask 40 to be etched silicon chip on, and by low speed rotation (300 ~ 500rpm), SC1 dissolution homogeneity is distributed on the chip surface, under temperature is 25 ~ 50 DEG C of parts, etch hard mask, the time of etching is 60 ~ 300 seconds.
After completing the step forming above-mentioned photoresist layer 60 in the second through hole 37, adopt the photoresist layer 60 in nmp solution etching removal first metallic region, and the post-processing approach of the removal photoresist adopting the application to provide cleans the first metallic region 25, and then form basal body structure as shown in Figure 9.Etching is removed in the process of above-mentioned photoresist and is preferably adopted infusion method or rotary spray method.When removing photoresist layer by infusion method, a kind of preferred process conditions are: the temperature of N-methyl 2-pyrrolones solution is 70 DEG C ~ 80 DEG C, and the time of etching is 30 ~ 120 seconds.
In the step that described first metallic region 25 is cleaned, Ozone Water is first adopted to clean the carrying out after etching, owing to having very active, that there is strong oxidation antozone in Ozone Water, can by the organic substance residues on oxidation Decomposition stripping semiconductor device surface and other defect; And then the residual organic matter utilizing washed with de-ionized water to peel off, thus reach the object of the residual defects removed on semiconductor device surface, and then improve the stability of semiconductor device.
Preferably, O in above-mentioned Ozone Water
3content be preferably 10 ~ 80ppm, first time cleaning temperature be 25 ~ 45 DEG C, the time is 20 ~ 120 seconds; The temperature of second time cleaning is 25 ~ 45 DEG C, and the time is 20 ~ 120 seconds.First, second cleaning can be infusion method and rotary spray method.In a preferred embodiment, carry out first time cleaning by rotary spray method to the semiconductor device after removal photoresist, preferred process conditions are: by O
3content be 10 ~ 80ppm, the temperature of Ozone Water is at 25 ~ 45 DEG C, and the time of cleaning is 20 ~ 120min.In another preferred embodiment, carry out second time cleaning by rotary spray method to the semiconductor device after first time cleaning, preferred process conditions are: the temperature of deionized water is 25 ~ 45 DEG C, and the time of cleaning is 20 ~ 120 seconds.
Complete the photoresist layer 60 adopted in nmp solution etching removal first metallic region, and after the post-processing approach of the removal photoresist adopting the application to provide step that the first metallic region 25 is cleaned, in the second through hole 37, form the second metallic region 70, and then form basal body structure as shown in Figure 10.In the optional execution mode of one, the step forming above-mentioned second metallic region 70 comprises: in the second through hole 37 and the deposited on silicon metal preparation layers of hard mask 40; And planarization is carried out to this metal preparation layers, to remove the metal preparation layers on hard mask 40 and hard mask 40 surface, form above-mentioned second metallic region 70, and then form basal body structure as shown in Figure 10.
Preferably, the material of above-mentioned metal preparation layers includes but not limited to adopt Cu, Al, the technique of plated metal preparation layers includes but not limited to physical vapour deposition (PVD), chemical vapour deposition (CVD), plating, chemical plating, and the technique of planarization material preparation layers includes but not limited to chemico-mechanical polishing.Above-mentioned technique is the state of the art, does not repeat them here.
The post-processing approach of removal photoresist and the manufacture method of interconnect layer structure that the application provides will be further illustrated below for the interconnection process of integrated circuit; but the post-processing approach of the removal photoresist that the application provides is not limited in this, in semiconductor technology, the post-processing approach of any removal photoresist all belongs to the protection range of the application.
Embodiment 1
Present embodiments provide a kind of post-processing approach removing photoresist in interconnect layer structure and the method making interconnect layer structure, comprise the following steps:
Form inner first interconnection layer with the first metallic region, comprise the following steps and comprise: form the first etching barrier layer Si from lower to upper successively on the surface in semiconductor device district
3n
4, the first dielectric layer SiCOH; To the first dielectric layer SiCOH and the first etching barrier layer Si
3n
4etch, form the first raceway groove; A Cu region is formed in the first raceway groove.
First interconnection layer is formed and there is the second interconnection layer of the second through hole and there is the hard mask of the first through hole, comprise the following steps: form the second etching barrier layer Si by chemical vapor deposition method from lower to upper successively at the first interconnect layer surfaces
3n
4, the second dielectric layer SiCOH and there is the hard mask layer TiN of elementary through hole; The second dielectric layer SiCOH is etched downwards along elementary through hole, form the second raceway groove, the cross-sectional area of this second raceway groove conforms to the cross-sectional area in a Cu region, eat-back hard mask TiN, elementary via area is made to become large, form the first through hole, and etch the second dielectric layer SiCOH downwards along the first through hole and be positioned at the second etching barrier layer Si below the second raceway groove
3n
4, conforms to the cross-sectional area in a Cu region near the cross-sectional area of a Cu area part, and be greater than the second through hole of the cross-sectional area in a Cu region away from the cross-sectional area of a Cu area part, and this second through hole makes a Cu region upper surface exposed.
In the second through hole, form photoresist layer, comprise the following steps: formed and cover on hard mask layer, and be filled in the photoresist preparation layers in the first through hole and the second through hole; Etch above-mentioned photoresist by rotary spray method, comprising: N-methyl 2-pyrrolones solution temperature, at 80 DEG C, etches photoresist, and the time of etching is 30 seconds.
Outwards eat-back hard mask along the first through-hole wall, form the hard mask with third through-hole, comprise the following steps: H
2o
2or SC1 liquid sprays on the silicon chip that comprises and treat hard mask, and by low speed rotation (300 ~ 500rpm), SC1 dissolution homogeneity is distributed on the chip surface, under temperature is 45 DEG C of parts, etch hard mask, the time of etching is 120 seconds.
Adopt the photoresist in nmp solution etching removal first metallic region, and the first metallic region cleaned, comprise the following steps:
N-methyl 2-pyrrolones is placed in etching groove, and control the temperature of cleaning reagent in etching groove at 75 DEG C, the silicon chip then comprising photoresist layer is placed in N-methyl 2-pyrrolones, and photoresist layer and N-methyl 2-pyrrolones are reacted, and the reaction time is 250 seconds;
By O
3content be that the Ozone Water of 10ppm is placed in etching groove, control the temperature of Ozone Water in etching groove at 45 DEG C, then the semiconductor device after removal photoresist is placed in Ozone Water, carry out first time cleaning to the residual defects on semiconductor device, the time of cleaning is 100 seconds;
Deionized water is sprayed on the semiconductor device after first time cleaning, and make deionized water be uniformly distributed on the chip surface by low speed rotation (300 ~ 500rpm), under temperature is 25 DEG C of conditions, carry out second time cleaning to the semiconductor device after first time cleaning, the time of cleaning is 90 seconds.
Embodiment 2
Present embodiments provide a kind of post-processing approach removing photoresist in interconnect layer structure and the method making interconnect layer structure, wherein form the inner step with the first interconnection layer of the first metallic region, in the second through hole, form the step of photoresist layer, outwards eat-back the step of hard mask along the first through-hole wall and to remove the step of the photoresist layer in the first metallic region identical with embodiment 1.
Wherein, after the step adopting the photoresist in nmp solution etching removal first metallic region, clean the first metallic region, the step of cleaning comprises:
N-methyl 2-pyrrolones is placed in etching groove, and control the temperature of cleaning reagent in etching groove at 75 DEG C, the silicon chip then comprising photoresist layer is placed in N-methyl 2-pyrrolones, and photoresist layer and N-methyl 2-pyrrolones are reacted, and the reaction time is 250 seconds;
By O
3content be that the Ozone Water of 40ppm is placed in etching groove, control the temperature of Ozone Water in etching groove at 45 DEG C, then the semiconductor device after removal photoresist is placed in Ozone Water, carry out first time cleaning to the residual defects on semiconductor device, the time of cleaning is 120 seconds;
Deionized water is sprayed on the semiconductor device after first time cleaning, and make deionized water be uniformly distributed on the chip surface by low speed rotation (300 ~ 500rpm), under temperature is 45 DEG C of conditions, carry out second time cleaning to the semiconductor device after first time cleaning, the time of cleaning is 120 seconds.
Embodiment 3
Present embodiments provide a kind of post-processing approach removing photoresist in interconnect layer structure and the method making interconnect layer structure, wherein form the inner step with the first interconnection layer of the first metallic region, in the second through hole, form the step of photoresist layer, outwards eat-back the step of hard mask along the first through-hole wall and to remove the step of the photoresist layer in the first metallic region identical with embodiment 1.
Wherein, after the step adopting the photoresist in nmp solution etching removal first metallic region, clean the first metallic region, the step of cleaning comprises:
In the second through hole, form photoresist layer, comprise the following steps: formed and cover on hard mask layer and the photoresist preparation layers be filled in the first through hole and the second through hole; Etch above-mentioned photoresist by rotary spray method, comprising: N-methyl 2-pyrrolones solution temperature, at 80 DEG C, etches photoresist, and the time of etching is 100 seconds.
Outwards eat-back hard mask along the first through-hole wall, form the hard mask with third through-hole, comprise the following steps: H
2o
2or SC1 liquid sprays on the silicon chip that comprises and treat hard mask, and by low speed rotation (300 ~ 500rpm), SC1 dissolution homogeneity is distributed on the chip surface, be under the condition of 45 DEG C in temperature, etch hard mask, the time of etching is 120 seconds.
Adopt the photoresist in nmp solution etching removal first metallic region, and the first metallic region cleaned, comprise the following steps:
N-methyl 2-pyrrolones is placed in etching groove, and control the temperature of cleaning reagent in etching groove at 75 DEG C, the silicon chip then comprising photoresist layer is placed in N-methyl 2-pyrrolones, and photoresist layer and N-methyl 2-pyrrolones are reacted, and the reaction time is 250 seconds;
By O
3content be that the Ozone Water of 80ppm is placed in etching groove, control the temperature of Ozone Water in etching groove at 30 DEG C, then the semiconductor device after removal photoresist is placed in Ozone Water, carry out first time cleaning to the residual defects on semiconductor device, the time of cleaning is 20 seconds;
Deionized water is sprayed on the semiconductor device after first time cleaning, and make deionized water be uniformly distributed on the chip surface by low speed rotation (300 ~ 500rpm), under temperature is 30 DEG C of conditions, carry out second time cleaning to the semiconductor device after first time cleaning, the time of cleaning is 20 seconds.
Comparative example 1
This comparative example provides a kind of post-processing approach removing photoresist in interconnect layer structure and the method making interconnect layer structure, wherein form the inner step with the first interconnection layer of the first metallic region, in the second through hole, form the step of photoresist layer, outwards eat-back the step of hard mask along the first through-hole wall and to remove the step of the photoresist layer in the first metallic region identical with embodiment 1.
Wherein, after the step adopting the photoresist in nmp solution etching removal first metallic region, clean the first metallic region, the step of cleaning comprises:
By EKC and H
2o
2mixed liquor sprays on chip, and makes EKC and H by low speed rotation (300 ~ 500rpm)
2o
2mixed liquor is uniformly distributed on the chip surface, under temperature is 70 DEG C of conditions, etches hard mask, and the time of etching is 45 seconds.
Observed the microscopic appearance carrying out cleaning front and back in embodiment 1 to 3 and comparative example 1 to Cu by SEM, and adopt the method for statistics to calculate Cu layer loss (diametrically) and Cu blemish clearance, its result asks for an interview table 1.As can be seen from Table 1, in comparative example 1, Cu layer waste (diametrically) is
cu blemish clearance is only 67%, and in the embodiment of the present application 1 to 3 Cu layer waste (diametrically) be 8 ~
cu blemish clearance is up to 89% ~ 92%.As can be seen from above-mentioned data analysis, the technical scheme that application the application provides, makes Cu layer waste in interconnection layer decrease 82% ~ 87%, Cu blemish clearance and is increased to 89% ~ 92% by original 67%.
Table 1
As can be seen from the above embodiments, the application's the above embodiments achieve following technique effect:
(1) after adopting nmp solution etching to remove the photoresist on semiconductor device, first by the organic substance residues on the oxygenolysis stripping semiconductor device surface of Ozone Water and the residual defects that derives, and then the organic substance residues utilizing washed with de-ionized water to peel off and the residual defects that derives, thus the organic substance residues eliminated on semiconductor device surface and the residual defects that derives, to improve the stability of semiconductor.
(2) wet etching method by adopting nmp solution and photoresist to react removes the photoresist layer in the first metallic region, avoids the infringement to the first metallic region surface, improves the stability of semiconductor.
These are only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (10)
1. remove a post-processing approach for photoresist, described photoresist adopts nmp solution etching to remove, and it is characterized in that, described post-processing approach comprises:
Ozone Water is adopted to carry out first time cleaning to the semiconductor device after the described photoresist of removal; And
Deionized water is adopted to carry out second time cleaning to the described semiconductor device after described first time cleaning.
2. post-processing approach according to claim 1, is characterized in that, O in described Ozone Water
3content be 10 ~ 80ppm.
3. post-processing approach according to claim 2, is characterized in that, the temperature of described first time cleaning is 25 ~ 45 DEG C, and the time is 20 ~ 120 seconds.
4. post-processing approach according to claim 1, is characterized in that, the temperature of described second time cleaning is 25 ~ 45 DEG C, and the time is 20 ~ 120 seconds.
5. post-processing approach according to any one of claim 1 to 4, is characterized in that, described post-processing approach comprises further: the described semiconductor device after adopting nitrogen to dry up the cleaning of described second time.
6. a manufacture method for interconnect layer structure, is characterized in that, described manufacture method comprises:
Form inner first interconnection layer with the first metallic region;
Described first interconnection layer is formed and has the second interconnection layer of the second through hole and have the hard mask of the first through hole, wherein said first through hole and described second through hole and described first metallic region position match;
Photoresist layer is formed in described second through hole;
Adopt the photoresist layer in described first metallic region of nmp solution etching removal;
Adopt described first metallic region of post-processing approach cleaning of the removal photoresist according to any one of claim 1 to 5; And
The second metallic region is formed in described second through hole.
7. manufacture method according to claim 6, it is characterized in that, before adopting nmp solution etching to remove the step of the described photoresist layer in described first metallic region, also comprise and outwards eat-back described hard mask along described first through-hole wall, form the step with the hard mask of third through-hole, the cross-sectional area of wherein said third through-hole is greater than the cross-sectional area of described first through hole.
8. manufacture method according to claim 6, is characterized in that, forms the inner step with described first interconnection layer of described first metallic region and comprises:
The first etching barrier layer and the first dielectric layer is formed successively, to form described first interconnection layer along the direction away from described semiconductor device district on the surface in semiconductor device district;
Etch described first dielectric layer and described first etching barrier layer successively, in described first interconnection layer, form the first raceway groove;
Described first metallic region is formed in described first raceway groove.
9. manufacture method according to claim 6, is characterized in that, the step that described first interconnection layer is formed second interconnection layer with the second through hole and the hard mask with the first through hole comprises:
The second etching barrier layer and the second dielectric layer is formed successively, to form described second interconnection layer along the direction away from described first interconnection layer at described first interconnect layer surfaces;
Described second interconnection layer forms hard mask, and etches described hard mask, in described hard mask, form described first through hole;
Described second dielectric layer and the second etching barrier layer is etched downwards, to form described second through hole making the first metallic region upper surface exposed along described first through hole.
10. method according to claim 6, is characterized in that, the step forming described photoresist layer comprises:
Formed and cover on described hard mask layer and the photoresist preparation layers be filled in described first through hole and the second through hole;
Etching is removed and is arranged on described hard mask in described photoresist preparation layers and is positioned at the photoresist of described first through hole, forms the photoresist layer being arranged in described second through hole.
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| CN111105996A (en) * | 2020-01-03 | 2020-05-05 | 长江存储科技有限责任公司 | Cleaning method and cleaning equipment for workpiece to be cleaned |
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| CN1649101A (en) * | 2004-01-30 | 2005-08-03 | 松下电器产业株式会社 | Manufacturing method for compound semiconductor device |
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