CN107527862B - semiconductor device and manufacturing method thereof - Google Patents
semiconductor device and manufacturing method thereof Download PDFInfo
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- CN107527862B CN107527862B CN201610458068.3A CN201610458068A CN107527862B CN 107527862 B CN107527862 B CN 107527862B CN 201610458068 A CN201610458068 A CN 201610458068A CN 107527862 B CN107527862 B CN 107527862B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
Abstract
The invention provides a method for manufacturing a semiconductor device, which comprises the steps of providing a semiconductor substrate; forming a low-k dielectric layer and a copper interconnection structure in the low-k dielectric layer on the semiconductor substrate; depositing a layer of diblock copolymer material on the surface of the copper interconnect structure and the low-k dielectric layer; carrying out self-assembly treatment on the diblock copolymer material layer to form a first monomer and a second monomer which are arranged at intervals; removing the first monomer to form a plurality of openings between the second monomer; partially etching the copper interconnection structure by taking the second monomer as a mask so as to form a plurality of grooves on the surface of the copper interconnection structure; removing the second monomer; depositing an amorphous silicon layer on the surface of the copper interconnection structure and the low-k dielectric layer; performing heat treatment to form a copper silicon covering layer on the surface of the copper interconnection structure; and nitriding the copper silicon covering layer to form a copper silicon nitrogen covering layer.
Description
Technical Field
the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the development of integrated circuits, the feature size is continuously reduced, and the current density introduced by a metal wire is rapidly increased; meanwhile, the increase of chip integration level leads to an increase of power consumption per unit area, and thus, the reliability of metal wiring has been an important issue concerned in IC design and manufacture. In a metal wire, electrons moving in the opposite direction of the electric field exchange momentum with metal ions, resulting in diffusion-dominated mass transport of the metal ions, a phenomenon known as electromigration. Electromigration is an important metal failure mechanism in the interconnect structure of semiconductor devices. There are two types of failures caused by electromigration, namely open and short circuit of the interconnect. Along with electromigration of Cu ions, atomic loss occurs near a cathode, local tension is gradually increased, and after a critical value is reached, a cavity is formed, so that resistance is increased, and finally, an interconnection line is opened. In the anode atom accumulation region, the local pressure is increased continuously, so that there may be metal protrusion in this region, which may cause a short circuit of the interconnection line if the protruding metal is in contact with the metal interconnection adjacent to it.
Electromigration may have multiple diffusion paths such as surface, interface, grain boundary diffusion, lattice diffusion. Recent studies show that electromigration is mainly caused by diffusion at a Cu/dielectric cap layer interface and a Cu/barrier layer interface, and the Cu/dielectric cap layer interface is the most main diffusion path of electromigration, so that the Cu/dielectric cap layer interface is crucial to control the corresponding electrical property and reliability performance, and the electromigration characteristics can be improved by improving the interface performance to inhibit the diffusion phenomenon at the Cu/dielectric cap layer interface. Various interface processing techniques are widely used and studied as methods to improve the Cu/dielectric capping layer interface.
however, in the process of forming the Cu/dielectric cap interface according to the prior art, the problems of Cu/dielectric cap interface interaction, penetration, adhesion, etc. still need to be solved and improved in production practice.
Therefore, in view of the above problems, the present invention provides a new semiconductor device and a method for fabricating the same.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device.
The method comprises the following steps:
providing a semiconductor substrate;
Forming a low-k dielectric layer and a copper interconnection structure in the low-k dielectric layer on the semiconductor substrate;
Depositing a layer of diblock copolymer material on the surface of the copper interconnect structure and the low-k dielectric layer;
Carrying out self-assembly treatment on the diblock copolymer material layer to form a first monomer and a second monomer which are arranged at intervals;
removing the first monomer to form a plurality of openings between the second monomer;
Partially etching the copper interconnection structure by taking the second monomer as a mask so as to form a plurality of grooves on the surface of the copper interconnection structure;
removing the second monomer;
Depositing an amorphous silicon layer on the surface of the copper interconnection structure and the low-k dielectric layer;
Performing heat treatment to form a copper silicon covering layer on the surface of the copper interconnection structure;
nitriding the copper silicon covering layer to form a copper silicon nitrogen covering layer;
Further, the method also comprises the steps of carrying out Chemical Mechanical Polishing (CMP) on the surface of the copper interconnection structure and treating the surface of the copper interconnection structure by using nitrogen or ammonia gas to remove copper oxide on the surface of the copper interconnection structure before depositing the diblock copolymer material layer on the surfaces of the copper interconnection structure and the low-k dielectric layer.
Further, the diblock copolymer material layer comprises polystyrene-polymethylmethacrylate block copolymer (PS-b-PMMA).
Further, the diblock copolymer material layer is deposited by spin coating.
Further, the first monomer includes Polymethylmethacrylate (PMMA) and the second monomer includes Polystyrene (PS).
further, the first monomer is selectively removed.
Further, the self-assembly treatment comprises solvent fumigation or annealing treatment.
Further, the first monomer is selectively removed by irradiation with ultraviolet light and acetic acid.
Further, the second monomer is used as a mask, and HNO is utilized3、H2SO4+O2Or HCL + O2Partially etching the copper interconnecta connecting structure surface.
further, the second monomer is removed by plasma etching, the plasma etching including O2、Ar/O2、CF4and CHF3/O2。
Further, the amorphous silicon layer is formed by an atomic layer deposition method.
Further, the nitriding treatment includes a nitrogen gas or ammonia gas treatment. .
further, the nitridation treatment forms a silicon nitride layer on the low-k dielectric layer at the same time as the copper silicon nitrogen covering layer is formed.
Further, the method also comprises the step of forming a dielectric covering layer on the copper-silicon-nitrogen covering layer.
Further, the dielectric capping layer comprises silicon nitride or carbon-doped silicon nitride. .
In summary, according to the method of the present invention, the surface of the copper interconnect structure is etched by using the diblock copolymer self-assembly process, so that a plurality of grooves are formed on the surface of the copper interconnect structure, and then a copper silicon nitrogen capping layer is formed on the surface of the copper interconnect structure, so as to improve the electromigration characteristics, and further improve the reliability and yield of the device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1D are schematic cross-sectional views of a device obtained in accordance with the related steps of a prior art method of fabricating a structure having a Cu/dielectric cap interface;
FIG. 2 is a process flow diagram for fabricating a structure with a Cu/dielectric cap interface in accordance with one embodiment of the present invention;
FIGS. 3A-3G are schematic cross-sectional views of a device resulting from steps associated with fabricating a structure having a Cu/dielectric cap interface in accordance with one embodiment of the present invention;
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
in order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
fig. 1A-1D are schematic diagrams of a device obtained by the related steps of a conventional structure for forming a Cu/dielectric capping layer interface.
as shown in fig. 1A, a semiconductor substrate 100 is provided, on which an etch stop layer 101 and an interlayer dielectric layer 102 are formed in this order from bottom to top. Forming a copper interconnection structure 103 in the interlayer dielectric layer, and treating the copper interconnection structure 103 by using nitrogen or ammonia gas to remove copper oxide on the surface of the copper interconnection structure.
As shown in fig. 1B, an amorphous silicon layer is deposited on the surface of the copper interconnect structure and the interlayer dielectric layer, and a copper-silicon capping layer 104 is formed on the surface of the copper interconnect structure by performing a thermal treatment.
As shown in fig. 1C, the copper silicon nitride capping layer 104 is treated with nitrogen gas or ammonia gas to form a copper silicon nitride capping layer 105.
As shown in fig. 1D, a dielectric cap layer 106 is formed on the cu-si-n cap layer surface.
However, in the process of forming the Cu/dielectric cap interface according to the prior art, the problems of Cu/dielectric cap interface interaction, penetration, adhesion, etc. still need to be solved and improved in production practice.
In view of the above technical problem, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 2, the method comprising the steps of:
Providing a semiconductor substrate;
forming a low-k dielectric layer and a copper interconnection structure in the low-k dielectric layer on the semiconductor substrate;
Depositing a layer of diblock copolymer material on the surface of the copper interconnect structure and the low-k dielectric layer;
Carrying out self-assembly treatment on the diblock copolymer material layer to form a first monomer and a second monomer which are arranged at intervals;
Removing the first monomer to form a plurality of openings between the second monomer;
Partially etching the copper interconnection structure by taking the second monomer as a mask so as to form a plurality of grooves on the surface of the copper interconnection structure;
Removing the second monomer;
Depositing to form an amorphous silicon layer on the surfaces of the copper interconnection structure and the low-k dielectric layer;
Performing heat treatment to form a copper silicon covering layer on the surface of the copper interconnection structure;
And nitriding the copper silicon covering layer to form a copper silicon nitrogen covering layer.
the diblock copolymer material layer comprises polystyrene-polymethacryleneMethyl ester block copolymer (PS-b-PMMA). Depositing the layer of diblock copolymer material by spin coating. The first monomer includes Polymethylmethacrylate (PMMA) and the second monomer includes Polystyrene (PS). The first monomer is selectively removed. The self-assembly treatment comprises solvent fumigation or annealing treatment. The first monomer is selectively removed using ultraviolet light irradiation and acetic acid. Removing the second monomer by plasma etching, the plasma etching including O2、Ar/O2、CF4And CHF3/O2。
the surface of the copper interconnection structure is etched by utilizing the self-assembly treatment of the diblock copolymer, so that a plurality of grooves are formed on the surface of the structure, and then a copper silicon nitrogen covering layer is formed on the surface of the copper interconnection structure, so that the electromigration characteristic is improved, and the reliability and the yield of devices are improved.
[ example one ]
The detailed steps of forming a Cu/dielectric cap interface on a structure according to a method of an exemplary embodiment of the present invention are described below with reference to fig. 3A-3F.
First, as shown in fig. 3A, a semiconductor substrate 300 is provided, wherein the semiconductor substrate 300 may comprise any semiconductor material, such as but not limited to: si, SiC, SiGe, SiGeC, Ge alloys, GeAs, InAs, InP, and other III-V or II-VI compound semiconductors. The semiconductor substrate 300 includes various isolation structures, such as shallow trench isolation. The semiconductor substrate 300 may also include an organic semiconductor or a layered semiconductor such as Si/SiGe, silicon-on-insulator (SOI), or SiGe-on-insulator (sgoi).
An etch stop layer 301 is deposited on the semiconductor substrate 300, and is made of carbon-containing silicon Nitride (NDC) by a Chemical Vapor Deposition (CVD). As an example, in the chemical vapor deposition, the power is 200-400W, the temperature in the cavity is heated to 300-400 ℃, the pressure in the cavity is 2-5 Torr, the gas flow of trimethylsilane (3MS) or tetramethylsilane (4MS) is 100-200 cubic centimeters per minute (sccm), the gas flow of He is 350-450 cubic centimeters per minute (sccm)(sccm)，NH3The gas flow rate is 300-500 cubic centimeters per minute (sccm), and the deposition time lasts 3 s.
then, an interlayer dielectric layer 302 is deposited on the etch stop layer 301, wherein the material of the interlayer dielectric layer 302 may be a low-k dielectric material (formed as a low-k dielectric layer) or an ultra-low-k dielectric material (formed as an ultra-low-k dielectric layer). In general, a low-k dielectric material refers to a dielectric material having a dielectric constant (k value) of less than 4, and an ultra-low-k dielectric material refers to a dielectric material having a dielectric constant (k value) of less than 2. Typically, the material is silicon glass (FSG), silicon oxide (silicon oxide), carbon-containing material, porous material (pore-like material) or the like. As an example, the inter-layer dielectric layer 302 is a low-k dielectric material that is a porous material containing a porogen, which may be any suitable pore-generating material, which may be a hydrocarbon, a polymer containing the acrylate family of resists, a fluorinated polymer, or the like. Curing may be performed in a furnace or by other processes, such as ultraviolet curing, rapid thermal curing, flash lamp curing, laser curing, and the like.
the interlayer dielectric layer 302 and the etch stop layer 301 are etched to expose the semiconductor substrate 300, forming a trench. A diffusion barrier layer (not shown) and a copper metal layer are sequentially formed in the trench, wherein the diffusion barrier layer is formed by Physical Vapor Deposition (PVD), and the diffusion barrier layer is formed at a temperature between-40 ℃ and 400 ℃ and a pressure between about 0.1 mTorr and 100 mTorr. The diffusion barrier layer is made of metal or metal compound layer such as tantalum, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, alloy thereof or composition thereof. In addition, the diffusion barrier layer may also include multiple layers. Preferably, a cobalt (Co) enhancement layer (not shown) is formed on the diffusion barrier layer, and then a copper seed layer (not shown) is formed. The cobalt enhancement layer can improve electromigration resistance while effectively enhancing copper fill capability in smaller geometry trenches/structures. On the copper seed layerthe copper metal layer is formed by electrochemical plating, and a stable plating process can be maintained by the instant analysis of the water bath components and supplies of organic matters and inorganic matters, wherein the gap filling of 0.07 um-0.1 um can be completed by the optimized copper plating chemical additive and current waveform. Then, a Chemical Mechanical Polishing (CMP) process is used to treat the copper metal layer to remove the excess copper metal layer until the interlayer dielectric layer 302 is exposed, and the CMP is stopped when the copper metal layer 303 is flush with the top of the interlayer dielectric layer 302. The surface of copper metal layer 303 is oxidized to form copper oxide due to air oxidation. Using ammonia (NH)3) Or nitrogen plasma is used for treating the copper metal layer 303, and the introduced ammonia gas reduces copper oxide in the interconnection structure, so that the copper oxide in the interconnection structure is finally removed. As an example, ammonia (NH) is used3) The copper metal layer is processed by plasma, the flow rate of the gas is 200-300 cubic centimeters per minute (sccm), the pressure in the reaction chamber can be 5-10 millitorr (mTorr), the power is 900W-1100W, and the processing time of the plasma is 5 s-10 s.
Next, as shown in fig. 3B, a diblock copolymer material layer 304 is deposited on the surfaces of the copper interconnect structure 303 and the low-k dielectric layer; the diblock copolymer comprises a polystyrene-polymethylmethacrylate block copolymer (PS-b-PMMA). As an example, the layer of diblock copolymer material was deposited by a spin-coating method at a spin-coating speed of 3000r/min for a spin-coating time of 30 s.
Next, as shown in fig. 3C, the diblock copolymer material layer is self-assembled to form a first monomer and a second monomer disposed apart from each other, and the first monomer is selectively removed to form a plurality of openings between the second monomers. The self-assembly treatment comprises solvent fumigation or annealing treatment. The first monomer includes Polymethylmethacrylate (PMMA), the second monomer includes Polystyrene (PS), and the first monomer is selectively removed using ultraviolet light irradiation and acetic acid. As an example, the layer of diblock copolymer material was annealed at 190 ℃ for 4 hours, irradiated with UV light for 30 minutes, and then washed with acetic acid for 30 seconds to remove the first monomer PMMA.
Next, as shown in fig. 3D,Partially etching the copper interconnection structure by taking the second monomer as a mask so as to form a plurality of grooves on the surface of the copper interconnection structure; the second monomer 305 is removed. Using HNO3、H2SO4+O2or HCL + O2and etching the surface of the copper interconnection structure. Removing the second monomer by plasma etching, the plasma etching including O2、Ar/O2、CF4And CHF3/O2. As an example, dilute nitric acid is used to etch the copper interconnect structure surface; and removing the second monomer PS by adopting oxygen/argon mixed gas plasma etching, wherein the proportion of the oxygen content in the mixed gas is 2-3%, the treatment power is 3.6W, and the treatment time is 2 min.
Next, as shown in fig. 3E, an amorphous silicon layer is deposited on the surface of the copper interconnect structure and the low-k dielectric layer, and a thermal treatment is performed to form a copper-silicon capping layer 306 on the surface of the copper interconnect structure. The amorphous silicon layer may be formed by any technique known to those skilled in the art, such as atomic layer deposition, low pressure plasma chemical vapor deposition, or plasma enhanced chemical vapor deposition. As an example, the amorphous silicon layer is formed by an atomic layer deposition method, and the heat treatment temperature is 300-400 ℃. Optionally, the thickness of the amorphous silicon layer is 30-60 angstroms.
next, as shown in FIG. 3F, the copper silicon cap layer 306 is nitrided to form a copper silicon nitride cap layer 307. The nitrogen or ammonia gas is decomposed by the plasma and reacts with the copper-silicon capping layer 306 to finally generate the copper-silicon-nitrogen capping layer 307. As an example, the flow rate of the introduced ammonia gas is 50 cubic centimeters per minute (sccm) to 150 cubic centimeters per minute (sccm), and the power used for the plasma decomposition is 100W to 200W.
as shown in fig. 3G, a dielectric cap layer 308 is formed on the surface of the copper silicon nitride cap layer 307. The material of dielectric cap layer 308 comprises carbon-doped silicon nitride or silicon nitride, preferably a silicon nitride material. Which can prevent copper from diffusing into the surrounding low-k interlayer dielectric layer, the adhesion, physical properties and electrical properties of the dielectric capping layer are very important for the airtightness, internal stress, elastic modulus, etc. of the underlying low-k interlayer dielectric layer and metal layer and for reliability. As an example, the dielectric capping layer has a compressive stress with a thickness in the range of 100 angstroms to 500 angstroms.
In summary, according to the method for forming the Cu/dielectric capping layer interface provided by the present invention, the dual-block copolymer self-assembly process is used to etch the upper surface of the copper interconnection structure, so as to form a plurality of grooves on the upper surface of the structure, and then the copper silicon nitrogen capping layer is formed on the surface of the structure, which can improve the adhesion strength of the Cu/dielectric capping layer interface, improve the electromigration characteristics, and further improve the reliability and yield of the device.
[ example two ]
The structure of the semiconductor device provided by the embodiment of the invention is described below with reference to fig. 3G.
As shown in fig. 3G, the structure of the semiconductor device provided by the present invention includes a semiconductor substrate 300; an etching stop layer 301 and an interlayer dielectric layer 302 sequentially formed on the semiconductor substrate 300, wherein a copper interconnection structure 303 is formed in the interlayer dielectric layer 302, and a plurality of grooves are formed at the top of the copper interconnection structure 303; a copper silicon nitride capping layer 307 overlying the interlevel dielectric layer 302 and the copper interconnect structure 303, and a dielectric capping layer 308 formed over the copper silicon nitride capping layer 307.
the semiconductor device can be manufactured by the method for manufacturing a semiconductor device according to the first embodiment. As one example, the semiconductor substrate 300 may comprise any semiconductor material, which may include, but is not limited to: si, SiC, SiGe, SiGeC, Ge alloys, GeAs, InAs, InP, and other III-V or II-VI compound semiconductors. The semiconductor substrate 300 includes various isolation structures, such as shallow trench isolation. The semiconductor substrate 300 may also include an organic semiconductor or a layered semiconductor such as Si/SiGe, silicon-on-insulator (SOI), or SiGe-on-insulator (sgoi). The material of the interlayer dielectric layer 302 may be a low-k dielectric material (formed as a low-k dielectric layer) or an ultra-low-k dielectric material (formed as an ultra-low-k dielectric layer). The dielectric cap layer comprises silicon nitride or carbon-doped silicon nitride.
According to the structure of the semiconductor device provided by the embodiment of the invention, the plurality of grooves are formed on the surface of the copper interconnection structure, and then the copper-silicon-nitrogen covering layer is formed on the upper surface of the copper interconnection structure, so that the adhesion fastness of the Cu/dielectric covering layer interface can be improved, the electromigration characteristic is improved, and the reliability and the yield of the device are further improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (16)
1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
Providing a semiconductor substrate;
Forming a low-k dielectric layer and a copper interconnection structure in the low-k dielectric layer on the semiconductor substrate;
Depositing a layer of diblock copolymer material on the surface of the copper interconnect structure and the low-k dielectric layer;
Carrying out self-assembly treatment on the diblock copolymer material layer to form a first monomer and a second monomer which are arranged at intervals;
removing the first monomer to form a plurality of openings between the second monomer;
partially etching the copper interconnection structure by taking the second monomer as a mask so as to form a plurality of grooves on the surface of the copper interconnection structure;
Removing the second monomer;
depositing an amorphous silicon layer on the surface of the copper interconnection structure and the low-k dielectric layer;
performing heat treatment to form a copper silicon covering layer on the surface of the copper interconnection structure;
and nitriding the copper silicon covering layer to form a copper silicon nitrogen covering layer.
2. The method of claim 1, further comprising the steps of chemical mechanical polishing the surface of the copper interconnect structure and treating the surface of the copper interconnect structure with nitrogen or ammonia to remove copper oxide from the surface of the copper interconnect structure prior to depositing the layer of diblock copolymer material on the surface of the copper interconnect structure and the low-k dielectric layer.
3. the method of claim 1, wherein the layer of diblock copolymer material comprises a polystyrene-polymethylmethacrylate block copolymer.
4. The method of claim 1, wherein the layer of diblock copolymer material is deposited by spin coating.
5. The method of claim 1, wherein the first monomer comprises polymethylmethacrylate and the second monomer comprises polystyrene.
6. The method of claim 1, wherein the first monomer is selectively removed.
7. The method of claim 1, wherein the self-assembly process comprises a solvent fumigation or annealing process.
8. The method of claim 1, wherein the first monomer is selectively removed using ultraviolet light irradiation and acetic acid.
9. The method of claim 1, wherein HNO is utilized with the second monomer as a mask3、H2SO4+O2or HCL + O2Partially etching the copper interconnect structure surface.
10. The method of claim 1, wherein the second monomer is removed by plasma etching.
11. The method of claim 1, wherein the amorphous silicon layer is formed using atomic layer deposition.
12. The method of claim 1, wherein the nitriding process comprises a nitrogen or ammonia gas process.
13. The method of claim 1, wherein the nitridation process forms a silicon nitride layer on the low-k dielectric layer simultaneously with the formation of the copper silicon nitrogen capping layer.
14. The method of claim 1, further comprising the step of forming a dielectric cap layer on the copper-silicon-nitrogen cap layer.
15. The method of claim 14, wherein the dielectric cap layer comprises silicon nitride or carbon-doped silicon nitride.
16. A semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 1 to 15, comprising:
A semiconductor substrate;
A low-k dielectric layer formed on the semiconductor substrate and a copper interconnect structure located in the low-k dielectric layer;
And forming a copper silicon nitrogen covering layer on the surface of the copper interconnection structure.
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| US7361991B2 (en) * | 2003-09-19 | 2008-04-22 | International Business Machines Corporation | Closed air gap interconnect structure |
| CN104835777A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
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