CN102422397A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN102422397A
CN102422397A CN2009801591805A CN200980159180A CN102422397A CN 102422397 A CN102422397 A CN 102422397A CN 2009801591805 A CN2009801591805 A CN 2009801591805A CN 200980159180 A CN200980159180 A CN 200980159180A CN 102422397 A CN102422397 A CN 102422397A
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electrode
barrier layer
layer
electrode body
sample
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CN102422397B (zh
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宫崎富仁
木山诚
堀井拓
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Abstract

一种半导体器件，提供有：包括GaN的半导体层(1)以及电极。该电极包括：电极主体(6)；连接用电极(8)，其在从半导体层(1)观看时形成在比电极主体(6)更远的位置处并且包括Al；以及阻挡层(7)，其形成在电极主体(6)和连接用电极(8)之间，并且包括选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料。阻挡层(7)的表面粗糙度RMS为3.0nm或更小。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，并且更具体地，涉及一种包括包含GaN(氮化镓)的半导体层的半导体器件及其制造方法。
背景技术
由于GaN在紫外区具有带隙，所以已经促进了应用GaN作为用于光学器件的材料，例如产生诸如蓝光或紫外光的短波长光的激光器件。在这种使用GaN的光学器件中，具有低电阻的Au(金)已被用作用于连接到外部布线线路(例如，引线)的焊盘电极的材料。
由于GaN具有宽带隙、高载流子迁移率和高临界电场，所以近年来越来越多尝试将GaN不仅用于发光器件而且还用于肖特基势垒二极管(SBD)和晶体管的功率半导体器件。在这种使用GaN的功率半导体器件中，因为需要使大电流流过，所以通常使用具有200μm以上的大直径且由Al(铝)构成的布线线路(引线)来提供功率半导体器件和外部器件之间的连接。
例如，日本未审查专利申请公布No.2006-196764(PTL 1)，F.Renet al.，“Wide Energy Bandgap Electronic Devices”，World Scientific，2003，p.152-155(NPL 1)和H.Otake et al.，″Vertical GaN-Based TrenchGate Metal Oxide Semiconductor Field-Effect Transistors on GaN BulkSubstrates″，Appl.Phys.Express.，1(2008)011105(NPL 2)公开了利用GaN的常规功率半导体器件的结构。PTL 1公开了：由TixW1-xN(0＜x＜1＝构成的扩散阻挡层被设置在低电阻金属层和Ni层之间，Ni层与GaN构成的化合物半导体层进行肖特基接触。NPL 1公开了：形成在GaN衬底上的GaN肖特基势垒二极管。在该肖特基势垒二极管中，肖特基电极由Pt/Ti/Au构成。NPL 2公开了：形成在GaN衬底上的GaN基垂直MOSFET(金属氧化物半导体场效应晶体管)。在该MOSFET中，栅电极由Ni(镍)/Au构成。
引用目录
专利文献
PTL 1：日本未审查专利申请公布No.2006-196764
非专利文献
NPL 1：F.Ren et al.，“Wide Energy Bandgap Electronic Devices”，World Scientific，2003，p.152-155
NPL 2：H.Otake et al.，″Vertical GaN-Based Trench Gate MetalOxide Semiconductor Field-Effect Transistors on GaN Bulk Substrates″，Appl.Phys.Express.，1(2008)011105
发明内容
技术问题
在GaN基功率半导体器件中的焊盘电极像前文一样由Au构成的情况下，由于引线结合到焊盘电极时产生的热和驱动器件时产生的热，在组成焊盘电极的Au和包含在引线中的Al之间形成合金。因此，会劣化焊盘电极的质量。此外，在功率半导体器件中，焊盘电极需要具有特定的厚度，这可以耐受在安装厚Al引线时造成的破坏。使用Au作为用于焊盘电极的材料增加了成本。因此，在GaN基功率器件中，作为与引线材料相同的材料的Al用作焊盘电极的材料。
然而，当包含Al的焊盘电极(连接用电极)用于诸如SBD和垂直MOSFET的GaN基功率器件时，存在问题：由于安装或操作器件时产生的热而导致这种器件的特性劣化。
因而，本发明的目的是提供一种可以有效地抑制特性劣化的半导体器件以及制造这种半导体器件的方法。
要解决的问题
本发明的半导体器件包括包含GaN的半导体层和电极。所述电极包括：电极主体；连接用电极，其包含Al并且形成在相比于电极主体距离半导体层更远的位置处；以及阻挡层，其形成在电极主体和连接用电极之间，所述阻挡层包含选自由W(钨)、TiW(钨化钛)、WN(氮化钨)、TiN(氮化钛)、Ta(钽)和TaN(氮化钽)组成的组中的至少一种材料。阻挡层的表面粗糙度RMS为3.0nm或更小。
本发明的发明人已经发现：由于加热而使在连接用电极中包含的Al扩散到半导体层中，所以包括包含Al的连接用电极的半导体器件性能劣化。此外，本发明人还发现：通过将阻挡层的表面粗糙度控制为3.0nm或更小，可以有效地抑制在阻挡层上形成的连接用电极中包含的Al的扩散。因此，在本发明中，在半导体层和连接用电极之间形成包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料的阻挡层，以便具有3.0nm或更小的表面粗糙度，由此抑制了包含在连接用电极中的Al的扩散，并因此可以有效地抑制特性的劣化。
在本发明的半导体器件中，电极主体优选地与半导体层进行肖特基接触。这可以对半导体器件增加SBD功能，并可以实现高性能SBD。
在本发明的半导体器件中，阻挡层优选地具有
Figure BDA0000106426950000031
(0.3μm)或更大的厚度。
本发明人已经发现：通过控制阻挡层的厚度为
Figure BDA0000106426950000032
或更大，可以有效地抑制泄漏电流增加。由此，可以更有效地抑制特性劣化。
根据本发明一方面的制造半导体器件的方法包括如下步骤。形成包含GaN的半导体层并且形成电极。形成电极的步骤包括如下步骤。形成电极主体。在相比于电极主体距离半导体层更远的位置处形成包含Al的连接用电极。在电极主体和连接用电极之间形成包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料的阻挡层。在形成阻挡层的步骤中，在0.1Pa或更小的环境压力且施加300W或更大的电力的条件下，通过溅射方法来形成阻挡层。
根据本发明另一方面的制造半导体器件的方法包括如下步骤。形成包含GaN的半导体层并且形成电极。形成电极的步骤包括如下步骤。形成电极主体。在相比于电极主体距离半导体层更远的位置处形成包含Al的连接用电极。在电极主体和连接用电极之间形成包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料的阻挡层。在形成阻挡层的步骤中，在135℃以上加热电极主体的同时在0.1Pa或更小的环境压力下通过溅射方法来形成阻挡层。
作为对制造本发明的半导体器件进行深入研究的结果，本发明人发现：通过将环境压力和施加的电力控制在上述范围内，或通过将环境压力和加热温度控制在上述范围内，可以形成具有的表面粗糙度RMS为3.0nm或更小的阻挡层。因此，在本发明中，可以在半导体层和连接用电极之间形成包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料的阻挡层，以便具有3.0nm或更小的表面粗糙度。从而，抑制了在连接用电极中包含的Al的扩散，并由此可以有效地抑制特性的劣化。
发明的有益效果
根据本发明的半导体器件和制造半导体器件的方法，可以抑制特性劣化。
附图说明
图1是示意性示出根据本发明第一实施例的半导体器件的结构的截面图。
图2是示意性示出根据本发明第二实施例的半导体器件的结构的截面图。
图3是示出本发明实例1的样品1中作为反向电压函数的电流密度的变化的示意图。
图4是示出本发明实例1的样品2中作为反向电压函数的电流密度的变化的示意图。
图5是示出本发明实例1的样品3中作为反向电压函数的电流密度的变化的示意图。
图6是示出本发明实例1的样品4中作为反向电压函数的电流密度的变化的示意图。
图7是示出本发明实例1的样品5和6中作为反向电压函数的电流密度的变化的示意图。
具体实施方式
现在将参考附图来描述本发明的实施例。
(第一实施例)
图1是示意性示出根据本发明第一实施例的半导体器件的结构的截面图。参考图1，用作根据本实施例的半导体器件的SBD 100包括半导体层1、用作电极的肖特基电极2和欧姆电极3。肖特基电极2形成在半导体层1的上表面侧上，并且欧姆电极3形成在半导体层1的下表面侧上。
半导体层1包括衬底4和在衬底4上形成的漂移层5。衬底4和漂移层5包含GaN，并且例如由n型GaN构成。漂移层5的n型杂质浓度比衬底4的n型杂质浓度低。
肖特基电极2包括电极主体6、阻挡层7和连接用电极(焊盘电极)8。电极主体6与漂移层5接触，并且与漂移层5形成肖特基势垒。电极主体6例如由Ni/Au堆叠膜，也就是，与漂移层5肖特基接触的Ni层和在Ni层上形成的Au层组成。阻挡层7形成在电极主体6上，并且连接用电极8形成在阻挡层7上。连接用电极8是直接连接用于将外部器件与SBD100的肖特基电极电连接的布线线路(例如，由Al构成的引线)的电极。连接用电极8包含Al并且例如由Al构成。阻挡层7抑制了在连接用电极8中包含的Al扩散到半导体层1中，扩散是由加热造成的。阻挡层7包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料。阻挡层7例如由W、TiW、WN、TiN、Ta和TaN组成。
阻挡层7的表面7a的表面粗糙度RMS为3.0nm或更小，优选为2.0nm或更小，且更优选为1.4nm或更小。当表面粗糙度RMS为3.0nm或更小时，可以有效地抑制在阻挡层7上形成的连接用电极8中包含的Al的扩散。当表面粗糙度RMS为2.0nm或更小时，可以更有效地抑制在连接用电极8中包含的Al的扩散。当表面粗糙度RMS为1.4nm或更小时，可以最有效地抑制在连接用电极8中包含的Al的扩散。这里，阻挡层7的表面7a的表面粗糙度RMS优选尽可能小，但是考虑到制造工艺，其下限例如是1nm。
表面粗糙度RMS指的是在JIS B0601中规定的表面的均方根粗糙度，也就是，离测量表面的平均表面的距离(偏差)的均方根值。
阻挡层7优选地具有
Figure BDA0000106426950000061
或更大的厚度。在这种情况下，可以抑制泄漏电流增加。
欧姆电极3由与衬底4欧姆接触的材料构成，且例如由Ti/Al/Ti/Au堆叠膜组成。
在该SBD 100中，当在肖特基电极2和欧姆电极3之间施加超过在电极主体6和漂移层5之间形成的肖特基势垒的电压时，电流在与衬底4的主表面相垂直的方向(图中的垂直方向)上，从肖特基电极2通过半导体层1向欧姆电极3流动。
现在将描述制造根据本实施例的SBD 100的方法。首先，在衬底4上形成漂移层5。由此，可以形成半导体层1。随后，在漂移层5的上表面上形成肖特基电极2，且在衬底4的下表面上形成欧姆电极3。在形成肖特基电极2时，在漂移层5的上表面上形成电极主体6，在电极主体6上形成阻挡层7，然后在阻挡层7上形成连接用电极8。例如通过溅射方法来形成阻挡层7。
在形成阻挡层7的步骤中，在0.1Pa或更小的环境压力且施加300W或更大的电力(溅射功率)的条件下，通过溅射方法来形成阻挡层7。可替选地，在形成阻挡层7的步骤中，在135℃以上加热电极主体6的同时，在0.1Pa或更小的环境压力下，通过溅射方法来形成阻挡层7。优选地，在形成阻挡层7的步骤中，在135℃以上加热电极主体6的同时，在0.1Pa或更小的环境压力下且施加300W或更大的电力(溅射功率)的条件下，通过溅射方法来形成阻挡层7。
这里，上面描述的温度指的是为了形成阻挡层7将要溅射的目标设置在溅射设备中并用热电偶来测量电极主体6的表面时获得的温度。例如，通过将溅射设备中加热器的温度设定为250℃以上，可以将电极主体6加热到135℃以上。在该温度测量中，优选使用包含磁炉的RF溅射设备作为溅射设备。加热温度的上限例如为450℃，以抑制电极主体6的肖特基特性劣化。
在形成阻挡层7的步骤中加热电极主体6的情况下，加热时间例如大约为一小时。
如上所述，根据本实施例的SBD 100包括包含GaN的半导体层1和肖特基电极2。肖特基电极2包括：电极主体6；连接用电极8，其包含Al且形成在相比于电极主体6距离半导体层1更远的位置处；以及阻挡层7，其形成在电极主体6和连接用电极8之间。阻挡层7的表面粗糙度RMS为3.0nm或更小。
制造根据本实施例的SBD 100的方法包括下面的步骤。形成包含GaN的半导体层1以及形成肖特基电极2。形成肖特基电极2的步骤包括如下步骤。形成电极主体6。在相比于电极主体6距离半导体层1更远的位置处形成包含Al的连接用电极8。在电极主体6和连接用电极8之间形成阻挡层7。在形成阻挡层7的步骤中，在0.1Pa或更小的环境压力下且施加300W或更大的电力的条件下，通过溅射方法来形成阻挡层7。可替选地，在形成阻挡层7的步骤中，在135℃以上加热肖特基电极2的同时在0.1Pa或更小的环境压力下通过溅射方法来形成阻挡层7。
根据本实施例中的SBD 100和制造SBD 100的方法，即使由于在安装期间(例如，管芯结合期间)产生的热或者在驱动SBD 100时产生的热而加热连接用电极8，通过阻挡层7也防止在连接用电极8中包含的Al的扩散，这可以抑制Al进入到肖特基接触界面中。具体地，当阻挡层7的表面粗糙度RMS为3.0nm或更小时，可以抑制组成在阻挡层7上形成的连接用电极8的Al的晶界的尺寸增加。由此，可以抑制组成连接用电极8的Al以尖峰方式穿透阻挡层7，并且可以抑制Al扩散到肖特基电极2中。结果，在安装之后，可以抑制由自加热等造成的SBD 100的性能劣化。
第二实施例
图2是示意性示出根据本发明第二实施例的半导体器件的结构的截面图。参考图2，用作本实施例的半导体器件的垂直n沟道MOSFET101包括半导体层11和每个均用作电极的栅电极12、源电极13和漏电极14。沟槽11a形成在半导体层11的上表面上。栅电极12形成在沟槽11a的内表面上以及沟槽11a附近的半导体层11的上表面上，栅极绝缘层19位于它们之间。此外，源电极13形成在半导体层11的上表面的没有形成沟槽11a和栅极绝缘层19的部分上。漏电极14形成在半导体层11的下表面上。
半导体层11包括衬底15、n型漂移层16、p型主体层17和n型层18。n型漂移层16形成在衬底15上，p型主体层17形成在n型漂移层16上，并且n型层18形成在p型主体层17上。沟槽11a穿透n型层18和p型主体层17，并且到达n型漂移层16。衬底15、n型漂移层16、p型主体层17和n型层18中的每个包含GaN，并且例如由GaN构成。n型漂移层16的n型杂质浓度低于衬底15和n型层18的杂质浓度。
栅电极12包括电极主体6、阻挡层7和连接用电极(焊盘电极)8。电极主体6形成在栅极绝缘层19上，阻挡层7形成在电极主体6上，并且连接用电极8形成在阻挡层7上。连接用电极8是直接连接用于将外部器件与MOSFET 101的栅电极12电连接的布线线路的电极。电极主体6、阻挡层7和连接用电极8的构造与第一实施例中的电极主体、阻挡层和连接用电极的构造相同，并因此省略了它们的描述。
源电极13包括欧姆电极13a和欧姆电极13b。欧姆电极13a被形成为围绕沟槽11a，并且例如由Ti/Al堆叠膜组成。欧姆电极13b被形成为围绕欧姆电极13a，并电连接到p型主体层17和欧姆电极13a。欧姆电极13b例如由Ni/Au堆叠膜组成。漏电极14形成在衬底15的整个下表面上，并且例如由Ti/Al构成。
在MOSFET 101中，当栅电极12和漏电极14具有比源电极13更高的电势时，在通过栅绝缘层19面对栅电极12的p型主体层17中形成沟道，并且电流流过该沟道。结果，在与衬底15的主表面相垂直的方向上(图中的垂直方向)，电流从漏电极14通过半导体层11流到源电极13。
现在将描述根据制造本实施例的MOSFET 101的方法。首先，通过按顺序在衬底15上形成n型漂移层16、p型主体层17和n型层18，来制造半导体层1。然后在半导体层11的上表面上形成沟槽11a，以至达到n型漂移层16。在沟槽11a的内表面上形成栅极绝缘层19，并且在栅极绝缘层19上形成栅电极12。随后，在n型层18上形成欧姆电极13a，并且蚀刻位于欧姆电极13a的***上的n型层18，以暴露p型主体层17。欧姆电极13b被形成为电连接到欧姆电极13a和p型主体层17。欧姆电极13a和欧姆电极13b组成源电极13。然后，在衬底15的下表面上形成漏电极14。
在形成栅电极12中，在栅极绝缘层19上形成电极主体6，在电极主体6上形成阻挡层7，然后在阻挡层7上形成连接用电极8。形成阻挡层7的步骤与第一实施例中的步骤相同，并因此省略了它的描述。
如上所述，根据本实施例的MOSFET 101包括包含GaN的半导体层11和栅电极12。栅电极12包括：电极主体6；连接用电极8，其包含Al且形成在相比于电极主体6距离半导体层11更远的位置处；以及阻挡层7，其形成在电极主体6和连接用电极8之间。阻挡层7的表面粗糙度RMS为3.0nm或更小。
制造根据本实施例的MOSFET 101的方法包括下面的步骤。形成包含GaN的半导体层11并且形成栅电极12。形成栅电极12的步骤包括如下步骤。形成电极主体6。在相比于电极主体6距离半导体层11更远的位置处形成包含Al的连接用电极8。在电极主体6和连接用电极8之间形成阻挡层7。在形成阻挡层7的步骤中，在0.1Pa或更小的环境压力下、在施加300W或更大的电力下，通过溅射方法来形成阻挡层7。可替选地，在135℃或更大处加热电极主体6的同时，在0.1Pa或更小的环境压力下，通过溅射方法来形成阻挡层7。
根据本实施例中的MOSFET 101和制造MOSFET 101的方法，即使由于在安装期间(例如，管芯结合期间)产生的热或者在驱动MOSFET101时产生的热而导致加热连接用电极8，通过阻挡层7，也防止在连接用电极8中包含的Al的扩散，这能够抑制Al进入到MOS界面中。结果，能够抑制由加热造成的MOSFET 101的性能劣化。
在本实施例中，已经描述了使用包含电极主体、阻挡层和连接用电极的电极作为MOSFET的栅电极的情况。然而，本发明的这种电极也可以用作MOSFET的源电极。
此外，在第一和第二实施例中，已经描述了本发明的半导体器件为SBD或垂直MOSFET的情况。然而，本发明的半导体器件例如可以是电容器、横向MOSFET、高电子迁移率晶体管或双极晶体管，以代替上述器件。具体地，本发明的半导体器件优选为垂直器件，也就是，沟道在与衬底的主表面基本垂直的方向上延伸的器件。
实例1
在本实例中，首先，在以下条件下制造用作样品1至6的SBD。
样品1(发明实例)：制造具有图1所示的结构的SBD。具体地，准备由HVPE(氢化物气相外延)制造的GaN独立式衬底。该衬底具有3×1018cm-3的n型杂质浓度、400μm的厚度和1×106/cm2的平均位错密度。随后，通过OMVPE(有机金属气相外延)在衬底的(0001)面上外延生长由GaN构成的且具有5×1015cm-3的n型杂质浓度以及5μm的厚度的漂移层。在利用有机溶剂清洗该衬底之后，在衬底的下表面上形成欧姆电极。作为欧姆电极，通过EB(电子束)蒸发方法，形成由Ti(厚度：20nm)/Al(厚度：100nm)/Ti(厚度：20nm)/Au(厚度：300nm)构成的堆叠膜。随后，在氮气氛中且在600℃下，对欧姆电极进行热处理1分钟。
接下来，在漂移层的上表面上形成肖特基电极。通过电子束蒸发方法来形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；通过利用Ti和W的合金作为目标进行溅射，在电极主体上形成由TiW构成且具有
Figure BDA0000106426950000111
厚度的阻挡层；以及通过溅射Al形成具有3μm厚度的连接用电极，来形成肖特基电极。在形成阻挡层中，利用磁控RF溅射设备作为溅射设备。在没有加热电极主体的情况下，在0.1Pa的环境压力且施加300W的电力的条件下，通过溅射方法来形成阻挡层。根据JISB0601测量的阻挡层的表面粗糙度RMS为2.0nm。
肖特基电极被构图成具有边长1mm的正方形形状。具体地，通过光刻，在连接用电极上对抗蚀剂进行构图，并利用该抗蚀剂作为掩模，用温度为40℃的混合酸蚀刻剂(磷酸+硝酸+醋酸+纯水)来蚀刻Al。随后，用温度为室温的氨蚀刻剂(氨水+过氧化氢溶液+纯水)蚀刻阻挡层。通过ICP(感应耦合等离子体)分析来测量在蚀刻之后的阻挡层中Ti的含量。Ti的质量百分比含量为8％。紧接在蒸发欧姆电极和肖特基电极之前，利用温度为室温的盐酸水溶液(用于半导体的盐酸∶纯水＝1∶10)处理要蒸发的表面3分钟。
样品2(发明实例)：在阻挡层形成方法方面，样品2和样品1不同。具体地，通过电子束蒸发方法形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；在135℃加热电极主体的同时，在0.1Pa的环境压力且施加300W的电力的条件下，通过溅射方法在电极主体上形成阻挡层；以及，然后通过溅射Al在TiW层上形成具有3μm厚度的连接用电极，来形成肖特基电极。阻挡层具有1.4nm的表面粗糙度RMS和
Figure BDA0000106426950000121
的厚度。除了上述方法之外的制造方法与样品1的制造方法相同。
样品3(发明实例)：在阻挡层的形成方法方面，样品3与样品1不同。具体地，通过电子束蒸发方法形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；在135℃加热电极主体的同时，在0.1Pa的环境压力且施加50W的电力的条件下，通过溅射方法在电极主体上形成阻挡层；以及然后通过溅射Al在TiW层上形成具有3μm厚度的连接用电极，来形成肖特基电极。阻挡层具有3.0nm的表面粗糙度RMS和的厚度。除了上述方法之外的制造方法与样品1的制造方法相同。
样品4(比较实例)：在阻挡层的形成方法方面，样品4与样品1不同。具体地，通过电子束蒸发方法形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；在没有加热电极主体的同时，在0.1Pa的环境压力且施加50W的电力的条件下，通过溅射方法在电极主体上形成阻挡层；以及然后通过溅射Al在TiW层上形成具有3μm厚度的连接用电极，来形成肖特基电极。阻挡层具有3.2nm的表面粗糙度RMS和
Figure BDA0000106426950000131
的厚度。除了上述方法之外的制造方法与样品1的制造方法相同。
样品5(比较实例)：样品5和样品1的不同之处在于没有形成阻挡层。具体地，通过电子束蒸发方法形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；以及然后在没有形成阻挡层的情况下，通过溅射Al在电极主体上形成具有3μm厚度的连接用电极，来形成肖特基电极。在对肖特基电极进行构图中，利用温度为40℃的混合酸蚀刻剂(磷酸+硝酸+醋酸+纯水)来蚀刻Al。除了上述方法之外的制造方法与样品1的制造方法相同。
样品6(比较实例)：在阻挡层形成方法方面，样品6与样品1不同。具体地，通过电子束蒸发方法形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；形成具有0.15μm厚度的Ti层；以及然后通过溅射Al在Ti层上形成具有3μm厚度的连接用电极，来形成肖特基电极。在对肖特基电极进行构图中，利用温度为40℃的混合酸蚀刻剂(磷酸+硝酸+醋酸+纯水)来蚀刻Al，且随后利用温度为室温的氨蚀刻剂(氨水+过氧化氢溶液+纯水)来蚀刻Ti层。除了上述方法之外的制造方法与样品1的制造方法相同。
评估样品1至6的热稳定性。具体地，在350℃处热处理(退火)样品1至6，认为该温度为SBD安装(管芯结合)器件的温度。在热处理之前和之后，测量作为反向电压函数的电流密度。图3至7以及表1示出了结果。关于施加350V的反向电压时获得的电流密度，表Ⅰ中的泄漏电流指的是热处理前和热处理后之间电流密度的增加。
[表Ⅰ]
  RMS(nm)   泄漏电流
  样品1   2.0   一个数位的增加
  样品2   1.4   没有增加
  样品3   3.0   一个数位的增加
  样品4   3.2   四个数位的增加
图3至6是示出本发明实例1的样品1至4中的作为反向电压函数的电流密度变化的图。图7是示出本发明实例1的样品15和6中的作为反向电压函数的电流密度变化的图。参考图3至5以及表Ⅰ，在包括具有的表面粗糙度RMS为3.0nm或更小的阻挡层的样品1至3中，没有看到作为反向电压函数的电流密度的显著变化，并因此有效地抑制了由加热造成的特性劣化。具体地，在表面粗糙度为1.4nm或更小的样品2中，高度有效地抑制由加热造成的特性劣化。
另一方面，参考图6和表Ⅰ，在包括具有的表面粗糙度RMS大于3.0nm的阻挡层的样品4中，看到了作为反向电压函数的电流密度的显著变化，并因此看到了由加热造成的特性劣化。此外，参考图7，在不包含本发明的阻挡层的样品5和6中，在热处理后作为反向电压函数的电流密度极大增加，并由此显著看到由加热造成的特性劣化。
根据本实例，发现：通过形成阻挡层，可以抑制特性劣化；以及此外通过将阻挡层的表面粗糙度RMS控制在3.0nm或更小，可以有效地抑制特性劣化。
实例2
在本实例中，研究了形成具有的表面粗糙度RMS为3.0nm或更小的阻挡层的条件。因此，在本实例中，除了样品1至4之外，在下面的条件下制造用作样品7和8的SBD。
样品7(比较实例)：在阻挡层的形成方法方面，样品7与样品1不同。具体地，通过电子束蒸发方法形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；在没有加热电极主体的情况下，在0.5Pa的环境压力且施加300W的电力的条件下，通过溅射方法在电极主体上形成阻挡层；以及然后通过溅射Al在TiW层上形成具有3μm厚度的连接用电极，来形成肖特基电极。阻挡层具有
Figure BDA0000106426950000151
的厚度。除了上述方法之外的制造方法与样品1的制造方法相同。
样品8(比较实例)：在阻挡层的形成方法方面，样品8与样品1不同。具体地，通过电子束蒸发方法来形成由Ni(厚度：50nm)/Au(厚度：300nm)构成的电极主体；在没有加热电极主体的情况下，在1.5Pa的环境压力且施加300W的电力的情况下，通过溅射方法在电极主体上形成阻挡层；以及然后通过溅射Al在TiW层上形成具有3μm厚度的连接用电极，来形成肖特基电极。阻挡层具有
Figure BDA0000106426950000152
的厚度。除了上述方法之外的制造方法与样品1的制造方法相同。
像样品1至4中一样，也根据JIS B0601来测量样品7和8的阻挡层的表面粗糙度RMS。表Ⅱ示出了结果。
[表Ⅱ]
Figure BDA0000106426950000153
如表Ⅱ所示，在样品1和2中，其中在0.1Pa或更小的环境压力且施加300W的电力的条件下，通过溅射方法形成了阻挡层，表面粗糙度RMS为2.0nm或更小。在样品2和3中，其中在135℃以上加热电极主体的同时，在0.1Pa或更小的环境压力下，通过溅射方法形成了阻挡层，表面粗糙度RMS为3.0nm或更小。此外，在样品2中，其中在135℃以上加热电极主体的同时，在0.1Pa或更小的环境压力且施加300W或更大的电力的条件下，通过溅射方法形成了阻挡层，表面粗糙度RMS为1.4nm或更小。
另一方面，在没有满足任一条件的样品4、7和8中，阻挡层具有3.2nm或更大的表面粗糙度RMS。
根据本实例，发现：通过控制诸如环境压力和施加的电力或环境压力和加热温度的溅射条件，阻挡层的表面粗糙度RMS可以减小为3.0nm或更小。
应该理解，上面描述的实施例和实例仅是说明性的，并且不能以任何方式限制本发明的范围。本发明的范围由所附的权利要求来限定，而不是由前面的公开来限定，并且在由所附权利要求及其等效所限定的范围内，包括所有修改和替选。
工业应用性
本发明可适合作为由GaN-基材料构成的功率半导体器件。
附图标记列表
1，11    半导体层
2        肖特基电极
3        欧姆电极
4，15    衬底
5        漂移层
6        电极主体
7        阻挡层
7a       表面
8        连接用电极
11a      沟槽
12       栅电极
13       源电极
13a，13b 欧姆电极
14       漏电极
16       n型漂移层
17       p型主体层
18       n型层
19       栅极绝缘层
100      SBD
101      MOSFET

Claims (5)

1.一种半导体器件，其包括：
半导体层(1，11)，所述半导体层(1，11)包含氮化镓；以及
电极(2，12)，
其中，所述电极(2，12)包括：电极主体(6)；连接用电极(8)，所述连接用电极(8)包含铝且形成在相比于所述电极主体(6)距离所述半导体层(1，11)更远的位置处；以及阻挡层(7)，所述阻挡层(7)形成在所述电极主体(6)和所述连接用电极(8)之间，所述阻挡层(7)包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料，并且，
所述阻挡层(7)的表面粗糙度RMS为3.0nm或更小。
2.根据权利要求1所述的半导体器件，其中，
所述电极主体(6)与所述半导体层(1，11)形成肖特基接触。
3.根据权利要求1所述的半导体器件，其中，所述阻挡层(7)具有
Figure FDA0000106426940000011
或更大的厚度。
4.一种制造半导体器件的方法，其包括：
形成包含氮化镓的半导体层(1，11)的步骤；以及
形成电极(2，12)的步骤；
其中，形成所述电极(2，12)的步骤包括：形成电极主体(6)的步骤、在相比于所述电极主体(6)距离所述半导体层(1，11)更远的位置处形成包含铝的连接用电极(8)的步骤、以及在所述电极主体(6)和所述连接用电极(8)之间形成所述阻挡层(7)的步骤，所述阻挡层(7)包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料，并且，
在形成所述阻挡层(7)的步骤中，在以0.1Pa或更小的环境压力且施加300W或更大的电力的情况下通过溅射方法来形成所述阻挡层(7)。
5.一种制造半导体器件的方法，其包括：
形成包含氮化镓的半导体层(1，11)的步骤；以及
形成电极(2，12)的步骤；
其中，形成电极(2，12)的步骤包括：形成电极主体(6)的步骤、在相比于所述电极主体(6)距离所述半导体层(1，11)更远的位置处形成包含铝的连接用电极(8)的步骤、以及在所述电极主体(6)和所述连接用电极(8)之间形成阻挡层(7)的步骤，所述阻挡层(7)包含选自由W、TiW、WN、TiN、Ta和TaN组成的组中的至少一种材料，并且，
在形成所述阻挡层(7)的步骤中，在135℃或更高的温度下加热所述电极主体(6)的同时在0.1Pa或更小的环境压力下通过溅射方法来形成所述阻挡层(7)。
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