CN102288941B - Intermediate frequency linear frequency modulation-pulse Doppler (LFM-PD) radar signal real-time processing system based on field programmable gate array (FPGA) and digital signal processor (DSP) and processing method - Google Patents

Abstract

The invention discloses an intermediate frequency linear frequency modulation-pulse Doppler (LFM-PD) radar signal real-time processing system based on field programmable gate array (FPGA) and digital signal processor (DSP) and a method for realizing the system. The system consists of an intermediate frequency sampling module, a digital down-conversion module, a pulse compression module, a coherent accumulation module, a motion compensation module and a constant false alarm detection module. A processed radar signal enters the intermediate frequency sampling module at first; the dispersed signal is sent into the digital down-conversion module for digital down-conversion processing; then the signal enters the pulse compression module for pulse compression processing; after the coherent accumulation module accumulates out a result, the signal enters the motion compensation module to calculate the motion compensation quantity; and finally, the coherent accumulation result enters the constant false alarm detection module to detect out an object. The intermediate frequency LFM-PD radar signal real-time processing system based on FPGA and DSP can meet real-time processing requirements, is short in development cycle and strong in flexibility, and is suitable to be applied to large-scale radar detection systems.

Description

A kind of intermediate frequency LFM-PD radar signal real time processing system and disposal route based on FPGA and DSP

Technical field

The present invention relates to a kind of intermediate frequency LFM-PD (linear frequency modulation-coherent) radar signal real time processing system and disposal route based on FPGA and DSP, belong to radar detection technique field.

Background technology

Radar is the main tool of the detection of a target in military and civilian field.When there is relative motion between radar and target, between the frequency of echoed signal and the frequency transmitting, will there is the difference on the frequency that is proportional to relative radial rate, the embodiment of Here it is Doppler effect.The radar that utilizes Doppler effect to carry out target information extraction and processing is called radar Doppler, if radar emission is pulse modulated radiofrequency signal, is referred to as pulse Doppler radar, is called for short PD radar.PD radar is the pulsed radar of a kind of advanced person's of growing up on moving-target indication radar basis full coherent system.And the PD radar that adopts linear frequency modulation (LFM) signal combines the advantage of pulse Doppler system and pulse compression system, feature due to signal wide bandwidth product when large, make the radar can be with broad pulse transmitted waveform, in the situation that not increasing pulse repetition rate, increase the average power of radar, improve the operating distance of radar, when receiving, adopt matched filter to carry out pulse compression, obtain narrow pulse signal, to keep the range resolution of narrow pulse system and the speed resoluting force of doppler system, realize the detection to moving-target in strong clutter environment.In modern PD-pulse compression radar system, the Data Update of target echo signal is very fast, and this just requires radar processor within the extremely short time, to complete the processing to a frame echo data, has the ability of real-time processing, otherwise just may lose.Therefore, intermediate frequency LFM-PD radar real-time processing technique becomes a standard technique of modern radar gradually.

Eighties of last century is since the eighties, and along with the rapid progress of infotech and semiconductor technology, very high speed integrated circuit (VHSIC) and VLSI (very large scale integrated circuit) (VLSI) technology have obtained increasing substantially.The single-chip microcomputer of low speed, low reliability and small-scale integrated circuit more and more can not be satisfied the demand, and are replaced just gradually by programmable logic device (PLD) (as FPGA, CPLD) and DSP.Current Digital Down Convert and process of pulse-compression device have multiple implementation method, and main implementation method comprises that PC software is realized, DSP realizes and FPGA realization.

Hanoverian, Germany university is used 6 HiPAR-DSP 16 and FPGA to realize a REAL TIME SAR IMAGES processor.This processor adopts 6 HiPAR-DSP 16 interconnected, and its processing speed is 28GOPS, can under the repetition of 1200Hz, process in real time 4096 * 4096 8bit plural number FFT, and system has advantages of that handling property is high, low in energy consumption, volume is little.Virginia Polytechnic Institute and State University (Virginia Polytechnic Institute and State University) adopts high speed FPGA, by controlling 8 high-speed ADCs, designed the hypervelocity sampling digital transceiver of speed up to 8G-samples/s, can realize the hypervelocity sampling to UWB pulse, for signal follow-up in UWB system, process with data handling system and lay a good foundation.

In the above-mentioned method that realizes the processing in real time of intermediate frequency LFM-PD radar, utilize PC software to realize Digital Down Convert and pulse compression exploitation simple, but speed can not reach the requirement of real-time processing conventionally, and be not suitable for being applied in large-scale radar sensing system.

Summary of the invention

Technology of the present invention is dealt with problems: overcome the deficiencies in the prior art, a kind of intermediate frequency LFM-PD radar signal real time processing system and disposal route based on FPGA and DSP is provided, can meet the requirement of real-time processing, and the construction cycle is short, dirigibility is strong, is applicable to being applied in large-scale radar sensing system.

Technical solution of the present invention: a kind of intermediate frequency LFM-PD radar signal real time processing system based on FPGA and DSP, comprising: FPGA and DSP.Wherein FPGA comprises if sampling module, Digital Down Converter Module, pulse compression module; DSP comprises coherent accumulation module, motion compensating module and CFAR detection (CFAR) module.The signal that enters FPGA if sampling module is if radar signal, and the direct IF Sampling by if sampling module has obtained digital medium-frequency signal; Digital medium-frequency signal enters Digital Down Converter Module, carries out Digital Down Convert, has obtained I, Q two paths of signals; I, Q two paths of signals enter pulse compression module, and pulse compression module produces matching factor to I, Q two paths of signals, carries out process of pulse-compression.Signal after pulse compression enters DSP coherent accumulation module, and this module is FFT to signal, obtains accumulating result; Signal after coherent accumulation enters CFAR detection module and detects, and judges whether to exist target.

Pulse compression module comprises matching factor generation module, FFT module, takes advantage of module and IFFT module again.Each several part annexation as shown in the figure.I, Q signal are introduced into FFT module and do FFT computing, the coefficient that generation is simultaneously mated with I, Q signal, coefficient after producing is done to FFT computing, the result that twice FFT draws enters takes advantage of module to carry out after multiple multiplication again, enter IFFT module and carry out IFFT computing, the result after IFFT computing is the result after pulse compression.

Motion compensating module has adopted movement compensating algorithm.Native system adopts envelope delay backoff algorithm, the target velocity result that this algorithm calculates by previous frame data calculates the required motion compensation quantity of making of next frame data, the sequential that the parameter adjustment gate signal that FPGA revises according to DSP generates, simultaneously by adding up to corrected parameter, determine in a frame pulse string, the clock periodicity that each pulse gate signal demand is adjusted, realizes motion compensation by adjusting the gate signal of straight ripple, echo.

Described CFAR detection module is realized by DSP, this module is by sliding window module, detection threshold computing module and signal detection module form, signal after coherent accumulation is introduced into sliding window module, through sliding window module, filter out detecting unit, protected location and reference unit, described detection unit refers to the region that will detect, protection unit is the unit adjacent with detecting unit left and right, reference unit is the unit of detecting unit the right and left, then via detection threshold computing module, calculate required detection threshold, finally by signal detection module, judge in detecting unit whether have target.

An intermediate frequency LFM-PD radar signal real-time processing method based on FPGA and DSP, performing step is as follows:

(1) pass through if sampling module by the intermediate frequency LFM-PD radar signal discretize of simulation, intermediate frequency LFM-PD radar signal is carried out to quadrature sampling of medium frequency signal;

(2) digital signal that sampling obtains is carried out Digital Down Convert by Digital Down Converter Module, obtains I road signal and Q road signal;

(3) I road signal and Q road signal are by the pulse compression module in FPGA, by FFT module, first do FFT computing, matching factor generation module generates the coefficient with Signal Matching, coefficient is done to FFT computing, the result of twice FFT computing enters takes advantage of module to take advantage of again again, result after taking advantage of again enters IFFT module and carries out IFFT computing, completes pulse compression;

(4) utilize the signal after the coherent accumulation module paired pulses compression of DSP to carry out FFT computing, complete coherent accumulation;

(5) utilize DSP to carry out motion compensation calculations to the result after coherent accumulation, and by the parameter feedback calculating the controlling of sampling module to FPGA (13), complete the motion compensation to radar signal;

(6) result after utilizing CFAR detection (CFAR) module in DSP to coherent accumulation is carried out CFAR detection (CFAR).Signal after coherent accumulation is introduced into sliding window module; via sliding window module, filter out detecting unit, protected location and reference unit; then via detection threshold computing module, calculate required detection threshold, finally by signal detection module, judge in detecting unit whether have target.

The present invention's advantage is compared with prior art:

(1) the present invention is when doing process of pulse-compression, and essence is that the complex signal of base band is done to FFT, and Frequency Domain Pulse coefficient is taken advantage of and IFFT again.What the hardware implementation structure of fft algorithm adopted is pipeline organization, can calculate uninterruptedly.The maximum data percent of pass of the present invention is 210MSPS, and completing a pulse pressure processing time is only 0.25ms, can meet the data processing of nearly all radar now.

(2) the present invention adopts the method for time domain motion compensation, by adjusting the gate signal of straight ripple, echo, realizes motion compensation.The sequential that the parameter adjustment gate signal that FPGA revises according to DSP generates, cumulative by corrected parameter, determines in a frame pulse string clock periodicity that each pulse gate signal demand is adjusted simultaneously.This method realizes simple, and does not exist pulse signal to overflow the problem of gate signal scope.

(3) to take classical Digital Down Convert and pulse compression theory be basis in the present invention, data are being carried out to direct IF Sampling, realizing the digital I/Q based on multiphase filtering, broad pulse LFM echo is being carried out to compression pulse processing, make it become burst pulse, thereby obtained High Range Resolution.

(4) adopt programmable device FPGA and DSP as digital signal processing core device, there is very strong dirigibility and adaptability, greatly shortened the construction cycle.

(5) the present invention adopts two-level cache, makes the data that collect realize sufficient buffer memory.Adopt the FIFO of FPGA generation as the first order buffer memory of raw data, SDRAM, as the second level buffer memory of data, is connected with DSP, thereby the sequential of data is better mated.

(6) as far as possible little in order to guarantee the hardware system volume of design, therefore under the prerequisite of hardware burden that does not increase system, utilize existing FPGA in system, designed with FPGA internal resource Block RAM and realized asynchronous FIFO memory as Cache, it reads and writes the different hardware environment of clock frequency before and after meeting, make acquisition system flexible design, simple, convenient, there is very strong extendability.

Accompanying drawing explanation

Fig. 1 is the schematic diagram that the present invention realizes multiphase filtering numeral I/Q;

Fig. 2 is the ultimate principle figure of LFM pulse pressure of the present invention; Wherein, four parts represent respectively frequency delay character, the compression network pulse output of input pulse envelope, pulse carrier frequency frequency modulation characteristic, compression network from top to bottom;

Fig. 3 is structure composition frame chart of the present invention;

In this present invention of Fig. 4, Digital Down Convert realizes result figure; The left side represents the original signal figure of radar; The right represents the result figure of radar original signal after pulse compression;

Fig. 5 is decimation in frequency FFT and decimation in time IFFT figure.

Embodiment

The present invention adopts direct quadrature sampling of medium frequency signal and digital pulse compression mode, thereby realizes pulse compression fast.Schematic diagram as depicted in figs. 1 and 2.Digital Down Convert schematic diagram of the present invention as shown in Figure 1, in digital information processing system, conventionally need to be by the intermediate-freuqncy signal receiving by quadrature sampling, become the digital baseband signal that I, Q two-way represent and process.The I/Q passage inconsistency of bringing for fear of conventional simulation territory quadrature sampling adopts direct IF Sampling in this processor.By direct IF Sampling, extract again, avoided the impact of pre-amplifier DC shift on back end signal processing accuracy, obtained higher image-frequency rejection ratio.

In Fig. 1, the intermediate-freuqncy signal receiving by quadrature sampling, is become to the digital baseband signal that I, Q two-way represent and processes.If input

wherein a (t) is signal envelope,

for first phase, f ₀for carrier frequency.

According to bandpass sample theory, when real signal x (t) is sampled for assurance there is not aliasing, sample frequency f in positive and negative frequency spectrum _swith f ₀and signal bandwidth B should meet relation:

F _s>=2B and in formula, m is any positive integer (2.1)

With f _sinput is sampled, obtains sampled signal sequence:

$x\left(n\right)=a\left(n\right)\·\cos [2\mathrm{\π}\frac{f_0}{f_s}n+\mathrm{\φ}\left(n\right)]=a\left(n\right)\·\cos [2\mathrm{\π}\frac{(2m+1)}{4}n+\mathrm{\φ}\left(n\right)]$

$=a\left(n\right)\cos \mathrm{\φ}\left(n\right)\·\cos \left(\frac{2m+1}{2}\mathrm{\πn}\right)-a\left(n\right)\sin \mathrm{\φ}\left(n\right)\·\sin \left(\frac{2m+1}{2}\mathrm{\πn}\right)$

$=I\left(n\right)\cos \left(\frac{2m+1}{2}\mathrm{\πn}\right)-Q\left(n\right)\sin \left(\frac{2m+1}{2}\mathrm{\πn}\right)---\left(2.2\right)$

In formula, I (n)=a (n) cos φ (n), Q (n)=a (n) sin φ (n), is respectively in-phase component and the quadrature component of signal, and wherein a (n) is the sample sequence of envelope, and φ (n) is the phase place of sequence.In this processor, digital down converter method is: due to

x(2n)＝I(2n)cos[(2m+1)πn]＝I(2n)·(-1) ⁿ (2.3)

x(2n+1)＝-Q(2n+1)sin[(2m+1)/2·π(2n+1)]＝Q(2n+1)·(-1) ⁿ (2.4)

Order: I ' (n)=x (2n) (1) ⁿ, Q ' (n)=x (2n+1) (1) ⁿ, can obtain:

$\left\{\begin{array}{c}{I}^{\′}\left(n\right)=I\left(2n\right)\\ Q^{\′}\left(n\right)=Q(2n+1)\end{array}\right.---\left(2.5\right)$

That is to say that I (n) and two sequences of Q (n) are respectively the 2 frequency divisions extraction sequences of in-phase component I (2n) and quadrature component Q (2n).According to extracting principle, as long as the digital spectral of I (n) and Q (n) is less than pi/2, (be f _s>=4B), its 2 times extract sequence I ' (n), Q ' (n) can represent former sequence undistortedly.Easy proof, I ' is (n), Q ' digital spectral (n) is:

$\left\{\begin{array}{c}{I}^{\′}\left(e^{\mathrm{j\ω}}\right)=\frac{1}{2}I\left(e^{j\frac{\mathrm{\ω}}{2}}\right)\\ Q^{\′}\left(e^{\mathrm{j\ω}}\right)=\frac{1}{2}Q\left(e^{j\frac{\mathrm{\ω}}{2}}\right)\·e^{j\frac{\mathrm{\ω}}{2}}\end{array}\right.---\left(2.6\right)$

The digital spectral that can find out both differs a delay factor

thereby this is owing to having adopted odd even to extract in time domain to differ half sampled point caused.This temporal " misalignment " can adopt two Time-Delay Filters to be proofreaied and correct, and the frequency response of these two wave filters should meet:

$\frac{H_Q\left(e^{\mathrm{j\ω}}\right)}{H_I\left(e^{\mathrm{j\ω}}\right)}=e^{-j\frac{\mathrm{\ω}}{2}}$ And | H _q(e ^{j ω}) |=| H _i(e ^{j ω}) |=1 (2.7)

I ' is (n) sequence of the 2 frequency divisions extractions of I road sequence I (n), and Q ' is (n) sequence that sequence Q ' 2 frequency divisions (n) in Q road extract, I ' (e ^{j ω}) be I ' digital spectral (n), Q ' (e ^{j ω}) be Q ' digital spectral (n), H _q(e ^{j ω}) represent the wave filter amplitude response of Q road signal, H _i(e ^{j ω}) represent the wave filter amplitude response of I road signal.

In the present invention, pulse compression schematic diagram as shown in Figure 2, carries out compression pulse processing to the broad pulse LFM echo receiving, and makes it become burst pulse, the process that its essence is matched filtering.Tu2Zhong first input pulse envelope, second portion pulse carrier frequency frequency modulation characteristic represent that the signal of receiver input is the LFM signal of a broad pulse, and suppose that its carrier frequency increases by constant speed in pulse, and it is by pulse pressure wave filter.This pulse pressure wave filter has the time delay-frequency characteristic shown in the frequency delay character of third part compression network in Fig. 2, its time delay t _dwith frequency linearity, reduce, and speed is advanced the speed identical with the interior frequency of arteries and veins of echo.So it is long by the time lag of wave filter to part after than high frequency to make low frequency in echo-pulse arrive first part, therefore each frequency component in arteries and veins is compressed in together in time domain, the pulse signal that formation amplitude increases, width reduces, its desirable envelope is as shown in the 4th Partial shrinkage network pulse output in Fig. 2.

Fire pulse width τ and system be (compressed) pulsewidth τ effectively ₀ratio, be called pulse compression ratio,

D=τ/τ ₀or D=τ B is wherein, B=1/ τ ₀(2.8)

D is exactly pulse compression ratio, and B is the bandwidth of signal.

Be time wide-bandwidth product that ratio of compression equals signal, it is one of the key technical indexes of weighing pulse pressure processing.

The High Performance DSP ADSP-TS201 Tiger SHARC (TS201) of the High Performance FPGA XC4VSX55 HeAD company of the Virterx4 series of specific implementation Shi Yi Xilinx of the present invention company is workbench, the AD9430 chip of the ADC chip ShiAD company that the discretize of intermediate-freuqncy signal adopts, AD9430 is the digital-to-analog conversion device of a 12bit high sampling rate low-power consumption, in system of the present invention, be operated under LVDS pattern, data pass rate is 210MSPS, doubleway output.Fpga chip XC4VSX55 has the piece storage unit of 512 hardware multipliers and 11.5Mbits, and is directly connected with AD9430 by LVDS signal wire, and a pulse pressure processing time is only 0.25ms, can meet the data processing requirement of nearly all radar now.

Core processor of the present invention is selected the XC4VSX55FPGA of the Virtex4 series of Xilinx company product, this chip is one of representative of high-performance FPGA, the FPGA of a 1,000,000 gate leves, the piece storage unit that has 512 hardware multipliers and 11.5Mbits, processes application mainly for high performance signal.

In the present invention, the signal of two passages is carried out to identical processing simultaneously, process realization flow as shown in Figure 3, comprise FPGA13 and DSP 20, wherein FPGA 13 comprises if sampling module 3, Digital Down Converter Module 4, pulse compression module 12; If sampling module 3 is comprised of A/D module 1 and A/D controlling of sampling module 2.DSP20 comprises coherent accumulation module 14, motion compensating module 15 and CFAR detection (CFAR) module 19; If radar signal enters in the if sampling module 3 of FPGA13, and the direct IF Sampling of controlling A/D module 1 by A/D controlling of sampling module 2 obtains digital medium-frequency signal; Digital medium-frequency signal enters Digital Down Converter Module 4, carries out Digital Down Convert, has obtained I, Q two paths of signals; I, Q two paths of signals enter pulse compression module 12 and carry out process of pulse-compression; Signal after process of pulse-compression enters in DSP coherent accumulation module 14 and carries out FFT, obtains coherent accumulation result; Signal after coherent accumulation enters motion compensating module 15, calculates the motion compensation quantity that need to make by movement compensating algorithm, and the parameter feedback drawing is adjusted to gate signal sequential to the controlling of sampling module 2 of FPGA13; Signal after last coherent accumulation enters CFAR detection (CFAR) module 19 and detects, and judges whether to exist target.

In the present invention, first intermediate frequency LFM-PD radar signal enters the if sampling module 3 being comprised of A/D module 1 and A/D controlling of sampling module 2, and the ADC chip using in if sampling module is AD9430, and this chip has two sampling channels, can doubleway output.If radar signal is exported the digital signal of two-way after 3 samplings of if sampling module.A/D controlling of sampling module 2 in if sampling module 3 is realized according to the feedback parameter of motion compensating module 15 computings of DSP20 by FPGA 13, A/D controlling of sampling module 2 is controlled the sampling time sequence of A/D module 1, and then realizes the controlling of sampling to LFM-PD radar signal.Complete digital signal after sampling and send into Digital Down Converter Module 4 and complete Digital Down Convert, after Digital Down Convert, generated I/Q two paths of signals.I/Q two paths of signals enters pulse compression module 12 after generating and does process of pulse-compression.Pulse compression module 12 comprises matching factor generation module 5, FFT module 6, takes advantage of module 10 and IFFT module 11 again.I/Q two paths of signals enters after pulse compression module 12, the matching factor generation module 5 of pulse compression module 12 produces the coefficient matching according to the I/Q two paths of signals entering, simultaneously 6 pairs of I/Q two paths of signals of FFT module are done FFT computing, and by the result store after computing in RAM.The coefficient that matching factor generation module 5 produces completes at FFT computing module 6 and enters FFT computing module 6 after the FFT computing of I/Q two paths of signals and carry out FFT computing module, and operation result is stored in RAM.FFT module 6 completes after the FFT computing of matching factor, takes advantage of again the FFT result of 10 pairs of I/Q two paths of signals of module and the result of matching factor FFT to do multiple multiplication, and by the result store after taking advantage of again in RAM.Take advantage of again module 10 to complete after multiple multiplication, IFFT11 module is to taking advantage of again result to do IFFT computing, and the result after IFFT computing is exactly the result of pulse compression.

The result of pulse compression is sent into the coherent accumulation module 14 in DSP20 module, and coherent accumulation module 14 paired pulses compression result are done FFT computing, complete the coherent accumulation of pulse compression result.Result after coherent accumulation is sent into motion compensating module 15, motion compensating module 15 calculates according to the result of coherent accumulation the parameter needing, and correlation parameter is fed back to A/D controlling of sampling module 2, the parameter that A/D controlling of sampling module 2 can obtain according to the feedback adjustment of sampling.The result of coherent accumulation is also admitted to CFAR detection (CFAR) module 19, and CFAR detection (CFAR) module 19 comprises sliding window module 16, detection threshold computing module 17 and signal detection module 18.Sliding window module 16 is CFAR according to the result of coherent accumulation and is detected the slide window processing needing, result after slide window processing is sent into signal detection module 18, detection threshold computing module 17 can calculate and detect the needed detection threshold of target according to the result of coherent accumulation simultaneously, and sends detection threshold value to signal detection module 18.The result of last coherent accumulation detects whether there is target in signal detection module 18, and testing result is exported.

DSP and FPGA work in SOMD pattern, with identical signal processing flow work.Here only with passage 1, analyze.Needs due to digital I/Q; system is sampled with the frequency of 160MHz; each impulse sampling is considered the protected location of a few μ s in the time; the last sampling time is 50 μ s; the complex sampling obtaining after digital I/Q is counted totally 80 * 50=4000; therefore in the process of pulse compression, adopted the FFT of 4096, IFFT and taking advantage of again.For each complex points, need the storage space of two words (word) to be respectively used to store real part and imaginary part, so the data volume of each pulse is 4096 * 2=8KWords=256Kbits; And because the pulse number of a frame signal is 170～256, therefore coherent accumulation adopts 256 FFT while being Doppler, be that Doppler's unit number is 256, therefore to a frame signal carry out before coherent accumulation data volume be 4096 * 256 * 2=2M Words=64Mbits; And after coherent accumulation, owing to plural number having been carried out asking mould, data volume is 4096 * 256=1M Words=32Mbits.In processor, the task of each chip is distributed as shown in table 1.In conjunction with the processing speed of XC4VSX55 and ADSP-TS201S, calculate the processing time of algorithm in processor, the traffic of front and back, the memory space needing, the time of long permission is as shown in table 2.

Processing tasks in each processor of table 1

Each subalgorithm operand of table 2LFM-PD

According to the present invention, utilize FPGA and DSP design to realize a high speed intermediate frequency LFM-PD radar real-time processor, and Digital Down Convert and process of pulse-compression process are optimized, have the following advantages:

processing speed is high, and performance is remarkable.

utilize the method for designing of software and combination of hardware, user can revise flexibly.

in the present invention, the algorithm of Digital Down Convert and pulse compression can be generalized in other digital signal processing algorithms.

Visible, utilize FPGA and DSP design to have very high using value with Digital Down Convert and the intermediate frequency LFM-PD radar real-time processor realized, can be applied in military radar input, also can, in the performance great role of civilian Data Detection field, have good development space simultaneously.

Claims (2)

1. the intermediate frequency LFM-PD radar signal real time processing system based on FPGA and DSP, it is characterized in that comprising: FPGA(13) and DSP(20), FPGA(13 wherein) comprise if sampling module (3), Digital Down Converter Module (4), pulse compression module (12), if sampling module (3) is comprised of A/D module (1) and A/D controlling of sampling module (2); DSP(20) comprise coherent accumulation module (14), motion compensating module (15) and CFAR detection (CFAR) module (19); If radar signal enters FPGA(13) if sampling module (3) in, the direct IF Sampling of being controlled A/D module (1) by A/D controlling of sampling module (2) obtains digital medium-frequency signal; Digital medium-frequency signal enters Digital Down Converter Module (4), carries out Digital Down Convert, has obtained I, Q two paths of signals; I, Q two paths of signals enter pulse compression module (12) and carry out process of pulse-compression; Signal after process of pulse-compression enters in DSP coherent accumulation module (14) and carries out FFT, obtains coherent accumulation result; Signal after coherent accumulation enters motion compensating module (15), calculates the motion compensation quantity that need to make by movement compensating algorithm, by the parameter feedback drawing to FPGA(13) controlling of sampling module (2) adjust gate signal sequential; Signal after last coherent accumulation enters CFAR detection (CFAR) module (19) and detects, and judges whether to exist target;

Described pulse compression module (12) comprises matching factor generation module (5), FFT module (6), takes advantage of module (10) and IFFT module (11) again; I, Q signal are introduced into FFT module (6) and do FFT computing, the coefficient that matching factor generation module (5) generation is simultaneously mated with I, Q signal, coefficient after producing is done to FFT computing, the result that twice FFT draws enters takes advantage of module (10) to carry out after multiple multiplication again, enter IFFT module (11) and carry out IFFT computing, the result after IFFT computing is the result after process of pulse-compression;

Described motion compensating module adopts envelope delay backoff algorithm, the target velocity result that described envelope delay backoff algorithm calculates by previous frame data calculates the required motion compensation quantity of making of next frame data, then feed back to controlling of sampling module (2), controlling of sampling module (2) is according to the sequential of the parameter adjustment gate signal of envelope delay backoff algorithm feedback;

Described CFAR detection module (19) comprises sliding window module (16), detection threshold computing module (17) and signal detection module (18); Signal after coherent accumulation is introduced into sliding window module (16); via sliding window module (16), filter out detecting unit, protected location and reference unit; described detecting unit refers to the region that will detect; protected location is the unit adjacent with detecting unit left and right; reference unit is the unit of detecting unit the right and left; then via detection threshold computing module (17), calculate required detection threshold, finally by signal detection module (18), judge in detecting unit whether have target.

2. the intermediate frequency LFM-PD radar signal real-time processing method based on FPGA and DSP, is characterized in that performing step is as follows:

Step 1: by the intermediate frequency LFM-PD radar signal discretize of simulation, intermediate frequency LFM-PD radar signal is carried out to quadrature sampling of medium frequency signal by if sampling module (3);

Step 2: the digital signal that sampling obtains is carried out Digital Down Convert by Digital Down Converter Module (4), obtains I road signal and Q road signal;

Step 3:I road signal and Q road signal pass through FPGA(13) in pulse compression module (12), by FFT module (6), first signal is done to FFT computing, matching factor generation module (5) generates the coefficient with Signal Matching, FFT module (6) is again to doing FFT computing with the coefficient of Signal Matching, the result of twice FFT computing enters takes advantage of module (10) to take advantage of again again, result after taking advantage of again enters IFFT module (11) and carries out IFFT computing, completes pulse compression;

Step 4: utilize DSP(20) signal after coherent accumulation module (14) paired pulses compression carries out FFT computing, completes coherent accumulation;

Step 5: utilize DSP(20) result after coherent accumulation is carried out to motion compensation calculations, and by the parameter feedback calculating to FPGA(13) controlling of sampling module (2), complete the motion compensation to radar signal;

Step 6: utilize DSP(20) result after the CFAR detection in (CFAR) module (19) accumulates coherent is carried out CFAR detection (CFAR); signal after coherent accumulation is introduced into sliding window module (16); via sliding window module (16), filter out detecting unit, protected location and reference unit; then via detection threshold computing module (17), calculate required detection threshold, finally by signal detection module (18), judge in detecting unit whether have target.

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