CN112558032B - Digital signal processing assembly for ground warning radar - Google Patents
Digital signal processing assembly for ground warning radar Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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- G—PHYSICS
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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- G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
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Abstract
The invention relates to the field of radar signal processing, in particular to a digital signal processing component for ground warning radar, which adopts a double-FPGA structural form, fully exerts the characteristics of strong logic control capability and high-speed signal processing capability of an FPGA, and has stronger processing capability, larger storage capacity, more flexible interface and expandability compared with the traditional ground warning radar digital signal processing component; aiming at improving the existing ground warning radar digital signal processing method, the anti-interference and clutter suppression capability is stronger, and the signal processing effect is better.
Description
Technical Field
The invention provides a radar digital processing component for a ground warning radar, and belongs to the field of radar signal processing.
Background
Radar signal processing is an indispensable importance in radar systems. The essence is the process of demodulating the target echo, extracting useful information, reducing the interference of noise, removing unnecessary clutters and obtaining the required target information through certain processing. Early radars used analog circuitry to process the signal, not only was the structure complex, but the circuitry itself was also extremely susceptible to interference. With the continuous development of digital circuit technology and the application of the digital circuit technology in the aspect of radar signal processing, the overall performance of the radar is greatly improved. Subsequent developments in microelectronics, and in particular microprocessor technology, have led to a gradual conversion of radar signal processing from analogue to digital. Ground warning radars are required to be able to discover targets within range of action early and to determine their location approximately, and to closely monitor the activity of targets within range of action, as they serve as ground warning tasks in homeland defense. The signal processing system is necessarily a very critical part in order to effectively ensure high real-time performance and reliability of the working state of the warning radar. Therefore, the research on the special digital signal processing component applied to the ground warning radar has great significance for promoting the development of the ground warning radar.
The traditional radar digital signal processing component is realized by adopting a DSP, the technology is mature, but the DSP instruction is more suitable for realizing algorithm instead of logic control, the universality of an external interface is poor, and the control of a radar system is not flexible enough. The warrior of the university of electronic science and technology designs a warning radar signal processor based on FPGA and DSP, wherein the DSP is used as a main controller, and the FPGA is used as a coprocessor. The FPGA completes the sequential logic control, data format conversion and logic level conversion of the peripheral interface and the A/D, D/A converter. The DSP performs FFT processing to control data transmission. The architecture has the advantages that the whole hardware system is coordinated, the distribution of the computing resources is balanced, but the design and the realization of a hardware circuit are complex. Based on the above, the invention designs the radar digital signal processing component based on the FPGA, and all functions of the radar digital signal processing component are realized by two identical FPGAs. The FPGA has incomparable logic control capability of the DSP, has abundant digital signal processing IP core resources, has complete capability of realizing complex digital processing algorithms, and has relatively simple hardware circuit design compared with the FPGA+DSP hardware architecture.
Disclosure of Invention
The technical problems solved by the invention are as follows: the digital signal processing component for the ground warning radar is provided for realizing the functions of system control and digital signal processing of the ground warning radar, and improving the existing ground warning radar signal processing method to achieve better effects.
The technical scheme adopted by the invention is as follows: a radar digital processing component for ground warning radar comprises an analog-to-digital conversion module, a main control module and a storage module; wherein:
the analog-to-digital conversion module is used for performing analog-to-digital conversion on the radar echo signal to obtain an intermediate frequency digital signal sequence, and then sending the intermediate frequency digital signal sequence to the main control module;
the main control module carries out digital quadrature down-conversion on the intermediate frequency digital signal sequence to obtain an I-path digital baseband signal and a Q-path digital baseband signal, carries out pulse compression processing on the I-path digital baseband signal and the Q-path digital baseband signal, and removes broadband modulation signals to obtain an I-path narrow pulse echo sequence and a Q-path narrow pulse echo sequence; sequentially storing the I-path narrow pulse echo sequence and the Q-path narrow pulse echo sequence of each pulse repetition period into a storage module according to a distance dimension sequence, taking out and rearranging the I-path narrow pulse echo sequence and the Q-path narrow pulse echo sequence of a plurality of pulse repetition periods from the storage module according to a Doppler dimension sequence to obtain a plurality of pulse sequences of the same distance unit of the plurality of pulse repetition periods, performing moving target display processing on a plurality of pulse data of the same distance unit of the plurality of pulse repetition periods, removing a static target to obtain an I-path moving target display echo sequence and a Q-path moving target display echo sequence, performing moving target detection on the I-path moving target display echo sequence and the Q-path moving target display echo sequence, and performing constant false alarm processing according to a moving target detection result to obtain a target state, a target amplitude, a target distance and a target speed;
the storage module is used for storing the I path narrow pulse echo sequence and the Q path narrow pulse echo sequence.
The main control module comprises a first FPGA module and a second FPGA module;
the first FPGA module is used for carrying out digital quadrature down-conversion on the intermediate frequency digital signal sequence to obtain I, Q two paths of quadrature digital baseband signals, carrying out pulse compression processing on I, Q two paths of quadrature digital baseband signals, removing broadband modulation signals to obtain an I path of narrow pulse echo sequence and a Q path of narrow pulse echo sequence, and sequentially storing the I path of narrow pulse echo sequence and the Q path of narrow pulse echo sequence into the storage module according to a distance dimension sequence;
and the second FPGA module is used for taking out and rearranging the I-path narrow pulse echo sequence and the Q-path narrow pulse echo sequence of the pulse repetition periods from the storage module according to the Doppler dimension sequence to obtain a plurality of pulse sequences of the same distance unit of the pulse repetition periods, performing moving target display processing on a plurality of pulse data of the same distance unit of the pulse repetition periods, removing static targets to obtain an I-path moving target display echo sequence and a Q-path moving target display echo sequence, performing moving target detection on the I-path moving target display echo sequence and the Q-path moving target display echo sequence, and performing constant false alarm processing according to the moving target detection result to obtain a target state, a target amplitude, a target distance and a target speed.
The processing procedure of the first FPGA module for carrying out digital quadrature down-conversion on the intermediate frequency digital signal sequence is as follows:
odd-even alternate sampling is carried out on the intermediate frequency digital signals to form two paths of intermediate frequency digital signals, and then each path of intermediate frequency digital signals is multiplied by a symbol (-1) in sequence k K is the number of sampling points of each path of intermediate frequency digital signal, and the symbol correction processing is completed; and finally, extracting according to a preset rate to reduce the processing rate of a subsequent processing module, thereby obtaining an I-path digital baseband signal and a Q-path digital baseband signal.
The pulse compression processing process comprises the following steps:
the I path digital baseband signal is subjected to matched filtering treatment through an I path filter and a Q path filter respectively to obtain a first pulse compression signal and a second pulse compression signal;
the Q paths of digital baseband signals are subjected to matched filtering treatment through an I path filter and a Q path filter respectively to obtain a third pulse compression signal and a fourth pulse compression signal;
the first pulse compression signal and the fourth pulse compression signal are subjected to difference to obtain an I-path narrow pulse echo sequence;
and summing the second pulse compression signal and the third pulse compression signal to obtain a Q-path narrow pulse echo sequence.
The step of sequentially storing the I path narrow pulse echo sequence and the Q path narrow pulse echo sequence of each pulse repetition period according to the distance dimension sequence is as follows:
for M pulse repetition periods received by the ground warning radar, each pulse repetition period corresponds to echo signals of N distance units, an I-path narrow pulse echo sequence and a Q-path narrow pulse echo sequence obtained after pulse compression processing respectively form M rows and N columns of data matrixes, the M rows and the Q-path narrow pulse echo sequences are recorded as an I-path data matrix and a Q-path data matrix, and the I-path data matrix and the Q-path data matrix are respectively stored in a storage module.
The moving target display processing process comprises the following steps:
sequentially taking out the I-path data matrixes of M rows and N columns according to the columns to obtain an I-path rearranged narrow pulse echo sequence;
sequentially taking out the Q paths of data matrixes of M rows and N columns according to the columns to obtain a Q paths of rearranged narrow pulse echo sequence;
the method comprises the steps that after an I-path rearranged narrow pulse echo sequence is subjected to filtering treatment through an I-path filter and a Q-path filter respectively, a first moving target display treatment signal and a second moving target display treatment signal are obtained;
the Q-path rearranged narrow pulse echo sequence is subjected to matching filtering treatment through an I-path filter and a Q-path filter respectively, and then a third moving target display treatment signal and a fourth moving target display treatment signal are obtained;
the first moving target display processing signal and the fourth moving target display processing signal are subjected to difference to obtain an I-path moving target display echo sequence;
and summing the second moving target display processing signal and the third moving target display processing signal to obtain a Q-path moving target display echo sequence.
The moving target detection processing process comprises the following steps:
and (3) performing FFT (fast Fourier transform) on M points on the echo sequence displayed by the I-path moving target and the echo sequence displayed by the Q-path moving target to obtain a pulse sequence after coherent accumulation, namely: an I-path moving target detection echo sequence and a Q-path moving target detection echo sequence.
The constant false alarm detection processing process comprises the following steps:
taking the nth echo sequence element of the mth pulse repetition period I-path moving target detection echo sequence and the mth pulse repetition period Q-path moving target detection echo sequence as detection units, traversing each detection unit and executing the following steps:
(S1) calculating the power of each detection unit according to the I-path moving target detection echo sequence and the Q-path moving target detection echo sequence;
(S2) performing distance dimension detection: taking L detection units in front of and behind the detection unit according to lines, taking the average power of the reference unit as a reference unit, obtaining a first threshold value, judging whether the power of the detection unit is larger than the first threshold value, if so, performing the S3 step, otherwise, judging that the detection unit is in a non-target state, and L is larger than or equal to 1;
(S3) performing doppler detection: taking L detection units in front of and behind the detection unit according to the row, taking the L detection units as reference units, obtaining the average power of the reference units to obtain a second threshold value, judging whether the power of the detection unit is larger than the second threshold value, and judging that the detection unit has a target state if the power of the detection unit is larger than the second threshold value; step (S4) is entered; otherwise, judging that the detection unit has no target, wherein L is more than or equal to 1;
and S4, calculating the target amplitude, the target distance and the target speed according to the distance unit sequence number n and the pulse repetition period sequence number m of the detection unit, and outputting n epsilon [1, N ], m epsilon [1, M ].
Compared with the prior art, the invention has the advantages that:
(1) According to the invention, the moving target display (MTI), the Moving Target Detection (MTD) and the two-dimensional Constant False Alarm (CFAR) are adopted in the ground warning radar digital signal processing method, so that the anti-interference and clutter suppression capabilities of the radar are improved, and a better signal processing effect is obtained.
(2) The invention fully exerts the powerful logic control capability and digital signal processing capability of the FPGA by adopting the structure form of the double FPGAs, and solves the problems of inflexible control and complex hardware design of the traditional ground warning radar digital signal processing component.
(3) The FPGA1 carries out digital down-conversion and pulse compression processing on the intermediate frequency digital signal sequence, and simultaneously completes sensitivity time control, the FPGA2 carries out moving target display (MTI), moving Target Detection (MTD) and Constant False Alarm (CFAR) processing on the echo sequence after pulse pressure, and compared with the traditional ground warning radar digital signal processing component, the processing capacity is stronger, the storage capacity is larger, the interface is more flexible, and the expandability is realized.
Drawings
FIG. 1 is a diagram showing the construction of a radar digital processing assembly for a ground surveillance radar according to the present invention;
FIG. 2 is a digital down-conversion architecture of the present invention;
FIG. 3 is a block diagram of an implementation of digital down conversion of the present invention;
FIG. 4 is a block diagram of an implementation of pulse compression of the present invention;
FIG. 5 is a block diagram of an implementation of a moving object display of the present invention;
FIG. 6 is a block diagram of an implementation of moving object detection of the present invention;
FIG. 7 is a flow chart of an implementation of the constant false alarm detection of the present invention;
FIG. 8 is a flow chart of radar signal processing according to the present invention;
FIG. 9 is a diagram illustrating an embodiment of a memory module allocation map.
Detailed Description
In order to make the technical scheme, technical features, achievement of the purpose and effect of the invention easy to understand, the invention is further described below with reference to the specific embodiments.
The invention provides a radar digital processing component for a ground warning radar, which comprises an analog-to-digital conversion module, a main control module and a storage module; wherein:
the analog-to-digital conversion module is used for performing analog-to-digital conversion on the radar echo signal to obtain an intermediate frequency digital signal sequence, and then sending the intermediate frequency digital signal sequence to the main control module;
the main control module carries out digital quadrature down-conversion on the intermediate frequency digital signal sequence to obtain an I-path digital baseband signal and a Q-path digital baseband signal, carries out pulse compression processing on the I-path digital baseband signal and the Q-path digital baseband signal, and removes broadband modulation signals to obtain an I-path narrow pulse echo sequence and a Q-path narrow pulse echo sequence; sequentially storing an I path narrow pulse echo sequence and a Q path narrow pulse echo sequence of each pulse repetition period into a storage module according to a distance dimension sequence, taking out and rearranging the I path narrow pulse echo sequence and the Q path narrow pulse echo sequence of a plurality of pulse repetition periods from the storage module according to a Doppler dimension sequence to obtain a plurality of pulse sequences of a plurality of pulse repetition period same distance units, performing moving target display (MTI) processing on a plurality of pulse data of a plurality of pulse repetition period same distance units, removing static targets to obtain an I path moving target display echo sequence and a Q path moving target display echo sequence, performing Moving Target Detection (MTD) on the I path moving target display echo sequence and the Q path moving target display echo sequence, and performing Constant False Alarm (CFAR) processing according to the results of the Moving Target Detection (MTD) to obtain a target state, a target amplitude, a target distance and a target speed;
the storage module is used for storing the I path narrow pulse echo sequence and the Q path narrow pulse echo sequence.
As shown in fig. 1, the main control module includes a first FPGA module and a second FPGA module;
the first FPGA module is used for carrying out digital quadrature down-conversion on the intermediate frequency digital signal sequence to obtain I, Q two paths of quadrature digital baseband signals, carrying out pulse compression processing on I, Q two paths of quadrature digital baseband signals, removing broadband modulation signals to obtain an I path of narrow pulse echo sequence and a Q path of narrow pulse echo sequence, and sequentially storing the I path of narrow pulse echo sequence and the Q path of narrow pulse echo sequence into the storage module according to a distance dimension sequence;
and the second FPGA module is used for taking out and rearranging the I-path narrow pulse echo sequence and the Q-path narrow pulse echo sequence of the pulse repetition periods from the storage module according to the Doppler dimension sequence to obtain a plurality of pulse sequences of the same distance unit of the pulse repetition periods, performing moving target display (MTI) processing on a plurality of pulse data of the same distance unit of the pulse repetition periods, removing a static target to obtain an I-path moving target display echo sequence and a Q-path moving target display echo sequence, performing Moving Target Detection (MTD) on the I-path moving target display echo sequence and the Q-path moving target display echo sequence, and performing Constant False Alarm (CFAR) processing according to the result of the Moving Target Detection (MTD) to obtain a target state, a target amplitude, a target distance and a target speed.
As shown in fig. 2 and fig. 3, the processing procedure of the first FPGA module for performing digital quadrature down-conversion on the intermediate frequency digital signal sequence is:
odd-even alternate sampling is carried out on the intermediate frequency digital signals to form two paths of intermediate frequency digital signals, and then each path of intermediate frequency digital signals is multiplied by a symbol (-1) in sequence k K is the sampling point number of each path of intermediate frequency digital signal,finishing the symbol correction processing; and finally, extracting according to a preset rate to reduce the processing rate of a subsequent processing module, thereby obtaining an I-path digital baseband signal and a Q-path digital baseband signal.
The implementation block diagram of pulse compression is shown in fig. 4, and the pulse compression processing process is as follows:
the I path digital baseband signal is subjected to matched filtering treatment through an I path filter and a Q path filter respectively to obtain a first pulse compression signal and a second pulse compression signal;
the Q paths of digital baseband signals are subjected to matched filtering treatment through an I path filter and a Q path filter respectively to obtain a third pulse compression signal and a fourth pulse compression signal;
the first pulse compression signal and the fourth pulse compression signal are subjected to difference to obtain an I-path narrow pulse echo sequence;
and summing the second pulse compression signal and the third pulse compression signal to obtain a Q-path narrow pulse echo sequence.
The step of sequentially storing the I path narrow pulse echo sequence and the Q path narrow pulse echo sequence of each pulse repetition period according to the distance dimension sequence is as follows:
for M pulse repetition periods received by the ground warning radar, each pulse repetition period corresponds to echo signals of N distance units, an I-path narrow pulse echo sequence and a Q-path narrow pulse echo sequence obtained after pulse compression processing respectively form M rows and N columns of data matrixes, the M rows and the Q-path narrow pulse echo sequences are recorded as an I-path data matrix and a Q-path data matrix, and the I-path data matrix and the Q-path data matrix are respectively stored in a storage module.
The moving target display is performed in a slow time domain, namely, a plurality of pulse data of the same distance unit are processed, so that data rearrangement is required, then filtering processing is performed, the implementation of the filtering processing is similar to pulse compression, and I, Q two paths of data are respectively processed by h I (m)、h Q (m) a filter, and synthesizing a final output result. The implementation structure of the moving object display can be designed as shown in fig. 5.
As shown in fig. 5, the moving target display processing procedure is:
sequentially taking out the I-path data matrixes of M rows and N columns according to the columns to obtain an I-path rearranged narrow pulse echo sequence;
sequentially taking out the Q paths of data matrixes of M rows and N columns according to the columns to obtain a Q paths of rearranged narrow pulse echo sequence;
the method comprises the steps that after an I-path rearranged narrow pulse echo sequence is subjected to filtering treatment through an I-path filter and a Q-path filter respectively, a first moving target display treatment signal and a second moving target display treatment signal are obtained;
the Q-path rearranged narrow pulse echo sequence is subjected to matching filtering treatment through an I-path filter and a Q-path filter respectively, and then a third moving target display treatment signal and a fourth moving target display treatment signal are obtained;
the first moving target display processing signal and the fourth moving target display processing signal are subjected to difference to obtain an I-path moving target display echo sequence;
and summing the second moving target display processing signal and the third moving target display processing signal to obtain a Q-path moving target display echo sequence.
The moving object detection is also a slow time domain process, as shown in fig. 6, in which the moving object detection process is:
and (3) performing FFT (fast Fourier transform) on M points on the echo sequence displayed by the I-path moving target and the echo sequence displayed by the Q-path moving target to obtain a pulse sequence after coherent accumulation, namely: an I-path moving target detection echo sequence and a Q-path moving target detection echo sequence.
As shown in fig. 8, the constant false alarm detection processing procedure is as follows:
taking the nth echo sequence element of the mth pulse repetition period I-path moving target detection echo sequence and the mth pulse repetition period Q-path moving target detection echo sequence as detection units, traversing each detection unit and executing the following steps:
(S1) calculating the power of each detection unit according to the I-path moving target detection echo sequence and the Q-path moving target detection echo sequence;
(S2) performing distance dimension detection: taking L detection units in front of and behind the detection unit according to lines, taking the average power of the reference unit as a reference unit, obtaining a first threshold value, judging whether the power of the detection unit is larger than the first threshold value, if so, performing the S3 step, otherwise, judging that the detection unit is in a non-target state, and L is larger than or equal to 1;
(S3) performing doppler detection: taking L detection units in front of and behind the detection unit according to the row, taking the L detection units as reference units, obtaining the average power of the reference units to obtain a second threshold value, judging whether the power of the detection unit is larger than the second threshold value, and judging that the detection unit has a target state if the power of the detection unit is larger than the second threshold value; step (S4) is entered; otherwise, judging that the detection unit has no target, wherein L is more than or equal to 1;
and S4, calculating the target amplitude, the target distance and the target speed according to the distance unit sequence number n and the pulse repetition period sequence number m of the detection unit, and outputting n epsilon [1, N ], m epsilon [1, M ].
The target amplitude is the square of the power value, and the target amplitude is the square of the detection echo value of the I path moving target of the detection unit plus the square of the detection echo value of the Q path moving target;
the target distance is: n times the theoretical distance resolution ((3 x 10) 8 * Pulse repetition period)/(2*N)),
the target speed is: m times the theoretical velocity resolution (1/(pulse repetition period. M)).
Examples:
the invention provides a radar digital processing assembly for a ground warning radar, which comprises an analog-to-digital conversion module, a main control module, a Sensitivity Time Control (STC) module, a storage module and an RS422 communication module.
1. The analog-to-digital conversion module adopts a high-speed ADC chip LTC2209, has 16-bit high resolution and a sampling rate of 160MSPS, completes band-pass sampling of an analog radar echo signal received by a radar antenna, converts the analog radar echo signal into a data stream suitable for FPGA processing, namely an intermediate frequency digital signal sequence, and then sends the data stream into the main control module for digital signal processing. The center frequency of the radar echo signal is 120MHz, the bandwidth is 40MHz, the sampling clock of the ADC is 160MHz according to the band-pass sampling law, the data flow rate output by the ADC is 160MHz, and the bandwidth is 40MHz. The main control module mainly comprises 2 FPGAs and 2 configuration chips, namely FPGA1 and FPGA2, and the programmable logic chip FPGA adopts an EP3SE110F1152I3 chip of ALTERA company, which has abundant on-chip resources and GPIO and satisfies the connection with various interfaces. The function of the FPGA1 is to perform digital down conversion and pulse compression processing on a medium frequency digital signal sequence, and meanwhile, the FPGA1 also needs to complete a sensitivity time control function. The FPGA2 has functions of performing moving target display (MTI), moving Target Detection (MTD) and Constant False Alarm (CFAR) processing on the echo sequence after pulse pressure.
The STC module comprises a DAC chip and an operational amplifier circuit, the DAC chip adopts AD9708 with 8bit resolution, the updating rate is up to 125MSPS, and the amplitude of the echo signal received by the receiver is adjusted by adjusting a voltage-controlled curve. The storage module is used for storing and rearranging large-capacity data. In the MTI operation, the data needs to be converted in the fast and slow domains, so that the data needs to be rearranged, and then 2 pieces of DDR2 SDRAM external memory are needed to realize. The memory module comprises two DDR2 SDRAM, adopts MT47H64M16 of MICRON company as a memory chip, has a memory capacity of 128MB, has a data rate as high as 667MT/s, and meets the requirements of system memory and rate. The RS422 communication module comprises a plurality of RS422 transceiver chips, and adopts ADM3488E of ANALOG DEVICES company, wherein the communication rate is 250kbps at maximum. The RS422 communication module realizes the function of completing the communication requirements among the radar digital processing assembly, the receiving and transmitting assembly, the upper computer and the servo. For example, the upper computer command is received, the echo signal of the transceiver is received, and the finally obtained target distance and target speed are transmitted to the upper computer.
Referring to fig. 8, the signal flow of the radar digital processing component of the ground alert radar of the present invention is: the radar echo intermediate frequency signal is subjected to A/D sampling to obtain an intermediate frequency digital signal sequence, orthogonal demodulation of DDC is performed to obtain I, Q two paths of orthogonal digital baseband signals, the I, Q paths of orthogonal digital baseband signals are respectively input into a pulse compression network, the echo sequence after pulse compression is sent into a buffer storage area to carry out data rearrangement, the digital signal sequence is converted from a fast time domain to a slow time domain, and then the digital signal sequence is sent to an MTI module to remove a static target, and FFT conversion is performed through the MTD module to achieve the aim of phase-coherent accumulation. The I, Q two paths of data output by the MTD are input to the CFAR module for constant false alarm processing after power calculation, and information such as whether a target exists or not, the distance and the speed of the target are judged.
After the digital intermediate frequency signal is obtained by sampling, the process converts the intermediate frequency signal into a baseband signal, filters out-of-band noise, and simultaneously performs data extraction to reduce the data stream so as to facilitate subsequent processing. The structure of the digital down-conversion is shown in fig. 1. The A/D sampled digital intermediate frequency signal is used as input, and is mixed with two paths of orthogonal local oscillation signals respectively, so that the signal frequency spectrum is shifted to a baseband; filtering to remove useless information outside the signal frequency band; and finally, extracting is completed, the rate of the signals is reduced to the rate required by the later-stage module, and I, Q two paths of signals are output. In the practical engineering implementation of digital down-conversion, each part in fig. 1 needs to be improved to complete real-time processing in an engineering realizable manner at a processing speed as fast as possible. The improvement mainly has two points: the analog mixing is changed into a digital mode of odd-even extraction, and two groups of 64-order filters are changed into 2 groups of 16-order filters, wherein the two groups of filters are two branches of a multiphase structure. The improved implementation structure is shown in fig. 2. Odd-even alternate sampling is carried out on the intermediate frequency digital signals to form two paths of signals, and symbol correction is carried out respectively; then filtering by using different branches of the polyphase filter respectively; and finally, extracting, and reducing the sampling rate to obtain I, Q two paths of signals.
Pulse compression processes complex signals, while the input of the actual pulse compression network (i.e. the output of digital down-conversion) is I, Q two-way real signals, so the implementation structure and operation flow of pulse compression need to be designed in combination with engineering implementation.
Let the pulse compressed input signal be
x(n)＝I(n)+jQ(n)
The matched filter and the weighting function are combined to be
f(n)＝w(n)·win(n)＝f I (n)+jf Q (n)
The pulse pressure output is
According to the above formula, the pulse compression process is actually a process of filtering four paths of data, and the output result is the sum of the outputs of all paths. The implementation of the pulse pressure network can be designed as the structure of fig. 4. The I path signals respectively pass through a filter f I (n)、f Q (n) the Q signals also pass through the filters f I (n)、f Q (n) one-way and four-way filter outputs are subjected to difference obtaining to obtain I-way signal y of pulse pressure output I (n) summing the outputs of the two-way filter and the three-way filter to obtain Q-way signal y of pulse pressure output Q (n). It should be noted that the two waveforms need to correspond to different filter coefficients, in addition, the pulse compression network uses more multipliers, and a time division multiplexing scheme is needed in engineering, so that the processing speed is sacrificed to a certain extent.
The primary problem with MTI/MTD processing is the data format and data rate at which the radar echo sequence is to be converted. The previous digital down-conversion process and pulse compression process are both processes performed in one PRI, i.e. the fast time domain, whereas the MTI/MTD process is a coherent process requiring it to be performed between bursts, i.e. in the slow time domain. To convert a data stream from a fast time domain to a slow time domain, then a data rearrangement is required. The data rearrangement is required to store data at the same distance of the transmitted echo of each PRI, and the data output mode is output according to adjacent PRIs of the same distance gate of one frame of data. In actual implementation, the data is alternately read and written in a ping-pong operation mode, so that the data is ensured to be processed by MTI/MTD without any loss.
One frame of data in one embodiment of the present invention is 512 PRI; each range gate is known to represent 3.75m, whereas assuming a range of 30.72km for radar, there are 8192 range gates of interest for each PRI after down-conversion. The structure of the ping pong store may be represented by fig. 9.
From the figure, we can see that the whole ping-pong storage is divided into four processes:
1. the 8192 distance units of a single PRI after pulse compression are first stored in cache 1, and when 8192 distance units have been completely stored in cache A in cache 1, then the distance unit of the next PRI is stored in cache B in cache 1 accordingly.
2. While the pulse compression module stores data in cache B of zone 1, data in cache a of zone 1 is transferred to cache a of zone 2. This is repeated until buffer a of zone 2 has completely stored one frame, i.e., 512 PRI data, then the next frame of PRI data transferred from zone 1 will be stored in buffer B of buffer 2.
3. While the 1-zone to 2-zone cache B stores data, the 2-zone cache a transfers data to the 3-zone cache a in units of the same distance of each column, i.e., 512 bursts. Until zone 3 cache a has completed storing the same range gate data for a frame, 512 data for the next range gate will be sent to zone 3 cache B.
4. And when the buffer B in the zone 2 is stored in the buffer B in the zone 3, the data of the buffer A in the zone 3 is sent to the MTI module for processing, and the ping-pong is repeated.
MTI/MTD implementations have been described above and are not described in detail herein.
And detecting the target, namely judging the processed data according to a certain criterion to find the real target and acquire the information of the target, wherein the judgment needs a threshold value as a reference, and serious false alarm or false alarm can occur when the threshold value is unsuitable. The constant false alarm is to adaptively adjust the threshold value along with signals such as background noise and the like, so as to achieve the purpose of ensuring the detection probability and the false alarm rate. Therefore, the key point of the constant false alarm detection is to design a proper judgment criterion and a detection threshold.
Aiming at the actual situation of the warning radar, a two-dimensional constant false alarm detection method based on distance and Doppler is designed, and the implementation flow of the method is shown in figure 8. The method is mainly divided into three parts:
1. calculating power according to the output of the moving target detection;
2. and (3) performing distance dimension detection: taking 16 reference units on the left and right sides of the detection unit, calculating the average power of the reference units to obtain a threshold value 1, judging whether the power of the detection unit is greater than the threshold value 1, if so, performing the step 3, otherwise, judging that the detection unit has no target;
3. and (3) Doppler dimension detection: and taking 16 reference units on the upper part and the lower part of the detection unit, calculating the average power of the reference units to obtain a threshold value 2, judging whether the power of the detection unit is larger than the threshold value 2, if so, judging that the detection unit has a target, and outputting the target amplitude, the target distance, the target speed and the detection state so as to package the later data, otherwise, judging that the detection unit has no target.
The parts of the specification not described in detail are common general knowledge to a person skilled in the art.
Claims (6)
1. The radar digital processing assembly for the ground warning radar is characterized by comprising an analog-to-digital conversion module, a main control module, a storage module and an STC module; wherein:
the analog-to-digital conversion module is used for performing analog-to-digital conversion on the radar echo signal to obtain an intermediate frequency digital signal sequence, and then sending the intermediate frequency digital signal sequence to the main control module;
the main control module carries out digital quadrature down-conversion on the intermediate frequency digital signal sequence to obtain an I-path digital baseband signal and a Q-path digital baseband signal, carries out pulse compression processing on the I-path digital baseband signal and the Q-path digital baseband signal, and removes broadband modulation signals to obtain an I-path narrow pulse echo sequence and a Q-path narrow pulse echo sequence; sequentially storing the I-path narrow pulse echo sequence and the Q-path narrow pulse echo sequence of each pulse repetition period into a storage module according to a distance dimension sequence, taking out and rearranging the I-path narrow pulse echo sequence and the Q-path narrow pulse echo sequence of a plurality of pulse repetition periods from the storage module according to a Doppler dimension sequence to obtain a plurality of pulse sequences of the same distance unit of the plurality of pulse repetition periods, performing moving target display processing on a plurality of pulse data of the same distance unit of the plurality of pulse repetition periods, removing a static target to obtain an I-path moving target display echo sequence and a Q-path moving target display echo sequence, performing moving target detection on the I-path moving target display echo sequence and the Q-path moving target display echo sequence, and performing constant false alarm processing according to a moving target detection result to obtain a target state, a target amplitude, a target distance and a target speed;
the storage module is used for storing the I path narrow pulse echo sequence and the Q path narrow pulse echo sequence;
the STC module adopts a digital-to-analog conversion (DAC) chip and an operational amplification circuit, and adjusts the amplitude of an echo signal received by the receiver by adjusting a voltage-controlled curve;
the main control module comprises a first FPGA module and a second FPGA module;
the first FPGA module is used for carrying out digital quadrature down-conversion on the intermediate frequency digital signal sequence to obtain I, Q two paths of quadrature digital baseband signals, carrying out pulse compression processing on I, Q two paths of quadrature digital baseband signals, removing broadband modulation signals to obtain an I path of narrow pulse echo sequence and a Q path of narrow pulse echo sequence, and sequentially storing the I path of narrow pulse echo sequence and the Q path of narrow pulse echo sequence into the storage module according to a distance dimension sequence;
the second FPGA module is used for taking out and rearranging the I-path narrow pulse echo sequence and the Q-path narrow pulse echo sequence of the pulse repetition periods from the storage module according to the Doppler dimension sequence to obtain a plurality of pulse sequences of the same distance unit of the pulse repetition periods, performing moving target display processing on a plurality of pulse data of the same distance unit of the pulse repetition periods, removing static targets to obtain an I-path moving target display echo sequence and a Q-path moving target display echo sequence, performing moving target detection on the I-path moving target display echo sequence and the Q-path moving target display echo sequence, and performing constant false alarm processing according to the moving target detection result to obtain a target state, a target amplitude, a target distance and a target speed;
the moving target display processing process comprises the following steps:
sequentially taking out the I-path data matrixes of M rows and N columns according to the columns to obtain an I-path rearranged narrow pulse echo sequence;
sequentially taking out the Q paths of data matrixes of M rows and N columns according to the columns to obtain a Q paths of rearranged narrow pulse echo sequence;
the method comprises the steps that after an I-path rearranged narrow pulse echo sequence is subjected to filtering treatment through an I-path filter and a Q-path filter respectively, a first moving target display treatment signal and a second moving target display treatment signal are obtained;
the Q-path rearranged narrow pulse echo sequence is subjected to matching filtering treatment through an I-path filter and a Q-path filter respectively, and then a third moving target display treatment signal and a fourth moving target display treatment signal are obtained;
the first moving target display processing signal and the fourth moving target display processing signal are subjected to difference to obtain an I-path moving target display echo sequence;
and summing the second moving target display processing signal and the third moving target display processing signal to obtain a Q-path moving target display echo sequence.
2. A radar digital processing assembly for a ground-alert radar according to claim 1, wherein the processing of the intermediate frequency digital signal sequence by the first FPGA module by digital quadrature down-conversion is:
odd-even alternate sampling is carried out on the intermediate frequency digital signals to form two paths of intermediate frequency digital signals, and then each path of intermediate frequency digital signals is multiplied by a symbol (-1) in sequence k K is the number of sampling points of each path of intermediate frequency digital signal, and the symbol correction processing is completed; and finally, extracting according to a preset rate to reduce the processing rate of a subsequent processing module, thereby obtaining an I-path digital baseband signal and a Q-path digital baseband signal.
3. A radar digital processing assembly for a ground-alert radar according to claim 1, characterized in that the pulse compression process is:
the I path digital baseband signal is subjected to matched filtering treatment through an I path filter and a Q path filter respectively to obtain a first pulse compression signal and a second pulse compression signal;
the Q paths of digital baseband signals are subjected to matched filtering treatment through an I path filter and a Q path filter respectively to obtain a third pulse compression signal and a fourth pulse compression signal;
the first pulse compression signal and the fourth pulse compression signal are subjected to difference to obtain an I-path narrow pulse echo sequence;
and summing the second pulse compression signal and the third pulse compression signal to obtain a Q-path narrow pulse echo sequence.
4. A radar digital processing assembly for a ground-alert radar according to claim 1, wherein sequentially storing each pulse repetition period I-path narrow pulse echo sequence and Q-path narrow pulse echo sequence in a distance dimension order means:
for M pulse repetition periods received by the ground warning radar, each pulse repetition period corresponds to echo signals of N distance units, an I-path narrow pulse echo sequence and a Q-path narrow pulse echo sequence obtained after pulse compression processing respectively form M rows and N columns of data matrixes, the M rows and the Q-path narrow pulse echo sequences are recorded as an I-path data matrix and a Q-path data matrix, and the I-path data matrix and the Q-path data matrix are respectively stored in a storage module.
5. A radar digital processing assembly for a ground-alert radar according to claim 1, characterized in that the moving-object detection process is:
and (3) performing FFT (fast Fourier transform) on M points on the echo sequence displayed by the I-path moving target and the echo sequence displayed by the Q-path moving target to obtain a pulse sequence after coherent accumulation, namely: an I-path moving target detection echo sequence and a Q-path moving target detection echo sequence.
6. A radar digital processing assembly for a ground-alert radar according to claim 1, characterized in that the constant false alarm processing procedure is:
taking the nth echo sequence element of the mth pulse repetition period I-path moving target detection echo sequence and the mth pulse repetition period Q-path moving target detection echo sequence as detection units, traversing each detection unit and executing the following steps:
(S1) calculating the power of each detection unit according to the I-path moving target detection echo sequence and the Q-path moving target detection echo sequence;
(S2) performing distance dimension detection: taking L detection units in front of and behind the detection unit according to lines, taking the average power of the reference unit as a reference unit, obtaining a first threshold value, judging whether the power of the detection unit is larger than the first threshold value, if so, performing the S3 step, otherwise, judging that the detection unit is in a non-target state, and L is larger than or equal to 1;
(S3) performing doppler detection: taking L detection units in front of and behind the detection unit according to the row, taking the L detection units as reference units, obtaining the average power of the reference units to obtain a second threshold value, judging whether the power of the detection unit is larger than the second threshold value, and judging that the detection unit has a target state if the power of the detection unit is larger than the second threshold value; step (S4) is entered; otherwise, judging that the detection unit has no target, wherein L is more than or equal to 1;
and S4, calculating the target amplitude, the target distance and the target speed according to the distance unit sequence number n and the pulse repetition period sequence number m of the detection unit, and outputting n epsilon [1, N ], m epsilon [1, M ].
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102288941A (en) * | 2011-05-19 | 2011-12-21 | 北京航空航天大学 | Intermediate frequency linear frequency modulation-pulse Doppler (LFM-PD) radar signal real-time processing system based on field programmable gate array (FPGA) and digital signal processor (DSP) and processing method |
| CN205507073U (en) * | 2016-03-30 | 2016-08-24 | 成都信息工程大学 | Weather radar signal processing device based on FPGA |
| CN106814356A (en) * | 2017-01-24 | 2017-06-09 | 成都泰格微电子研究所有限责任公司 | It is a kind of based on Radar Signal Processing System apart from tracing subsystem |
| CN108414991A (en) * | 2018-02-08 | 2018-08-17 | 北京理工大学 | The non-homogeneous clutter scene small objects CFAR detection method of high resolution radar |
| JP2019168255A (en) * | 2018-03-22 | 2019-10-03 | 株式会社東芝 | Pulse compression radar device and radar signal processing method therefor |
| CN111308437A (en) * | 2020-02-27 | 2020-06-19 | 南京慧尔视智能科技有限公司 | Entropy-solving and speed-ambiguity-solving method for millimeter wave MIMO traffic radar |
-
2020
- 2020-11-30 CN CN202011379083.1A patent/CN112558032B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102288941A (en) * | 2011-05-19 | 2011-12-21 | 北京航空航天大学 | Intermediate frequency linear frequency modulation-pulse Doppler (LFM-PD) radar signal real-time processing system based on field programmable gate array (FPGA) and digital signal processor (DSP) and processing method |
| CN205507073U (en) * | 2016-03-30 | 2016-08-24 | 成都信息工程大学 | Weather radar signal processing device based on FPGA |
| CN106814356A (en) * | 2017-01-24 | 2017-06-09 | 成都泰格微电子研究所有限责任公司 | It is a kind of based on Radar Signal Processing System apart from tracing subsystem |
| CN108414991A (en) * | 2018-02-08 | 2018-08-17 | 北京理工大学 | The non-homogeneous clutter scene small objects CFAR detection method of high resolution radar |
| JP2019168255A (en) * | 2018-03-22 | 2019-10-03 | 株式会社東芝 | Pulse compression radar device and radar signal processing method therefor |
| CN111308437A (en) * | 2020-02-27 | 2020-06-19 | 南京慧尔视智能科技有限公司 | Entropy-solving and speed-ambiguity-solving method for millimeter wave MIMO traffic radar |
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