CN103795401A - Output unit circuit with controllable output level - Google Patents
Output unit circuit with controllable output level Download PDFInfo
- Publication number
- CN103795401A CN103795401A CN201410053773.6A CN201410053773A CN103795401A CN 103795401 A CN103795401 A CN 103795401A CN 201410053773 A CN201410053773 A CN 201410053773A CN 103795401 A CN103795401 A CN 103795401A
- Authority
- CN
- China
- Prior art keywords
- circuit
- level
- output
- channel transistor
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The invention relates to an output unit circuit with the controllable output level. The output unit circuit comprises a first-stage level switching circuit, a logical control circuit, a second-stage level switching circuit and an output level. The first-stage level switching circuit is used for carrying out first-stage level switching on an input first data signal and an input enabling signal, the logical control circuit is used for carrying out the logical combination to output a second data signal and a second enabling signal, and outputting a second control signal after the logical phase reversal is carried out on a first control signal, the second-stage level switching circuit is used for carrying out level switching on the second enabling signal and the second control signal which are output by the logical control circuit and outputting a switched level signal, and the output level is used for carrying out level switching and improving the driving capacity of the signal. The output unit circuit has the advantages that a transistor normally works at the normal voltage, the level of the outwards output electric signal can be controlled, and a signal with the high-level voltage or the voltage equal to the rated operational voltage of the transistor can be selectively output to the outside according to requirements. In this way, the area of a chip is saved, power consumption is reduced, and the high application value is achieved.
Description
Technical field
The present invention relates to semiconductor integrated circuit, relate in particular to the controllable output unit circuit of a kind of output level.
Background technology
Along with improving constantly of integrated circuit fabrication process technology, characteristic size is more and more less.Reduce characteristic size, both can reduce the area of chip, also can reduce supply voltage, and then reduce the power consumption of whole chip.Thereby the reduction of dwindling the supply voltage that invariably accompanies of characteristic size, the supply voltage of reduction reduces the power consumption of whole chip.But chip in some system still adopts higher supply voltage as 3.3V or 5V.These chips often different company manufactured and designed in the different time, were difficult in short time complete unity supply voltage standard.In actual applications, different electrical power voltage chip interconnect is with exchange message.Different supply voltages means transistorized characteristic size difference on chip, the transistor voltage endurance capability difference of different characteristic size, and generally speaking, along with feature size downsizing, transistor voltage endurance capability is corresponding reducing also.
For example, the chip of a 5V supply voltage and a 3.3V supply voltage chip interconnect (often running in practical application), 3.3V chip generally adopts 3.3V technique, and in 3.3V chip, transistorized maximum operating voltage is generally no more than 3.6V.In the time that the signal on 5V supply voltage chip sends 3.3V chip to, if design bad, will permanent damage 3.3V transistor or reduce the transistorized life-span.And the signal of 3.3V is passed to 5V power supply chip and is easily caused large leakage of current.These problems are designer's difficult problems always, and for this reason, Many researchers is furtherd investigate this problem.But the research in past mainly concentrates on the I/O unit circuit studies in low pressure complementary metal oxide silicon (CMOS) technique with high input voltage tolerance.That is high-voltage signal sends low pressure process chip to, and time institute runs into security reliability problem, do not have in low pressure process chip, can optionally export report and the research of high-voltage signal or low-voltage signal, cause in current practical application, have to export high-voltage signal and low-voltage signal with high-pressure process, both increase the area of chip, also increased the power consumption of chip.
Summary of the invention
The object of the invention is to overcome the deficiency of above prior art, provides a kind of and can export higher level signal but adopt the output unit circuit of low voltage technique, safe and reliable, specifically has following technical scheme to realize:
The controllable output unit circuit of described output level, comprises
First order level shifting circuit, for carrying out first order level conversion to the first data-signal and the enable signal of input;
Logic control circuit, comprises some logic control devices, for receiving data-signal and the enable signal through first order level conversion, then carries out exporting the first composite signal, the second composite signal and the 3rd composite signal after logical combination; Accept the first control signal, to exporting the second control signal after described the first control signal logical inversion;
Second level level shifting circuit, for first combination, second of logic control circuit output is combined, letter closes, the second control signal is carried out level conversion and export the signal through conversion;
Output stage, for receiving described the 3rd composite signal of the described signal through second level level conversion and logic control circuit output, carries out level conversion and increases the driving force of signal, then export lead-out terminal to.
The further design of described output unit circuit is, described first order level shifting circuit comprises the first level shifting circuit and second electrical level change-over circuit;
Described the first level shifting circuit receives described the first data-signal;
Described second electrical level change-over circuit receives described enable signal;
The first level shifting circuit and second electrical level change-over circuit connect to form by upper trombone slide and lower trombone slide.
The further design of described output unit circuit is, described logic control circuit, comprise the first inverter, the second inverter, the 3rd inverter, NAND gate and NOR gate, two inputs of described NAND gate are connected respectively the output of the first level shifting circuit and second electrical level change-over circuit, one output of NAND gate connects the corresponding input of second level level shifting circuit by the second inverter, another output connects the corresponding input of second level level shifting circuit;
One input of described NOR gate connects the output of second electrical level change-over circuit by the first inverter, another input connects the output of the first level shifting circuit;
The input of described the 3rd inverter is the first control signal input, and output connects respectively the corresponding input of second level level shifting circuit;
Described each inverter, NAND gate and OR-NOT circuit connect to form by upper trombone slide and lower trombone slide.
The further design of described output unit circuit is, described second level level shifting circuit comprises the first level conversion unit and second electrical level converting unit, and described each unit is composed in series by upper trombone slide and drop-down pipe.
The further design of described output unit circuit is, described output-stage circuit is composed in series by upper trombone slide and drop-down pipe.
The further design of described output unit circuit is, described upper trombone slide all adopts p channel transistor, and described lower trombone slide all adopts N channel transistor.
The further design of described output unit circuit is, described the first level shifting circuit and described second electrical level change-over circuit have identical circuit structure, described circuit structure is made up of three parts, p channel transistor p13 and N channel transistor n13 composition Part I, p channel transistor p12 and N channel transistor n12 composition Part II, p channel transistor p11 and N channel transistor n11 composition Part III, p13, the grid of n13 joins and is connected to respectively input terminal and n12 grid, p13, the drain electrode of n13 is connected to respectively the grid of n11, p13, the source electrode of n13 is connected respectively to VDD and ground, p12 grid is connected to lead-out terminal, p12, the drain electrode of n12 is joined and is connected to p11 grid, p12, n12 source electrode is connected respectively to power vd DH and ground, p11, the drain electrode of n11 is joined and is connected to lead-out terminal, p11, the source electrode of n11 is connected respectively to power vd DH and ground.
The further design of described output unit circuit is, described second level level shifting circuit comprises p channel transistor mp1, mp3 and N channel transistor mn1, mn3 is connected in series the first level conversion unit and the p channel transistor mp2 of formation according to this, mp4 and N channel transistor mn2, mn4 is connected in series the second electrical level converting unit of formation according to this, mp1, the source electrode of mp2 joins and is connected to power supply VCC, mp1, the substrate of mp2 joins and is connected to power supply VCC, mp1 grid connects mp2 drain electrode, mp2 grid connects mp1 drain electrode, the source electrode of mp3 and substrate join and are connected to mp1 drain electrode, the grid of mp3 and mp4 joins and is connected in the output of described the 3rd inverter, mp4 source electrode joins with substrate and is connected mp2 drain electrode, mp3 and mp4 drain electrode are connected respectively in the drain electrode of mn1 and mn2, mn1 and mn2 grid join and are connected in power vd DH, mn1 and mn2 source electrode are connected respectively in the drain electrode of mn3 and mn4, mn3 grid connects the output of described NAND gate, mn4 grid connects the output of described the second inverter, the source electrode of mn3 and mn4 joins and ground connection, mn1, mn2, mn3, mn4 substrate joins and ground connection.
The further design of described output unit circuit is, described output-stage circuit comprises p channel transistor mp5, mp6 and N channel transistor mn5, mn6, mp5, mp6, mn5, mn6 is connected in series successively, mp5 source electrode connects power supply VCC, mp5 grid connects the mp2 drain electrode in the level shifting circuit of the described second level, mp5 drain electrode connects mp6 source electrode, mp6 grid is connected to described the 3rd inverter output, mn5, the drain electrode of mp6 is connected to the lead-out terminal of output unit circuit, mp5 joins with the substrate of mp6 and is connected power supply VCC, mn5 grid connects power vd DH, mn5 source electrode connects mn6 drain electrode, mn6 grid connects described the second inverter output, mn5, the substrate of mn6 and mn6 source electrode join and ground connection.
The further design of described output unit circuit is, in described logic control circuit,
The first inverter, the second inverter have identical structure, by p channel transistor p1 and N channel transistor n1 composition, the grid of p1, n1 joins and is connected to the input terminal of corresponding inverter, the drain electrode of p1, n1 is joined and is connected to the lead-out terminal of corresponding inverter, and p1, n1 source electrode are connected respectively power vd DH and ground;
Described the 3rd inverter is made up of p channel transistor p2 and N channel transistor n2, the grid of p2 and n2 joins and is connected to the input terminal of the 3rd inverter, p2 and n2 drain electrode is joined and is connected the lead-out terminal of the 3rd inverter, the source electrode of p2 and n2 be connected respectively power vd D with;
Described NAND gate circuit is made up of three parts, and Part I is made up of p channel transistor p3, p4 and N channel transistor n3, n4; Part II is made up of p channel transistor p5 and N channel transistor n5; Part III is made up of p channel transistor p6 and N channel transistor n6, p3 joins with the grid of n3 and is connected an input terminal of NAND gate circuit, p4 joins with the grid of n4 and is connected another input terminal, p3 joins with the source electrode of p4 and is connected power vd DH, p3 joins with the drain electrode of p4 and is connected n4 drain electrode, n4 source electrode connects n3 drain electrode, n3 source ground; P5 joins with the grid of n5 and is connected n4 drain electrode, the source electrode of p5 and n5 is connected respectively power vd DH and ground, the be connected grid of p6 and n6 of p5 and n5 drain electrode, p6 and n6 source electrode connect respectively VDDH and ground, p6 with n6 drain electrode join and be connected the lead-out terminal of NAND gate circuit;
Described OR-NOT circuit is made up of three parts, and Part I is made up of p channel transistor p7 and p8 and N channel transistor n7 and n8; Part II is made up of p channel transistor p9 and N channel transistor n9; Part III is made up of p channel transistor p10 and N channel transistor n10, P7 grid joins with n7 grid and is connected an input terminal of OR-NOT circuit, p8 joins with the grid of n8 and is connected another input terminal of OR-NOT circuit, p8 source electrode connects power vd DH, p8 drain electrode connects p7 source electrode, p7 drain electrode is connected with the drain electrode of n8, n7, and n8 source electrode and n7 source electrode join and ground connection; P9 connects with the grid of n9 and is connected n7 and drains, the source electrode of p9 and n9 is connected respectively power vd DH and ground, p9 and n9 drain electrode is joined and is connected the grid of p10 and n10, the source electrode of p10 and n10 is connected respectively power vd DH and ground, and p10 joins with the drain electrode of n10 and is connected the lead-out terminal of OR-NOT circuit.
Advantage of the present invention is as follows:
Output unit circuit provided by the invention adopts low-voltage technique, transistor is normally worked under rated voltage, do not damaging under condition in transistorized useful life, can control the level of outside output electrical signals, selecting as required has high level voltage signal or equals transistor rated operational voltage signal to extraneous output device.Do like this saving chip area on the one hand, reduce on the other hand power consumption, value has a wide range of applications.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the controllable output unit circuit of described output level.
Fig. 2 is the circuit diagram of described the first level shifting circuit LS1 and second electrical level change-over circuit LS2.
Fig. 3 is described the first inverter T3 and the second inverter T4 circuit diagram.
Fig. 4 is described NAND gate T1 circuit diagram.
Fig. 5 is described NOR gate T2 circuit diagram.
Fig. 6 is described the 3rd inverter T5 circuit diagram.
Embodiment
Below in conjunction with accompanying drawing, the present invention program is elaborated.
Contrast Fig. 1, the controllable output unit circuit of output level that the present embodiment provides comprises: first order level shifting circuit 10, logic control circuit 20, second level level shifting circuit 30 and output stage 40.First order level shifting circuit, logic control circuit, second level level shifting circuit is connected successively with output-stage circuit.First order level shifting circuit, for carrying out first order level conversion to the first data-signal and the enable signal of input.Logic control circuit, comprises some logic control devices, for receiving data-signal and the enable signal through first order level conversion, then carry out after logical combination exporting the first composite signal, the second combination letter closes and the 3rd composite signal; Meanwhile, accept the first control signal, to exporting the second control signal after the first control signal logical inversion.Second level level shifting circuit, for carrying out level conversion the output signal through level conversion to the first composite signal, the second composite signal, second control signal of logic control circuit output.Output stage, for receiving the 3rd composite signal through the voltage signal of second level level conversion and logic control circuit output, carries out level conversion and increases the driving force of signal, then export lead-out terminal to.
The controllable output unit circuit of output level that the present embodiment provides comprises three input terminal DIN, OE and LOV and a lead-out terminal PAD.Input DIN is data-signal input, and input OE is for enabling control signal input, and when enabling control signal OE while being logic high, this output unit circuit outputs to outside by output PAD by input data-signal DIN; When enabling control signal OE while being logic low, output PAD is high-impedance state.Input LOV is output level control signal input, LOV fetch logic low level in the time that supply voltage VCC is greater than VDDH, LOV fetch logic high level in the time that VCC equals VDDH.In the time that output level control signal LOV is logic high, output PAD is GND-VDDH data-signal to outside output voltage swing; In the time that output level control signal LOV is logic low, output PAD is GND-VCC data-signal to outside output voltage swing.Lead-out terminal PAD is data-signal output.
Contrast Fig. 1, the controllable output unit circuit of output level that the present embodiment provides comprises three DC power supply, is respectively VDD, VDDH and VCC.Vdd voltage value minimum, VCC magnitude of voltage maximum, VDDH magnitude of voltage is between VDD and VCC.Wherein the magnitude of voltage of power vd D is recommended as the high level voltage value of input signal DIN, the magnitude of voltage of power vd DH is recommended as the load voltage value of the normal work of described input stage transistor mn5 and mp5, the magnitude of voltage of power supply VCC be recommended as be not more than VDD and VDDH with.
First order level shifting circuit comprises the first level shifting circuit and second electrical level change-over circuit.The first level shifting circuit receives the first data-signal, i.e. the input signal of DIN terminal.Second electrical level change-over circuit receives enable signal, the i.e. input signal of OE terminal.The first level shifting circuit and second electrical level change-over circuit have identical circuit structure, circuit structure is made up of three parts, p channel transistor p13 and N channel transistor n13 composition Part I, p channel transistor p12 and N channel transistor n12 composition Part II, p channel transistor p11 and N channel transistor n11 composition Part III, p13, the grid of n13 joins and is connected to respectively input terminal and n12 grid, p13, the drain electrode of n13 is connected to respectively the grid of n11, p13, the source electrode of n13 is connected respectively to VDD and ground, p12 grid is connected to lead-out terminal, p12, the drain electrode of n12 is joined and is connected to p11 grid, p12, n12 source electrode is connected respectively to power vd DH and ground, p11, the drain electrode of n11 is joined and is connected to lead-out terminal, p11, the source electrode of n11 is connected respectively to power vd DH and ground.
Logic control circuit comprises the first inverter, the second inverter, the 3rd inverter, NAND gate and NOR gate, two inputs of NAND gate are connected respectively the output of the first level shifting circuit and second electrical level change-over circuit, one output of NAND gate connects the corresponding input of second level level shifting circuit by the second inverter, another output connects the corresponding input of second level level shifting circuit.One input of NOR gate connects the output of second electrical level change-over circuit by the first inverter, another input connects the output of the first level shifting circuit.The input of the 3rd inverter is the first control signal input, and output connects respectively the corresponding input of second level level shifting circuit.Each inverter, NAND gate and OR-NOT circuit connect to form by upper trombone slide and lower trombone slide.
Wherein, the first inverter, the second inverter have identical structure, and by p channel transistor p1 and N channel transistor n1 composition, the grid of p1, n1 joins and is connected to the input terminal OUT of corresponding inverter.The drain electrode of p1, n1 is joined and is connected to the lead-out terminal of corresponding inverter, and p1, n1 source electrode are connected respectively power vd DH and ground, referring to Fig. 3.The 3rd inverter is made up of p channel transistor p2 and N channel transistor n2, the grid of p2 and n2 joins and is connected to the input terminal of the 3rd inverter, p2 and n2 drain electrode is joined and is connected the lead-out terminal OUT of the 3rd inverter, the source electrode of p2 and n2 is connected respectively power vd D and ground, referring to Fig. 6.
NAND gate circuit is made up of three parts, referring to Fig. 4.Part I is made up of p channel transistor p3, p4 and N channel transistor n3, n4.Part II is made up of p channel transistor p5 and N channel transistor n5.Part III is made up of p channel transistor p6 and N channel transistor n6.P3 joins with the grid of n3 and is connected an input terminal of NAND gate circuit, p4 joins with the grid of n4 and is connected another input terminal, and p3 joins with the source electrode of p4 and is connected power vd DH, and p3 joins with the drain electrode of p4 and is connected n4 drain electrode, n4 source electrode connects n3 drain electrode, n3 source ground; P5 joins with the grid of n5 and is connected n4 drain electrode, the source electrode of p5 and n5 is connected respectively power vd DH and ground, the be connected grid of p6 and n6 of p5 and n5 drain electrode, p6 and n6 source electrode connect respectively VDDH and ground, p6 with n6 drain electrode join and be connected the lead-out terminal of NAND gate circuit.
OR-NOT circuit is made up of three parts, referring to Fig. 5.Part I is made up of p channel transistor p7 and p8 and N channel transistor n7 and n8.Part II is made up of p channel transistor p9 and N channel transistor n9.Part III is made up of p channel transistor p10 and N channel transistor n10.P7 grid joins with n7 grid and is connected an input terminal of OR-NOT circuit, and p8 joins with the grid of n8 and is connected another input terminal of OR-NOT circuit.P8 source electrode connects power vd DH, and p8 drain electrode connects p7 source electrode, and p7 drain electrode is connected with the drain electrode of n8, n7, and n8 source electrode and n7 source electrode join and ground connection.P9 connects with the grid of n9 and is connected n7 and drains, the source electrode of p9 and n9 is connected respectively power vd DH and ground, p9 and n9 drain electrode is joined and is connected the grid of p10 and n10, the source electrode of p10 and n10 is connected respectively power vd DH and ground, and p10 joins with the drain electrode of n10 and is connected the lead-out terminal of OR-NOT circuit.
Second level level shifting circuit, comprises the first level conversion unit and second electrical level converting unit, and each unit connects to form by upper trombone slide and drop-down pipe string connection.Second level level shifting circuit comprises p channel transistor mp1, mp3 and N channel transistor mn1, mn3 is connected in series the first level conversion unit and the p channel transistor mp2 of formation according to this, mp4 and N channel transistor mn2, mn4 is connected in series the second electrical level converting unit of formation according to this, mp1, the source electrode of mp2 joins and is connected to power supply VCC, mp1, the substrate of mp2 joins and is connected to power supply VCC, mp1 grid connects mp2 drain electrode, mp2 grid connects mp1 drain electrode, the source electrode of mp3 and substrate join and are connected to mp1 drain electrode, the grid of mp3 and mp4 joins and is connected in the output of the 3rd inverter, mp4 source electrode joins with substrate and is connected mp2 drain electrode, mp3 and mp4 drain electrode are connected respectively in the drain electrode of mn1 and mn2, mn1 and mn2 grid join and are connected in power vd DH, mn1 and mn2 source electrode are connected respectively in the drain electrode of mn3 and mn4, mn3 grid connects the output of NAND gate, mn4 grid connects the output of the second inverter, the source electrode of mn3 and mn4 joins and ground connection, mn1, mn2, mn3, mn4 substrate joins and ground connection.
Output-stage circuit is composed in series by upper trombone slide and drop-down pipe.Output-stage circuit comprises p channel transistor mp5, mp6 and N channel transistor mn5, mn6, mp5, mp6, mn5, mn6 is connected in series successively, mp5 source electrode connects power supply VCC, mp5 grid connects the mp2 drain electrode in the level shifting circuit of the second level, mp5 drain electrode connects mp6 source electrode, mp6 grid is connected to the 3rd inverter output, mn5, the drain electrode of mp6 is connected to the lead-out terminal of output unit circuit, mp5 joins with the substrate of mp6 and is connected power supply VCC, mn5 grid connects power vd DH, mn5 source electrode connects mn6 drain electrode, mn6 grid connects the second inverter output, mn5, the substrate of mn6 and mn6 source electrode join and ground connection.
In the present embodiment, adopt Dual Gate Oxide cmos standard technology, upper trombone slide all adopts p channel transistor, and described lower trombone slide all adopts N channel transistor.Contrast Fig. 2, wherein transistor p11, p12, n11 and n12 adopt thick grid oxygen transistor; And transistor n13 and p13 adopt thin grid oxygen transistor.Contrast Fig. 3, transistor p1 and n1 adopt thick grid oxygen transistor; Contrast Fig. 4, wherein transistor p3, p4, p5, p6, n3, n4, n5 and n6 adopt thick grid oxygen transistor; Contrast Fig. 5, wherein transistor p7, p8, p9, p10, n7, n8, n9 and n10 adopt thick grid oxygen transistor; Contrast Fig. 6, transistor p2 and n2 adopt thin grid oxygen transistor.Wherein thin grid oxygen transistor is operated in the scope of voltage VDD, and the recommended work of thick grid oxygen transistor is in the scope of voltage VDDH.Contrast Fig. 1, transistor mp1, mp2, mp3, mp4, mp5, mp6, mn1, mn2, mn3, mn4, mn5 and mn6 adopt thick grid oxygen transistor.
Contrast Fig. 1, the controllable output unit circuit working of the output level principle that the present embodiment provides is: all input signal amplitudes of oscillation are GND-VDD, when input control signal OE is that logic high is VDD, the signal VDD of OE is converted to VDDH by second electrical level change-over circuit LS2 and makes the outside outputting data signals DIN of described output circuit, the input signal amplitude of oscillation of DIN is GND-VDD, being converted to the amplitude of oscillation through the first level shifting circuit LS1 is that the signal of GND-VDDH passes to second level level shifting circuit, when the magnitude of voltage of power supply VCC is greater than power vd DH, it is that the signal of VDD-VCC is exported to described output stage that the signal that second level level shifting circuit is GND-VDDH by the amplitude of oscillation is converted to the amplitude of oscillation, being converted to the amplitude of oscillation through output stage is again that the output signal of GND-VCC is exported to outside.When the magnitude of voltage of power supply VCC equals power vd DH, it is that the signal of GND-VCC is exported to described output stage that the signal that second level level shifting circuit is GND-VDDH by the amplitude of oscillation is converted to the amplitude of oscillation, then to remain the amplitude of oscillation through output stage be that the output signal of GND-VCC is exported to outside.
Take 0.18um-1.8V/3.3V technique as embodiment, power vd D is 1.8V, and VDDH is 3.3V, and VCC is 3.3V or 5V. contrast Fig. 1, transistor mp1, and mp2, mp3, mp4, mp5, mp6, mn1, mn2, mn3, mn4, mn5 and mn6 adopt 3.3V transistor.Contrast Fig. 2, wherein transistor p11, p12, n11 and n12 adopt 3.3V transistor; And transistor n13 and p13 adopt 1.8V transistor.Contrast Fig. 3, transistor p1 and n1 adopt 3.3V transistor; Contrast Fig. 4, transistor p3, p4, p5, p6, n3, n4, n5 and n6 adopt 3.3V transistor; Contrast Fig. 5, transistor p7, p8, p9, p10, n7, n8, n9 and n10 adopt 3.3V transistor; Contrast Fig. 6, transistor p2 and n2 adopt 1.8V transistor.
In the time that power supply VCC is 5V, input signal LOV is logic low 0, be that logic high is 1.8V when enabling control signal OE, the input signal amplitude of oscillation of DIN is 0-1.8V, being converted to the amplitude of oscillation through the first level shifting circuit LS1 is that the signal of 0-3.3V passes to second level level shifting circuit, it is that the signal of 1.8-5V is exported to described output stage that the signal that second level level shifting circuit is 0-3.3V by the amplitude of oscillation is converted to the amplitude of oscillation, then to be converted to the amplitude of oscillation through output stage be that the output signal of 0-5V is exported to outside.
When the magnitude of voltage of power supply VCC equals 3.3V, input signal LOV is logic low and high level 1.8V, be that logic high is 1.8V when enabling control signal OE, the input signal amplitude of oscillation of DIN is 0-1.8V, being converted to the amplitude of oscillation through the first level shifting circuit LS1 is that the signal of 0-3.3V passes to second level level shifting circuit, it is that the signal of 0-3.3V is exported to described output stage that the signal that second level level shifting circuit is 0-3.3V by the amplitude of oscillation remains the amplitude of oscillation, then strengthens through output stage the output signal that the backward outside output voltage swing of actuating force is 0-3.3V.
The output unit circuit that the present embodiment provides adopts low-voltage technique, transistor is normally worked under rated voltage, do not damaging under condition in transistorized useful life, can control the level of outside output electrical signals, selecting as required has high level voltage signal or equals transistor rated operational voltage signal to extraneous output device.Do like this saving chip area on the one hand, reduce on the other hand power consumption, value has a wide range of applications.
Claims (10)
1. the controllable output unit circuit of output level, is characterized in that comprising
First order level shifting circuit, for carrying out first order level conversion to the first data-signal and the enable signal of input;
Logic control circuit, comprises some logic control devices, for receiving data-signal and the enable signal through first order level conversion, then carries out exporting the first composite signal, the second composite signal and the 3rd composite signal after logical combination; Accept the first control signal, to exporting the second control signal after described the first control signal logical inversion;
Second level level shifting circuit, for carrying out level conversion the output signal through level conversion to the first composite signal, the second composite signal, second control signal of logic control circuit output;
Output stage, for receiving described the 3rd composite signal of the described signal through second level level conversion and logic control circuit output, carries out level conversion and increases the driving force of signal, then export lead-out terminal to.
2. output unit circuit according to claim 1, is characterized in that described first order level shifting circuit comprises the first level shifting circuit and second electrical level change-over circuit;
Described the first level shifting circuit receives described the first data-signal;
Described second electrical level change-over circuit receives described enable signal;
The first level shifting circuit and second electrical level change-over circuit connect to form by upper trombone slide and lower trombone slide.
3. output unit circuit according to claim 1, it is characterized in that described logic control circuit, comprise the first inverter, the second inverter, the 3rd inverter, NAND gate and NOR gate, two inputs of described NAND gate are connected respectively the output of the first level shifting circuit and second electrical level change-over circuit, one output of NAND gate connects the corresponding input of second level level shifting circuit by the second inverter, another output connects the corresponding input of second level level shifting circuit;
One input of described NOR gate connects the output of second electrical level change-over circuit by the first inverter, another input connects the output of the first level shifting circuit;
The input of described the 3rd inverter is the first control signal input, and output connects respectively the corresponding input of second level level shifting circuit;
Described each inverter, NAND gate and OR-NOT circuit connect to form by upper trombone slide and lower trombone slide.
4. output unit circuit according to claim 1, is characterized in that described second level level shifting circuit, comprises the first level conversion unit and second electrical level converting unit, and described each unit connects to form by upper trombone slide and lower trombone slide.
5. output unit circuit according to claim 1, is characterized in that described output-stage circuit is composed in series by upper trombone slide and drop-down pipe.
6. according to the output unit circuit described in any one of claim 2-5, it is characterized in that described upper trombone slide all adopts p channel transistor, described lower trombone slide all adopts N channel transistor.
7. output unit circuit according to claim 6, it is characterized in that described the first level shifting circuit and described second electrical level change-over circuit have identical circuit structure, described circuit structure is made up of three parts, p channel transistor p13 and N channel transistor n13 composition Part I, p channel transistor p12 and N channel transistor n12 composition Part II, p channel transistor p11 and N channel transistor n11 composition Part III, p13, the grid of n13 joins and is connected to respectively input terminal and n12 grid, p13, the drain electrode of n13 is connected to respectively the grid of n11, p13, the source electrode of n13 is connected respectively to VDD and ground, p12 grid is connected to lead-out terminal, p12, the drain electrode of n12 is joined and is connected to p11 grid, p12, n12 source electrode is connected respectively to power vd DH and ground, p11, the drain electrode of n11 is joined and is connected to lead-out terminal, p11, the source electrode of n11 is connected respectively to power vd DH and ground.
8. output unit circuit according to claim 6, it is characterized in that described second level level shifting circuit comprises p channel transistor mp1, mp3 and N channel transistor mn1, mn3 is connected in series the first level conversion unit and the p channel transistor mp2 of formation according to this, mp4 and N channel transistor mn2, mn4 is connected in series the second electrical level converting unit of formation according to this, mp1, the source electrode of mp2 joins and is connected to power supply VCC, mp1, the substrate of mp2 joins and is connected to power supply VCC, mp1 grid connects mp2 drain electrode, mp2 grid connects mp1 drain electrode, the source electrode of mp3 and substrate join and are connected to mp1 drain electrode, the grid of mp3 and mp4 joins and is connected in the output of described the 3rd inverter, mp4 source electrode joins with substrate and is connected mp2 drain electrode, mp3 and mp4 drain electrode are connected respectively in the drain electrode of mn1 and mn2, mn1 and mn2 grid join and are connected in power vd DH, mn1 and mn2 source electrode are connected respectively in the drain electrode of mn3 and mn4, mn3 grid connects the output of described NAND gate, mn4 grid connects the output of described the second inverter, the source electrode of mn3 and mn4 joins and ground connection, mn1, mn2, mn3, mn4 substrate connects and ground connection.
9. output unit circuit according to claim 6, it is characterized in that described output-stage circuit comprises p channel transistor mp5, mp6 and N channel transistor mn5, mn6, mp5, mp6, mn5, mn6 is connected in series successively, mp5 source electrode connects power supply VCC, mp5 grid connects the mp2 drain electrode in the level shifting circuit of the described second level, mp5 drain electrode connects mp6 source electrode, mp6 grid is connected to described the 3rd inverter output, mn5, the drain electrode of mp6 is connected to the lead-out terminal of output unit circuit, mp5 joins with the substrate of mp6 and is connected power supply VCC, mn5 grid connects power vd DH, mn5 source electrode connects mn6 drain electrode, mn6 grid connects described the second inverter output, mn5, the substrate of mn6 and mn6 source electrode join and ground connection.
10. output unit circuit according to claim 6, is characterized in that in described logic control circuit,
The first inverter, the second inverter have identical structure, by p channel transistor p1 and N channel transistor n1 composition, the grid of p1, n1 joins and is connected to the input terminal of corresponding inverter, the drain electrode of p1, n1 is joined and is connected to the lead-out terminal of corresponding inverter, and p1, n1 source electrode are connected respectively power vd DH and ground;
Described the 3rd inverter is made up of p channel transistor p2 and N channel transistor n2, the grid of p2 and n2 joins and is connected to the input terminal of the 3rd inverter, p2 and n2 drain electrode is joined and is connected the lead-out terminal of the 3rd inverter, the source electrode of p2 and n2 be connected respectively power vd D with;
Described NAND gate circuit is made up of three parts, and Part I is made up of p channel transistor p3, p4 and N channel transistor n3, n4; Part II is made up of p channel transistor p5 and N channel transistor n5; Part III is made up of p channel transistor p6 and N channel transistor n6, p3 joins with the grid of n3 and is connected an input terminal of NAND gate circuit, p4 joins with the grid of n4 and is connected another input terminal, p3 joins with the source electrode of p4 and is connected power vd DH, p3 joins with the drain electrode of p4 and is connected n4 drain electrode, n4 source electrode connects n3 drain electrode, n3 source ground; P5 joins with the grid of n5 and is connected n4 drain electrode, the source electrode of p5 and n5 is connected respectively power vd DH and ground, the be connected grid of p6 and n6 of p5 and n5 drain electrode, p6 and n6 source electrode connect respectively VDDH and ground, p6 with n6 drain electrode join and be connected the lead-out terminal of NAND gate circuit;
Described OR-NOT circuit is made up of three parts, and Part I is made up of p channel transistor p7 and p8 and N channel transistor n7 and n8; Part II is made up of p channel transistor p9 and N channel transistor n9; Part III is made up of p channel transistor p10 and N channel transistor n10, P7 grid joins with n7 grid and is connected an input terminal of OR-NOT circuit, p8 joins with the grid of n8 and is connected another input terminal of OR-NOT circuit, p8 source electrode connects power vd DH, p8 drain electrode connects p7 source electrode, p7 drain electrode is connected with the drain electrode of n8, n7, and n8 source electrode and n7 source electrode join and ground connection; P9 connects with the grid of n9 and is connected n7 and drains, the source electrode of p9 and n9 is connected respectively power vd DH and ground, p9 and n9 drain electrode is joined and is connected the grid of p10 and n10, the source electrode of p10 and n10 is connected respectively power vd DH and ground, and p10 joins with the drain electrode of n10 and is connected the lead-out terminal of OR-NOT circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410053773.6A CN103795401A (en) | 2014-02-18 | 2014-02-18 | Output unit circuit with controllable output level |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410053773.6A CN103795401A (en) | 2014-02-18 | 2014-02-18 | Output unit circuit with controllable output level |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103795401A true CN103795401A (en) | 2014-05-14 |
Family
ID=50670766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410053773.6A Pending CN103795401A (en) | 2014-02-18 | 2014-02-18 | Output unit circuit with controllable output level |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103795401A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104505118A (en) * | 2014-12-18 | 2015-04-08 | 西安华芯半导体有限公司 | Electrical level converter for high-speed dynamic random access memory (DRAM) |
| CN104883181A (en) * | 2015-06-10 | 2015-09-02 | 京东方科技集团股份有限公司 | NOR gate circuit, shift register, array substrate, and display apparatus |
| CN107204768A (en) * | 2017-06-12 | 2017-09-26 | 成都锐成芯微科技股份有限公司 | High Pressure Difference level shifting circuit and method |
| CN108597473A (en) * | 2018-07-27 | 2018-09-28 | 上海芯北电子科技有限公司 | A kind of voltage commutation circuit and method for lattice lcd driving chip |
| CN110739961A (en) * | 2019-10-21 | 2020-01-31 | 上海华虹宏力半导体制造有限公司 | Level shifter |
| CN112311379A (en) * | 2019-12-17 | 2021-02-02 | 成都华微电子科技有限公司 | CML level to CMOS logic level conversion circuit |
| WO2023115888A1 (en) * | 2021-12-22 | 2023-06-29 | 无锡中微亿芯有限公司 | Logic process-based level translation circuit of flash-based fpga |
| US12015404B2 (en) | 2021-12-22 | 2024-06-18 | Wuxi Esiontech Co., Ltd. | Logic process-based level conversion circuit of flash field programmable gate array (FPGA) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136408A (en) * | 2007-09-14 | 2008-03-05 | 北京大学 | CMOS circuit based on semi-conductor nano material and preparation therefor |
| CN101976940A (en) * | 2010-10-12 | 2011-02-16 | 上海交通大学 | Drive bootstrap circuit for switching tube of switching power supply converter |
| CN102270984A (en) * | 2011-07-01 | 2011-12-07 | 清华大学 | Positive high voltage level conversion circuit |
| CN102521176A (en) * | 2011-12-01 | 2012-06-27 | 深圳市国微电子股份有限公司 | Input output (IO) interface output circuit in microprocessor |
| CN103066990A (en) * | 2013-01-16 | 2013-04-24 | 南通大学 | Output unit circuit based on integrated circuit |
-
2014
- 2014-02-18 CN CN201410053773.6A patent/CN103795401A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136408A (en) * | 2007-09-14 | 2008-03-05 | 北京大学 | CMOS circuit based on semi-conductor nano material and preparation therefor |
| CN101976940A (en) * | 2010-10-12 | 2011-02-16 | 上海交通大学 | Drive bootstrap circuit for switching tube of switching power supply converter |
| CN102270984A (en) * | 2011-07-01 | 2011-12-07 | 清华大学 | Positive high voltage level conversion circuit |
| CN102521176A (en) * | 2011-12-01 | 2012-06-27 | 深圳市国微电子股份有限公司 | Input output (IO) interface output circuit in microprocessor |
| CN103066990A (en) * | 2013-01-16 | 2013-04-24 | 南通大学 | Output unit circuit based on integrated circuit |
Non-Patent Citations (1)
| Title |
|---|
| 电源网: "电路常识性概念之MOS管及简单CMOS逻辑门电路原理", 《HTTP://WWW.EEWORLD.COM.CN/DYGL/2013/1227/ARTICLE_19764_1.HTML》, 27 December 2013 (2013-12-27) * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104505118A (en) * | 2014-12-18 | 2015-04-08 | 西安华芯半导体有限公司 | Electrical level converter for high-speed dynamic random access memory (DRAM) |
| CN104883181A (en) * | 2015-06-10 | 2015-09-02 | 京东方科技集团股份有限公司 | NOR gate circuit, shift register, array substrate, and display apparatus |
| WO2016197523A1 (en) * | 2015-06-10 | 2016-12-15 | 京东方科技集团股份有限公司 | Nor gate circuit, shift register, array substrate and display device |
| CN104883181B (en) * | 2015-06-10 | 2018-03-16 | 京东方科技集团股份有限公司 | OR-NOT circuit, shift register, array base palte and display device |
| US10027329B2 (en) | 2015-06-10 | 2018-07-17 | Boe Technology Group Co., Ltd. | NOR gate circuit, shift register, array substrate and display apparatus |
| CN107204768A (en) * | 2017-06-12 | 2017-09-26 | 成都锐成芯微科技股份有限公司 | High Pressure Difference level shifting circuit and method |
| CN108597473A (en) * | 2018-07-27 | 2018-09-28 | 上海芯北电子科技有限公司 | A kind of voltage commutation circuit and method for lattice lcd driving chip |
| CN108597473B (en) * | 2018-07-27 | 2023-08-18 | 上海芯北电子科技有限公司 | Voltage switching circuit and method for dot matrix liquid crystal driving chip |
| CN110739961A (en) * | 2019-10-21 | 2020-01-31 | 上海华虹宏力半导体制造有限公司 | Level shifter |
| CN110739961B (en) * | 2019-10-21 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Level shifter |
| CN112311379A (en) * | 2019-12-17 | 2021-02-02 | 成都华微电子科技有限公司 | CML level to CMOS logic level conversion circuit |
| WO2023115888A1 (en) * | 2021-12-22 | 2023-06-29 | 无锡中微亿芯有限公司 | Logic process-based level translation circuit of flash-based fpga |
| US12015404B2 (en) | 2021-12-22 | 2024-06-18 | Wuxi Esiontech Co., Ltd. | Logic process-based level conversion circuit of flash field programmable gate array (FPGA) |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103795401A (en) | Output unit circuit with controllable output level | |
| CN101969305B (en) | Potential conversion circuit | |
| CN106230416B (en) | It is a kind of with active clamp without bootstrapping gate driving circuit | |
| CN103259521B (en) | High Speed Level Shifter with Low Input Voltage to Wide Range High Output Voltage | |
| CN107947784A (en) | A kind of high-performance output driving circuit | |
| CN101420224B (en) | Output buffer circuit | |
| CN104124957B (en) | Level switching circuit | |
| CN108616269B (en) | Low-working-voltage downlink level shift circuit | |
| CN108155903A (en) | High speed and high pressure level shifting circuit applied to GaN gate drivings | |
| CN107222196A (en) | Semiconductor devices | |
| CN102208909A (en) | Level shift circuit | |
| CN103066990A (en) | Output unit circuit based on integrated circuit | |
| WO2020147306A1 (en) | Withstand voltage level conversion circuit | |
| CN109428567A (en) | A kind of device for realizing duty ratio adjustment | |
| CN101866635A (en) | Transformer | |
| CN109933120A (en) | A kind of voltage commutation circuit and chip | |
| CN206595983U (en) | Level conversion drive circuit | |
| CN105577165B (en) | A kind of I/O interface level shifting circuit and I/O interface level conversion method | |
| CN105375916A (en) | Improved XOR gate logic unit circuit | |
| CN208401821U (en) | A kind of downlink level shift circuit of low-work voltage | |
| CN104702268B (en) | The circuit that voltage buffer circuit and driving load with it switch with sequential | |
| CN106059516A (en) | Rail-to-rail operational amplifier circuit, ADC converter, DCDC converter and power amplifier | |
| CN103098375A (en) | Controlled switch | |
| CN209517097U (en) | Pressure-resistant level shifting circuit | |
| TW201440402A (en) | Voltage conversion device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140514 |
|
| RJ01 | Rejection of invention patent application after publication |