CN102270660B - 沟槽型金属氧化物半导体场效应晶体管形成方法 - Google Patents

沟槽型金属氧化物半导体场效应晶体管形成方法 Download PDF

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CN102270660B
CN102270660B CN201010552507.XA CN201010552507A CN102270660B CN 102270660 B CN102270660 B CN 102270660B CN 201010552507 A CN201010552507 A CN 201010552507A CN 102270660 B CN102270660 B CN 102270660B
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substrate
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trench mosfet
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亚历山大·卡尼斯基
段孝勤
吴国铭
黄伟宗
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种位于基板上的沟槽型金属氧化物半导体场效应晶体管结构及其形成方法，其采用自对准接触物因而可降低沟槽型金属氧化物半导体场效应晶体管的间距尺寸。该晶体管结构包括：第一沟槽与第二沟槽，位于基板上，第一沟槽与第二沟槽衬覆有栅极介电层并为栅极多晶硅所填满；自对准源极接触物，位于第一沟槽与第二沟槽之间，自对准源极接触物连接于源极金属；栅极接触物，位于沟槽之上，沟槽接触物连接于栅极金属与位于第一沟槽内的栅极多晶硅；源极区，环绕自对准源极接触物，其中源极区具有凸出形态。上述自对准接触物借由蚀刻露出的硅区域而形成，无须使用光刻光掩模与对准情形。因而可免除对准容忍度并可降低间距尺寸。

Description

沟槽型金属氧化物半导体场效应晶体管形成方法
技术领域
本发明涉及沟槽型金属氧化物半导体场效应晶体管(trench MOSFET)结构及其形成方法，尤其涉及具有自对准接触物(self-aligned contacts)的沟槽型金属氧化物半导体场效应晶体管。 
背景技术
半导体集成电路工业已经历了快速成长。随着集成电路材料及设计等技术的演进，目前已制作出了数个世代的集成电路，而每一世代均较前一世代具有更小且更为复杂的电路。如此的演进增加了集成电路的制作与工艺的困难度与挑战。 
垂直型传导沟槽型金属氧化物半导体场效应晶体管(vertically-conducting MOSFETs)可用于电源电子学中(power electronics)。当一沟槽型金属氧化物半导体场效应晶体管于开启状态(on state)时经偏压，电流垂直地流经了源极区与基板。金属氧化物半导体场效应晶体管间的胞距(cell pitch)的降低对于降低元件尺寸以及增加于一半导体晶片上的有源装置数量极为有效。此外，胞距也影响了元件表现，如当元件于开启时介于源极与漏极之间的电阻值(Rdson)。元件间距的降低受限于工艺技术，例如为光刻机台对于最小临界尺寸以及不同图案膜层间的对准的处理能力。将借由下文加以解说上述限制。 
发明内容
为了解决现有技术的问题，本发明提供了位于基板上的沟槽型金属氧化物半导体场效应晶体管结构及其形成方法。 
于一实施例中，本发明提供了一种位于基板上的沟槽型金属氧化物半导体场效应晶体管结构，包括： 
一第一沟槽与一第二沟槽，位于该基板上，其中该第一沟槽与该第二沟 槽衬覆有一栅极介电层并为一栅极多晶硅所填满；一自对准源极接触物，位于该第一沟槽与该第二沟槽之间，其中该自对准源极接触物连接于一源极金属；一栅极接触物，位于该沟槽之上，其中该沟槽接触物连接于一栅极金属与位于该第一沟槽内的该栅极多晶硅；以及一源极区，环绕该自对准源极接触物，其中该源极区具有一凸出形态。 
于另一实施例中，本发明提供了一种位于基板上的沟槽型金属氧化物半导体场效应晶体管结构，包括： 
位于该基板上的一第一沟槽、一第二沟槽与一第三沟槽，其中该第一沟槽、该第二沟槽与该第三沟槽衬覆有一栅极介电层并为栅极多晶硅所填满；一第一自对准源极接触物，位于该第一沟槽与该第二沟槽之间，以及一第二自对准源极接触物，位于该第二沟槽与该第三沟槽之间，其中该第一自对准源极接触物与该第二自对准源极接触物均连接于一源极金属；一栅极接触物，位于该第一沟槽之上，其中该栅极接触物连接于一栅极金属以及位于该第一沟槽内的该栅极多晶硅；以及一第一源极区环绕该第一自对准源极接触物以及一第二源极区环绕该第二自对准源极接触物，其中该第一源极区与该第二源极区具有一凸出形态。 
于又一实施例中，本发明提供了一种位于基板上的沟槽型金属氧化物半导体场效应晶体管结构的形成方法，包括： 
蚀刻该基板以形成具有一硬掩模层的多个沟槽；于所述多个沟槽内衬覆一栅极氧化物层；于所述多个沟槽内填满经掺杂多晶硅；回蚀刻位于所述多个沟槽内的该经掺杂多晶硅至低于所述多个沟槽的顶面；于经过回蚀刻该经掺杂多晶硅后，沉积一介电层于该基板之上，其中该介电层于所述多个沟槽内的所述多个侧壁上具有一最小沉积；施行一湿氧化物蚀刻以移除位于所述多个沟槽的所述多个侧壁上的该介电层，以露出所述多个沟槽的所述多个侧壁上的硅；施行一各向同性硅蚀刻，以底切位于该硬掩模层下方的硅，其中形成了高于所述多个沟槽的所述多个空间以及该硬掩模层下方借由该各向同性硅蚀刻的硅底切而形成的所述多个区域形成了数个碗状区域；移除该硬掩模层；于该基板上施行源极掺质注入，以位于露出硅之上形成凸状形态的多个源极区，其中凸状形态的所述多个源极区具有接连于所述多个碗状区域的表面；于所述多个碗状区域内填满一介电层；施行一硅蚀刻，以形成多个 自对准源极接触物开口；以及于所述多个自对准源极接触物开口内填入接触金属以形成多个自对准接触物。 
本发明可免除对准容忍度并可降低间距尺寸。 
为让本发明的上述目的、特征及优点能更明显易懂，下文特举一优选实施例，并配合所附的附图，作详细说明如下： 
附图说明
图1显示了依据本发明的多个实施例的沟槽型金属氧化物半导体场效应晶体管的剖面情形； 
图2A-图2J显示了依据本发明的多个实施例的于制作具有自对准接触物的一沟槽型金属氧化物半导体场效应晶体管时的多个中间阶段与结构； 
图3显示了依据本发明的一实施例的采用沟槽型金属氧化物半导体场效应晶体管的一电源元件。 
其中，附图标记说明如下： 
100、100’～沟槽型金属氧化物半导体场效应晶体管； 
101、102、103～沟槽； 
104～栅极氧化物； 
105～栅极多晶硅； 
108～薄氧化物层； 
109～硅区域； 
110～介电硬掩模层； 
114～表面； 
115～源极区； 
117～侧壁； 
121～栅极金属； 
122～源极金属； 
123～粘着层/阻障层； 
124、125～接触物； 
126～牺牲氧化物层； 
127～源极区； 
130～P型掺杂区； 
131～介电层； 
132～硅表面； 
133、134～硅区域； 
135、136～接触开口； 
139～粘着层； 
140～接触金属层； 
141～介电蚀刻停止层； 
142～层间介电氧化物层； 
144～金属层； 
145～铜扩散阻障层； 
146～最终厚度； 
147～铜晶种层； 
150～漏极区/N+基板； 
101～末端沟槽； 
160～N型外延层； 
165～一P型掺杂区； 
300～电源元件； 
P、P*～胞距； 
D～距离； 
W～硅宽度； 
α～角度； 
m、n～沟槽。 
具体实施方式
图1显示了依据部分实施例的一沟槽型金属氧化物半导体场效应晶体管(trench MOSFET)100的剖面图。于部分实施例中，沟槽型金属氧化物半导体场效应晶体管100为电源元件(power device)的一部，而上述电源元件于介于1.8-600伏特的电压区间操作。沟槽型金属氧化物半导体场效应晶体管100具有沟槽101、102、103，上述沟槽具有栅极氧化物(gate oxide)104成长于沟 槽的侧壁上且上述沟槽为栅极多晶硅(gate polysilicon)105所填满。沟槽型金属氧化物半导体场效应晶体管可为N型沟槽型金属氧化物半导体场效应晶体管或P型沟槽型金属氧化物半导体场效应晶体管。基于简化的目的，下文中实施例中的沟槽型金属氧化物半导体场效应晶体管以N型沟槽型金属氧化物半导体场效应晶体管为例。然而，相似结构与其制法也适用于P型沟槽型金属氧化物半导体场效应晶体管。此外，用于设置沟槽型金属氧化物半导体场效应晶体管100的基板也可为其他的装置结构。 
沟槽型金属氧化物半导体场效应晶体管100形成于一基板区150之上，于该处掺杂有N型掺质(或为一N+基板)。此N+(或为经高度N型掺质掺杂)掺杂基板也作为沟槽型金属氧化物半导体场效应晶体管100的漏极。于基板区150之上则形成有一N型外延层160。沟槽101、102与103的部分则为一P型掺杂区165所环绕。位于沟槽101内的栅极多晶硅105通过接触物124(栅极接触物)而连接于一栅极金属(gate metal)121。源极区115则通过了接触物125(源极接触物)而连接于源极金属(source metal)122。接触物124、125、栅极金属121以及源极金属122衬覆有一粘着层/阻障层123。沟槽型金属氧化物半导体场效应晶体管100可包括为栅极多晶硅105所填满的更多沟槽，其可相似于沟槽102与103。于如图1所示的实施例中，仅显示了两个沟槽102与103。于部分实施例中，于源极金属122下方可形成有两个以上的沟槽。于其他实施例中，则仅于源极金属122下设置单一沟槽102(沟槽103不存在)。沟槽型金属氧化物半导体场效应晶体管110包括了位于沟槽101、102与103间的数个源极区115。当沟槽型金属氧化物半导体场效应晶体管100于开启状态下经偏压时，电流将垂直地流动于源极区115与漏极区150之间。 
如图1所示，沟槽型金属氧化物半导体场效应晶体管100的胞距(cellpitch)为“P”，其为介于两邻近沟槽102与103之间的一间距。为了降低胞距“P”以增加元件密度，需降低如沟槽102与103的沟槽的宽度、接触物125的宽度及沟槽102与103与接触物125的对准控制。当降低沟槽与接触物的宽度时，对于工艺与整合方面则形成问题。然而，当接触物125为自对准时，则可完全不考虑于接触物125与沟槽102与103之间的自对准控制容忍度。其结果为，自对准接触物的形成可更为降低沟槽型金属氧化物半导体场效应 晶体管110的胞距。 
图2A-图2J显示了依据本发明的多个实施例的用于制造具有自对准接触物的一沟槽型金属氧化物半导体场效应晶体管的结构以及位于工艺流程中的不同中间阶段。图2A显示了具有一N型外延层160(掺杂有N型掺质的外延层)以及一介电硬掩模层110的一N+基板150(掺杂有N型掺质的基板)。介电硬掩模层110经过形成与图案化后可用于沟槽101、102与103的制作。介电硬掩模层110可由氧化物、氮化物、氮氧化物或其结合情形所形成。于部分实施例中，介电硬掩模层110由等离子体加强型化学气相沉积氧化物(PECVD oxide)所形成，其具有介于约200-20000埃的厚度。于介电硬掩模层110的沉积后，于基板上施行深沟槽蚀刻(为一硅蚀刻)以形成沟槽101、102与103。于部分实施例中，用于沟槽101的沟槽开口较用于沟槽102与103的沟槽开口来的大，且沟槽101较沟槽102与103来的深。 
于部分实施例中，沟槽101、102与103的宽度约介于0.1-10微米。于部分实施例中，沟槽101、102与103的深度约介于0.2-40微米。沟槽的深宽比(aspect ratio，AR)定义为沟槽的深度比上沟槽的宽度。于部分实施例中，沟槽101、102与103的深宽比约介于1-30。于部分实施例中，沟槽101、102与103的深宽比约介于5-15。 
如图2B所示，于部分实施例中，于深沟槽蚀刻之后成长栅极氧化物104。于部分实施例中，栅极氧化物104的厚度约介于40-2000埃。于部分实施例中，栅极氧化物104的成长是于高于900℃的一温度下以及具有氧气、水蒸气或其组合的一环境施行。于部分实施例中，可先成长一牺牲氧化物层(未显示)以衬覆沟槽，并稍后于栅极氧化物104成长之前将其移除。上述牺牲氧化物层的成长与移除用于调整沟槽的硅表面。 
于成长栅极氧化物104后，沉积栅极多晶硅105以填满沟槽101、102与103。于部分实施例中，栅极多晶硅经过掺杂以增加其导电率。于部分实施例中，所使用的掺质例如为磷。也可使用其他类型的掺质。于部分实施例中，早于栅极多晶硅沉积之前，可沉积如介于数千埃至数微米的氧化物的一厚绝缘层于沟槽的底部之上。此厚绝缘层可降低栅极的电容量。 
于栅极多晶硅105沉积之后，位于沟槽外的过量多晶硅(包括沉积于介电层110上的多晶硅)可经过如蚀刻方式(即回蚀刻)的方法移除。于蚀刻过后， 位于沟槽内的栅极多晶硅105低于外延层160的表面一距离“D”。于部分实施例中，此距离“D”约介于0.1-2.0微米。于部分实施例中，早于降低栅极多晶硅105至低于介电层110的表面一深度“D”的蚀刻工艺(或回蚀刻)施行前，首先借由化学机械研磨方式移除高于介电硬掩模层110(于栅极多晶硅沉积之后)的栅极多晶硅105。如图2B所示，早于回蚀刻的此化学机械研磨工艺使得位于沟槽101、102与103内的栅极多晶硅105的表面114变的滑顺。 
图2C显示了于某些实施例中覆盖于栅极多晶硅105的表面114与介电层110的一薄氧化物层108，但其并不覆盖侧壁117。此薄氧化物层108可首先沉积一厚氧化物层(未显示)于如图2B所示的基板上以覆盖基板表面。此厚氧化物层的用途在于覆盖栅极多晶硅105的硅表面114并于沟槽的侧壁上形成最少沉积情形。于部分实施例中，此厚氧化物层的厚度约介于200-10000埃。于某些实施例中，可使用高密度等离子体化学气相沉积(HDP CVD)工艺以使得于侧壁之上形成最少的氧化物沉积。于厚氧化物层沉积之后，可施行如适用缓冲氧化物蚀刻剂(BOE)的湿氧化物将其蚀刻以移除位于沟槽101、102与103侧壁上的氧化物。于蚀刻工艺中，也可薄化(或蚀刻)高于栅极多晶硅105的氧化物层。于氧化物蚀刻后，露出了硅的侧壁117而一薄氧化物层108则覆盖了栅极多晶硅105。于部分实施例中，于蚀刻之后覆盖栅极多晶硅105的薄氧化物层108的厚度大于100埃以保护多晶硅栅极105免于后续基板工艺的毁损。 
如图2D所示，于部分实施例中，于前述的侧壁氧化物移除之后，施行一各向同性硅蚀刻以形成位于介电硬掩模层110下方的硅底切(siliconundercut)情形。此各向同性硅蚀刻经过时间控制以于沟槽101与102之间以及于沟槽102与103之间形成期望的硅宽度“W”。具有宽度“W”的硅区域109于后续操作中定义了用于形成自对准接触物的区域。 
接着，如图2E所示，于部分实施例中，移除了介电硬掩模层110与保护氧化物层108并沉积一牺牲氧化物层126。介电硬掩模层110与保护氧化物层108可借由不同工艺而移除，例如BOE湿蚀刻。于移除氧化物之后，可于具有硅或多晶硅的基板表面之上成长一牺牲氧化物层126。于部分实施例中，牺牲氧化物层126的厚度约介于100-1000埃。于部分实施例中，牺牲氧化物层126的成长是于高于900℃的温度下以及于具有氧气、水蒸气或其 结合情形的一环境下施行。于牺牲氧化物层126成长之后，利用P型掺质以施行一坦覆的基板注入。于部分实施例中，上述P型掺质为硼且使用的掺杂能量约介于5-2000KeV。于部分实施例中，上述掺杂剂量约介于1E11-5E14原子/每平方公分。经注入的掺质接着借由一热回火工艺(或一热驱入工艺)被驱入至基板内深处。于部分实施例中，上述热回火的温度约高于900℃。热回火可为一炉管回火或一快速热回火。图2E显示了于依据本发明的部分实施例中，经过施行注入与回火后的P型掺杂区130的轮廓。 
如图2F所示，于部分实施例中，于P型注入之后，接着针对基板施行一N+源极注入。于部分实施例中，注入掺质为砷或磷，而注入剂量约为5-200KeV。于部分实施例中，注入剂量约为5E14-1E17原子/每平方公分。N+掺质注入可于使得掺质主要地位于接近基板表面处的一角度下施行。于部分实施例中，上述注入可于约30°-60°的一角度下进行。于部分实施例中，上述注入可于介于约40°-50°的一角度“α”下施行。于布置时，基板经过旋转以确保掺质可均匀地分布于位于牺牲氧化物层126下方的顶面。图2F显示了经过注入而形成于区域127内N+源极掺质，其为凸出形状(具有面对基板表面的凸出表面)。于部分实施例中，源极区127高于栅极多晶硅105的表面之上。 
如图2G所示，于部分实施例中，于源极注入之后，沉积一介电层131并平坦化的至硅表面132。经平坦化的介电层131填满了位于沟槽101、102与103顶部的开口。如图2H所示，于部分实施例中，接着可施行坦覆的硅干蚀刻以形成自对准接触开口135与136。图2G内介于沟槽101与102间的硅区域133以及介于沟槽102与103间的硅区域134经过蚀刻而分别形成有接触开口135与136，如图2H所示。此些接触开口135与136是自我对准的。如图2H所示，接着施行一P+接触注入。注入P+掺质(或高浓度的P掺质)于露出的硅区域内。于部分实施例中，开口135与136的宽度约介于0.1-20微米。上述P+接触注入使得源极接触物成为欧姆接触物(ohmiccontacts)。 
依据某些实施例，于形成接触开口之后，形成于基板之上一光致抗蚀剂层(未显示)且将其图案化以形成一栅极接触开口(未显示)。可接着移除上述光致抗蚀剂层。于栅极接触开口形成之后，接触开口135与136以及栅极接触 开口可为一粘着层139与一接触金属140所填入。于部分实施例中，粘着层139为Ti/TiN(一双重膜层)所形成，而接触金属则由化学气相沉积的钨(CVDtungsten)所形成。如图2I所示，于部分实施例中，接着移除位于接触开口(或插拴)外的接触金属与粘着层。于部分实施例中，位于接触开口外的粘着层139与接触金属层140可经过一回蚀刻工艺或一化学机械研磨而移除。 
于部分实施例中，如图2J所示，于形成接触物124与125之后，可沉积介电蚀刻停止层141。于部分实施例中，介电蚀刻停止层141由氮化物所形成且具有介于约100-2000埃的厚度。接着，沉积一层间介电氧化物层142，并借由化学机械研磨而平坦化至高于接触物124与125的一最终厚度146，也如图2J所示。于部分实施例中，层间介电氧化物层142可借由一化学气相沉积工艺所形成，且具有约介于5000-25000埃的一化学机械研磨前厚度。于部分实施例中，高于接触物124与125的最终厚度146约介于2000-10000埃。于层间介电氧化物层142的平坦化之后，接着使用一光致抗蚀剂层(未显示)以图案化层间介电氧化物层142并形成了用于金属沉积的数个金属开口。于此些金属开口形成之后，沉积一金属层144并将其平坦化，借以留下位于开口内的金属层144。此金属层可借由具有低电阻率的导电金属所形成，例如铝、铜或一铜合金。金属层144可借由物理气相沉积、化学气相沉积、无电电镀或电化学电镀等方式沉积。位于沟槽101(栅极沟槽)上的金属层144也标示为栅极金属121，而位于沟槽102与103(胞沟槽)上的金属层144则标示为源极金属122。 
当使用铜或铜合金时，需使用一铜扩散阻障层145以阻挡铜扩散。适用于铜扩散阻障层145的材料包括了Ti、TiN、Ta、TaN或其组合，但并不以上述材料为限。当采用电化学电镀(ECP)沉积铜时，通常需要一铜晶种层147。于部分实施例中，铜晶种层146是由物理气相沉积而沉积形成。 
由于源极接触物125的形成无须光刻的图案化与对准，因而胞距“P*”可少于如图1所示的间距“P”。于部分实施例中，用于沟槽型金属氧化物半导体场效应晶体管100’的胞距约为0.4-5微米。 
图3显示了依据本发明的某些实施例的使用一沟槽型金属氧化物半导体场效应晶体管的电源元件300的俯视情形。前述的沟槽型金属氧化物半导体场效应晶体管100’也为电源元件300的一部。图3显示了栅极金属121与源 极金属122。图3也显示了胞沟槽102与103。相邻于沟槽102与103为数个胞沟槽，如沟槽“m”与“n”等。环绕栅极金属的是为用于隔离电源元件与周遭区域的一末端沟槽101。图3还显示了栅极沟槽101与栅极接触物124。源极接触物125隐藏于源极金属122下方而并未显示。图3中也显示了胞距“P*”。由于存在有数个胞沟槽，如沟槽102、103、m、n等，因此需维持胞距“P*”需为小。采用自对准接触物作为源极接触物可使得上述间距维持较小，因而可消除了对准裕度的需求。 
如前述的用于形成沟槽型金属氧化物半导体场效应晶体管的结构与制造方法采用了自对准接触物，因而可降低沟槽型金属氧化物半导体场效应晶体管的间距尺寸。上述自对准接触物是借由蚀刻露出的硅区域而形成，并无须使用光刻光掩模与对准情形。因而可免除了对准容忍度的需求且可降低间距尺寸。 
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。 

Claims (3)

1.一种位于基板上的沟槽型金属氧化物半导体场效应晶体管结构的形成方法，包括：
蚀刻该基板以形成具有一硬掩模层的多个沟槽；
于所述多个沟槽内衬覆一栅极氧化物层；
于所述多个沟槽内填满经掺杂多晶硅；
回蚀刻位于所述多个沟槽内的该经掺杂多晶硅至低于所述多个沟槽的顶面；
于经过回蚀刻该经掺杂多晶硅后，沉积一介电层于该基板之上，其中该介电层于所述多个沟槽内的多个侧壁上具有一最小沉积；
施行一湿氧化物蚀刻以移除位于所述多个沟槽的所述多个侧壁上的该介电层，以露出所述多个沟槽的所述多个侧壁上的硅；
施行一各向同性硅蚀刻，以底切位于该硬掩模层下方的硅，其中形成了高于所述多个沟槽的多个空间以及该硬掩模层下方借由该各向同性硅蚀刻的硅底切而形成的多个区域形成了多个碗状区域；
移除该硬掩模层；
于该基板上施行源极掺质注入，以位于露出硅之上形成具有面对该基板的表面的一凸出表面的多个源极区，其中具有面对该基板的表面的该凸出表面的所述多个源极区具有接连于所述多个碗状区域的表面；
于所述多个碗状区域内填满一介电层；
施行一硅蚀刻，以形成多个自对准源极接触物开口；以及
于所述多个自对准源极接触物开口内填入接触金属以形成多个自对准接触物。
2.如权利要求1所述的位于基板上的沟槽型金属氧化物半导体场效应晶体管结构的形成方法，其中该源极区是经过相对垂直于该基板的一表面的一轴的为非0度角的一注入。
3.如权利要求1所述的位于基板上的沟槽型金属氧化物半导体场效应晶体管结构的形成方法，其中该衬覆所述多个沟槽一栅极氧化物层的操作还包括：
于衬覆所述多个沟槽该栅极氧化物层之前沉积一牺牲氧化物层；以及于衬覆所述多个沟槽该栅极氧化物层之前移除该牺牲氧化物层。
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