CN102165570A - Method and device for manufacturing field-effect transistor - Google Patents
Method and device for manufacturing field-effect transistor Download PDFInfo
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- CN102165570A CN102165570A CN2009801379296A CN200980137929A CN102165570A CN 102165570 A CN102165570 A CN 102165570A CN 2009801379296 A CN2009801379296 A CN 2009801379296A CN 200980137929 A CN200980137929 A CN 200980137929A CN 102165570 A CN102165570 A CN 102165570A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
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Abstract
Provided are a method for manufacturing a field-effect transistor by which an active layer can be protected from an etchant without being exposed to an air atmosphere, and a device for manufacturing same. A method for manufacturing a field-effect transistor comprises a step of forming an active layer (15) (IGZO film (15F)) of In-Ga-Zn-O based composition on a base material (10) by a sputtering method, a step of forming, on the active layer, a stopper layer (16) (stopper layer forming film (16F)) for protecting the active layer from an etchant for the active layer by the sputtering method, and a step of etching the active layer with the stopper layer as a mask. By depositing the stopper layer by the sputtering method, the stopper layer can be formed without exposing the active layer to the air after the active layer is deposited. Consequently, film quality degradation caused by the adhesion of water and impurities in the air to the surface of the active layer can be prevented.
Description
Technical field
The present invention relates to a kind of manufacture method and manufacturing installation with field-effect transistor of active layer, this active layer is formed by InGaZnO based semiconductor oxide.
Background technology
In recent years, people are extensive use of active matrix liquid crystal display.Each pixel of this active matrix liquid LCD has the field effect thin-film transistor (TFT) as switch element.
The known thin-film transistor that following kind is arranged of people, that is, and the amorphous silicon film transistor that polycrystalline SiTFT that active layer is made of polysilicon and active layer are made of amorphous silicon.
Compare with polycrystalline SiTFT, amorphous silicon film transistor have that active layer is easy to make and can be on bigger substrate the even advantage of film forming.
Because transparent amorphous oxides film is compared with amorphous silicon, the mobile degree of its charge carrier (electronics, hole) is higher, and as active layer material, people develop it.For example, in patent documentation 1, record a kind of field-effect transistor, its active layer has used Compound I nMO of the same clan
3(ZnO)
m(M=In, Fe, Ga or Al, m are the integer of 1 above less than 50).In addition, in patent documentation 2, record the manufacture method that a kind of In-Ga-Zn-O of being formed with is the field-effect transistor of active layer, to by having InGaO
3(ZnO)
4The target that the polycrystalline sintered body of composition constitutes carries out sputter processing and forms this In-Ga-Zn-O is active layer.
Amorphous silicon film transistor adopts the CVD method to carry out film forming processing on the active layer that amorphous silicon constitutes and makes.Because being active layer, In-Ga-Zn-O can't adopt the CVD method to carry out film forming processing, so need to adopt sputtering method to carry out film forming processing.In addition, In-Ga-Zn-O is that film dissolves in bronsted lowry acids and bases bronsted lowry.Therefore, using etchant (etching solution) to carry out needing to form protective layer in the operation that pattern forms, with the not etched dose erosion of protection In-Ga-Zn-O film.In the prior art, people are extensive use of the mask against corrosion that is formed by photosensitive resin during etched pattern on film.
The open communique spy of [patent documentation 1] Japanese patent of invention opens ([0010] section) 2004-103957 number
The open communique spy of [patent documentation 2] Japanese patent of invention opens ([0103]～[0119] section) 2006-165527 number
But under normal conditions, mask against corrosion forms in atmospheric environment.Therefore, when constituting above-mentioned protective layer by mask against corrosion, this active layer is exposed in the atmospheric environment after forming active layer.Thereby following problem might appear, that is, moisture in the atmosphere or impurity impair the film quality of active layer attached to the surface of active layer.In addition, need for a long time when forming protective layer, these all can become the production efficiency main reasons for decrease.
Summary of the invention
In view of the foregoing, the object of the present invention is to provide a kind of manufacture method and manufacturing installation of field-effect transistor, it can not be exposed to the not etched dose erosion of this active layer of protection under the situation in the atmospheric environment at active layer.
For achieving the above object, the manufacture method of the described field-effect transistor of an embodiment of the invention comprises the operation that adopts sputtering method to form active layer on base material, and wherein, formed active layer has the In-Ga-Zn-O set member.Adopt sputtering method to form the barrier layer on above-mentioned active layer, this barrier layer is used for protecting the not etched dose erosion of above-mentioned active layer.As mask above-mentioned active layer is carried out etching and processing with this barrier layer.
For achieving the above object, the manufacturing installation of the described field-effect transistor of an embodiment of the invention is used for forming active layer on the base material and form the barrier layer on this active layer respectively, and described barrier layer is used for protecting the not etched dose erosion of above-mentioned active layer.Above-mentioned manufacturing installation has first film forming room and second film forming room.Described first film forming room comprises first sputter cathode that is used for forming above-mentioned active layer on above-mentioned base material, and this active layer has the In-Ga-Zn-O set member.Described second film forming room comprises second sputter cathode that is used for forming above-mentioned barrier layer on above-mentioned base material, and this barrier layer is formed by silicon oxide film or silicon nitride film.
Description of drawings
Fig. 1 is the profile at main position of each operation of the manufacture method of the described field-effect transistor of expression explanation first embodiment of the invention.
Fig. 2 is the profile at main position of each operation of the manufacture method of the described field-effect transistor of expression explanation first embodiment of the invention.
Fig. 3 is the profile at main position of each operation of the manufacture method of the described field-effect transistor of expression explanation first embodiment of the invention.
Fig. 4 is the profile at main position of each operation of the manufacture method of the described field-effect transistor of expression explanation first embodiment of the invention.
Fig. 5 is the profile at main position of each operation of the manufacture method of the described field-effect transistor of expression explanation first embodiment of the invention.
Fig. 6 is the general configuration figure of the manufacturing installation of the described field-effect transistor of expression first embodiment of the invention.
Fig. 7 is the roughly profile of the described field-effect transistor structure of expression second embodiment of the invention.
Fig. 8 is the general configuration figure of the manufacturing installation of the described field-effect transistor of expression second embodiment of the invention.
Fig. 9 is the roughly profile of the described field-effect transistor structure of expression third embodiment of the invention.
Figure 10 is the general configuration figure of the manufacturing installation of the described field-effect transistor of expression third embodiment of the invention.
Figure 11 is the general configuration figure of the manufacturing installation of the described field-effect transistor of expression four embodiment of the invention.
Embodiment
The manufacture method of the described field-effect transistor of one embodiment of the present invention comprises the operation that adopts sputtering method to form active layer on base material, and wherein, formed active layer has the In-Ga-Zn-O set member.Adopt sputtering method to form the barrier layer on above-mentioned active layer, this barrier layer is used for protecting the not etched dose erosion of above-mentioned active layer.As mask above-mentioned active layer is carried out etching and processing with this barrier layer.
In the manufacture method of above-mentioned field-effect transistor, adopt sputtering method to form the barrier layer.Therefore after forming active layer, can under this active layer is not exposed to situation in the atmosphere, not form the barrier layer, occur so can prevent moisture in the atmosphere or impurity cause the film quality variation attached to the surface of active layer situation.In addition, owing to after forming active layer, can form the barrier layer continuously, thus can shorten formation barrier layer required man-hour, so the present invention helps to enhance productivity.
Comparatively typical base material is a glass substrate.Size to this base material does not have particular determination.
Also can adopt can with oxidizing gas (O for example
2, O
3, H
2O etc.) sputtering method of generation chemical reaction forms above-mentioned active layer.For the sputtering target that forms the In-Ga-Zn-O film can use simple In-Ga-Zn-O target, also can use In
2O
3Target, Ga
2O
3A plurality of targets such as target, ZnO target.The processing of the spatter film forming that carries out in oxygen atmosphere when controlling, can easily be controlled the oxygen concentration in the film to the oxygen pneumatic (flow) that imports.
Form above-mentioned barrier layer more continuously after also can in active layer film forming cavity, forming above-mentioned active layer.
Therefore, owing to can under need not the situation that base material is taken out of in the film forming cavity of active layer, form the barrier layer, so the present invention more helps to enhance productivity.At this moment, different with the sputtering target that is used for forming active layer in above-mentioned film forming cavity, be provided with the sputtering target that is used for forming the barrier layer in addition.Therefore, can in different film formation process, separately use corresponding sputtering target.
The operation that forms above-mentioned barrier layer also can comprise following operation, that is, adopt sputtering method to form the operation of first dielectric film that is made of silicon oxide film or silicon nitride film on above-mentioned active layer; Adopt sputtering method on this first dielectric film, to form the operation of second dielectric film that constitutes by metal oxide film.
In addition, the operation that forms above-mentioned barrier layer also can comprise following operation, that is, adopt sputtering method to form the operation of first dielectric film that is made of metal oxide film on above-mentioned active layer; Adopt sputtering method on this first dielectric film, to form the operation of second dielectric film that constitutes by silicon oxide film or silicon nitride film.
When constituting the barrier layer by plural layers like this, can guarantee that this barrier layer has the various functions that itself should have.In last example, first dielectric film has the function that can guarantee the electrical insulating property stipulated, and second dielectric film has the function that can guarantee the block of stipulating.
Above-mentioned first dielectric film and above-mentioned second dielectric film also can form in same cavity continuously.
By continuous formation first and second dielectric films, can in a cavity, concentrate to form the barrier layer, so can enhance productivity.At this moment, in above-mentioned cavity, be provided with the sputtering target that is used for forming the sputtering target of first dielectric film and is used for forming second dielectric film.Therefore, can in different film formation process, separately use corresponding sputtering target.
Form above-mentioned barrier layer more continuously after also can in active layer film forming cavity, forming above-mentioned active layer.
Therefore, owing to can under need not the situation that base material is taken out of in the film forming cavity of active layer, form the barrier layer, so the present invention more helps to enhance productivity.
Above-mentioned base material comprises gate electrode, also can form the gate insulating film that is used for covering described gate electrode before forming above-mentioned active layer.
Can be made into the bottom gate type field-effect transistor thus.Gate electrode also can be formed in the electrode film on the base material, also can adopt the structure of base material as gate electrode itself.
Also can adopt sputtering method to form described gate insulating film.
Therefore, can in vacuum environment, form gate insulating film, active layer and barrier layer continuously.
The operation that forms above-mentioned gate insulating film also can comprise following operation, that is, adopt sputtering method to form the operation of the first grid dielectric film that is made of metal oxide film on above-mentioned gate electrode; Adopt sputtering method on this first grid dielectric film, to form the operation of the second grid dielectric film that constitutes by silicon oxide film or silicon nitride film.
In addition, the operation that forms above-mentioned gate insulating film also can comprise following operation,, forms the operation of the first grid dielectric film that is made of silicon oxide film or silicon nitride film on above-mentioned gate electrode that is; On this first grid dielectric film, form the operation of the second grid dielectric film that constitutes by metal oxide film.
When constituting gate insulating film by plural layers like this, can guarantee that this gate insulating film has the various functions that itself should have.In last example, the first grid dielectric film has the function that can guarantee the block of stipulating, and second dielectric film has the function that can guarantee the electrical insulating property stipulated.
The diaphragm that covers above-mentioned active layer be can form, and the source electrode and the drain electrode of this active layer of contact formed.Can adopt sputtering method to form diaphragm.
The manufacturing installation of the described field-effect transistor of an embodiment of the invention is used for forming active layer on the base material respectively and form the barrier layer on this active layer, and described barrier layer is used for protecting the not etched dose erosion of above-mentioned active layer.Above-mentioned manufacturing installation has first film forming room and second film forming room.Described first film forming room comprises first sputter cathode that is used for forming above-mentioned active layer on above-mentioned base material, and this active layer has the In-Ga-Zn-O set member.Described second film forming room comprises second sputter cathode that is used for forming above-mentioned barrier layer on above-mentioned base material, and this barrier layer is formed by silicon oxide film or silicon nitride film.
In the manufacturing installation of above-mentioned field-effect transistor, adopt sputtering method in first film forming room, to form active layer with In-Ga-Zn-O set member, adopt sputtering method in second film forming room, to form the barrier layer that constitutes by silicon oxide film or silicon nitride film.Therefore after forming active layer, can under this active layer is not exposed to situation in the atmosphere, not form the barrier layer, occur so can prevent moisture in the atmosphere or impurity cause the film quality variation attached to the surface of active layer situation.In addition, owing to after forming active layer, can form the barrier layer continuously, thus can shorten formation barrier layer required man-hour, so the present invention helps to enhance productivity.
Above-mentioned first film forming room and second film forming room also can be shared film forming room.
Therefore, can in same cavity, form active layer and barrier layer continuously.
Above-mentioned second sputter cathode also can comprise first target that is made of silica or silicon nitride and second target that is made of metal oxide.
Therefore, can form the barrier layer of the sandwich construction of second dielectric film that has first dielectric film that constitutes by silicon oxide film or silicon nitride film and constitute by metal oxide film continuously, thereby can obtain to have the insulating properties of regulation and the barrier layer of block.
The manufacturing installation of above-mentioned field-effect transistor also can have the 3rd film forming room that is used for forming gate insulating film on above-mentioned base material.
Therefore, can in same device, form gate insulating film, active layer and barrier layer.
Perhaps the manufacturing installation of above-mentioned field-effect transistor can also have the 3rd film forming room that comprises the 3rd sputter cathode that is used on above-mentioned base material forming gate insulating film.
Therefore, can in same device, form gate insulating film, active layer and barrier layer.
Above-mentioned the 3rd sputter cathode also can comprise the 3rd target that is made of metal oxide and the 4th target that is made of silica or silicon nitride.
Therefore, the barrier layer of the sandwich construction of the second grid dielectric film that for example has the first grid dielectric film that constitutes by silicon oxide film or silicon nitride film and constitute by metal oxide film can be formed continuously, thereby the insulating properties of regulation and the gate insulating film of block can be obtained to have.
Above-mentioned manufacturing installation also can have the carrying room that can exhaust becomes vacuum state, and this carrying room has the conveying robot of picking above-mentioned base material to above-mentioned first film forming room and above-mentioned second film forming room.Above-mentioned first film forming room and above-mentioned second film forming room be arranged on above-mentioned carrying room around.That is, this manufacturing installation can adopt aggregation type film formation device structure.
Above-mentioned manufacturing installation can also have carrying mechanism from above-mentioned first film forming room to above-mentioned second film forming room that carry above-mentioned base material from.The adjacent setting of above-mentioned first film forming room and above-mentioned second film forming room.That is, this manufacturing installation can adopt intraconnected film formation device structure.
Embodiments of the present invention are described below with reference to the accompanying drawings.
[first execution mode]
Fig. 1～Fig. 5 is the profile at main position of each operation of the manufacture method of the described field-effect transistor of expression explanation first embodiment of the invention.The manufacture method of the field-effect transistor with so-called bottom gate type transistor arrangement is described in the present embodiment.
Shown in (A) among Fig. 1, at first form gate electrode film 11F on a surface of base material 10.
Comparatively typical base material 10 is a glass substrate.Comparatively typical gate electrode film 11F is made of the metal single layer film or the metallized multilayer film of molybdenum, chromium, aluminium etc., and it for example adopts sputtering method to form.Thickness to gate electrode film 11F does not have particular determination, and for example it is 300nm.
Next shown in (D) among (B)～Fig. 1 among Fig. 1, gate electrode film 11F is processed into the pattern with regulation shape forms with mask 12 against corrosion.This operation has photoresist film 12F and forms operation (among Fig. 1 (B)), exposure process (among Fig. 1 (C)), developing procedure (among Fig. 1 (D)).
Make it dry after being coated in the liquid photosensitive material on the gate electrode film 11F and form photoresist film 12F.Also can use dry type film resist as photoresist film 12F.After exposing, 13 couples of formed photoresist film 12F of mask can develop.Therefore, can on gate electrode film 11F, form mask 12 against corrosion.
Then shown in (E) among Fig. 1, as mask gate electrode film 11F is carried out etching and processing with mask 12 against corrosion.Therefore, can form gate electrode 11 on the surface of base material 10.
Engraving method to gate electrode film 11F does not have particular determination, can adopt wet etching, can adopt the dry-etching method yet.Remove mask 12 against corrosion after the etching and processing.The method of removing mask 12 against corrosion is suitable for the ashing treatment of oxygen plasma, but present embodiment is not limited thereto, and also can adopt the method for removing with soup.
Next, shown in (A) among Fig. 2, but form the gate insulating film 14 of covering grid electrode 11 on one of base material 10 surface.
Comparatively typical gate insulating film 14 is by silicon oxide film (SiO
2), silicon nitride film (SiN
x) wait oxide-film or nitride film to constitute, it is CVD method or the formation of employing sputtering method for example.Thickness to gate electrode film 11F does not have particular determination, and for example it is 200～500nm.
Next shown in (B) among Fig. 2, on gate insulating film 14, form film (being designated hereinafter simply as " IGZO film ") 15F and barrier layer successively and form film 16F with In-Ga-Zn-O set member.Adopt sputtering method to form IGZO film 15F and barrier layer formation film 16F.Can form IGZO film 15F and barrier layer continuously and form film 16F.At this moment, the sputtering target that is used for forming the sputtering target of IGZO film 15F and is used for forming barrier layer formation film 16F also can be set in same sputter cavity.By switching employed target, can independently form IGZO film 15F or barrier layer and form film 16F.
Under the state that base material 10 is heated to set point of temperature, form IGZO film 15F.In the present embodiment, the sputtering method that employing can produce chemical reaction forms active layer 15 (IGZO film 15F), wherein, and by in oxygen atmosphere, target being carried out sputter and will being deposited on the base material 10 with the reactant that oxygen reacts.Discharge type can be any in DC discharge, AC discharge, the RF discharge.In addition, also can adopt the magnetron discharge method that permanent magnet is set in the rear side of target.
Active layer (current-carrying layer) 15 by IGZO film 15F transistor formed.The metal film pattern that constitutes source electrode and drain electrode in aftermentioned forms operation; with adopt processing method to remove in the operation of unwanted part of IGZO film 15F, the barrier layer forms film 16F and plays the etch protection layer effect of trench region of protection IGZO film to prevent etched dose of erosion.The barrier layer forms film 16F for example by SiO
2Constitute.
Next, shown in (D) among (C) and Fig. 2 among Fig. 2, the barrier layer is formed film 16F be processed into the pattern with regulation shape and form with behind the mask 27 against corrosion, 16F carries out etching and processing through 27 pairs of barrier layers formation of this mask against corrosion film.Therefore, can form the barrier layer 16 that clips gate insulating film 14 and IGZO film 15F and face with gate electrode 14.
Shown in (E) among Fig. 2, remove the metal film 17F that mask 27 back formation against corrosion can cover IGZO film 15F and barrier layer 16.
Comparatively typical metal film 17F is made of the metal single layer film or the metallized multilayer film of molybdenum, chromium, aluminium etc., and it for example adopts sputtering method to form.Thickness to metal film 17F does not have particular determination, and for example it is 100～500nm.
Then shown in (B) among (A) and Fig. 3 among Fig. 3, metal film 17F is carried out pattern form processing.
The pattern of metal film 17F forms operation and has the formation operation (among Fig. 3 (A)) of mask 18 against corrosion and the etching work procedure (among Fig. 3 (B)) of metal film 17F.Mask 18 against corrosion has area just above and the uncovered mask pattern in each transistorized peripheral region that makes barrier layer 16.Forming mask against corrosion 18 backs adopts wet etching that metal film 17F is carried out etching and processing.Therefore, metal film 17F is separated into source electrode 17S and drain electrode 17D.In addition, in explanation after this, also source electrode 17S and drain electrode 17D are generically and collectively referred to as source/drain electrode 17 sometimes.
In source/drain electrode 17 formation operations, the effect of the etch stop layer of metal film 17F is played on barrier layer 16.That is, barrier layer 16 has the function of protection IGZO film 15F to prevent etched dose (for example phosphorus nitre acetate) erosion.This etchant is at metal film 17F.Barrier layer 16 forms in the mode that covers the zone (hereinafter referred to as " trench region ") between source electrode 17S on the IGZO film 15F and drain electrode 17D.Therefore, the trench region of IGZO film 15F is unaffected in the etching work procedure of metal film 17F.
Next, shown in (D) among (C) and Fig. 3 among Fig. 3, be that mask carries out etching and processing to IGZO film 15F with mask 18 against corrosion.
Engraving method is not had particular determination, can adopt wet etching, can adopt the dry-etching method yet.Through the etching work procedure of this IGZO film 15F, IGZO film 15F promptly can be that unit is isolated with the element, can form the active layer 15 that is made of IGZO film 15F again.
At this moment, the effect of the etching protective film of the IGZO film 15F that is positioned at trench region is played on barrier layer 16.That is, the effect of barrier layer 16 with protection trench region under the barrier layer 16 corroded to prevent etched dose (for example oxalic acid system).This etchant is aimed at IGZO film 15F's.Therefore, the trench region of active layer 15 is unaffected in the etching work procedure of IGZO film 15F.
After the pattern of IGZO film 15F forms processing, adopt method such as ashing treatment from the source/drain electrode 17 removal masks 18 against corrosion (Fig. 3 (D)).
Next shown in (A) among Fig. 4, form the diaphragm (passivating film) 19 that can cover source/drain electrode 17, barrier layer 16, active layer 15, gate insulating film 14 on the surface of base material 10.
Then shown in (D) among (B)～Fig. 4 among Fig. 4, on diaphragm 19, form the intercommunicating pore 19a that is communicated with source/drain electrode 17.This operation has the operation (among Fig. 4 (B)) that forms mask 20 against corrosion on diaphragm 19, the diaphragm 19 that the peristome 20a from mask 20 against corrosion is exposed carries out the operation (Fig. 4 (C)) of etching and processing, the operation (among Fig. 4 (D)) of removal mask 20 against corrosion.
Adopt the dry-etching method when forming intercommunicating pore 19a, but also can adopt wet etching.In addition, though omitted its diagram, be formed with the contact hole that is connected with source electrode 17S equally on the desired position arbitrarily.
Next, shown in (D) among (A)～Fig. 5 among Fig. 5, through the nesa coating 21 that intercommunicating pore 19a forms with the source/drain electrode 17 contacts.This operation has the operation (among Fig. 5 (A)) that forms transparent conductive film 21F, the operation (among Fig. 5 (B)) that forms mask 22 against corrosion on transparent conductive film 21F, the transparent conductive film 21F that is not covered by mask 22 against corrosion is carried out the operation (among Fig. 5 (C)) of etching and processing, the operation (among Fig. 5 (D)) of removal mask 20 against corrosion.
Comparatively typical transparent conductive film 21F is made of ITO film or IZO film, and it for example adopts sputtering method, CVD method to form.Adopted wet etching when transparent conductive film 21F is carried out etching and processing, but present embodiment is not limited thereto, also can adopts the dry-etching method.
Afterwards the transistor unit that is formed with nesa coating 21 shown in (D) among Fig. 5 100 is carried out annealing in process, its purpose is to relax the stress of active layer 15.Therefore, do like this and can give active layer 15 needed transistor characteristics.
By above each step, promptly can be made into field-effect transistor (transistor unit 100).
In the present embodiment, IGZO film 15F that constitutes active layer 15 and the barrier layer that constitutes barrier layer 16 form film 16F to adopt sputtering method to form respectively.Therefore after forming IGZO film 15F (active layer 15), can under this IGZO film 15F is not exposed to situation in the atmosphere, not form barrier layer 16, occur so can prevent moisture in the atmosphere or impurity cause the film quality variation attached to the surface of active layer 15 situation.
In addition, owing to after forming active layer 15, can form barrier layer 16 continuously, thus can shorten formation barrier layer 16 required man-hour, so the present invention helps to enhance productivity.
Among Fig. 6 among (A), Fig. 6 (B) be the general configuration figure of vacuum treatment installation of the part of the expression manufacturing process that is used for carrying out above-mentioned transistor unit 100 (field-effect transistor).
Comparatively typical situation is that the base material 10 (with reference to (F) among Fig. 1) that is formed with gate electrode 11 is moved in the compression chamber 211.By above-mentioned conveying robot base material 10 is transported to the heating chamber 212 from compression chamber 211.Base material 10 is heated processing in heating chamber 212, adheres to or is adsorbed on its lip-deep moisture etc. with removal.Be moved to again after base material 10 is heated in the CVD chamber 213, in CVD chamber 213, form gate insulating film 14 (in reference to Fig. 2 (A)).Form gate insulating film 14 back base materials 10 and be moved to again in the sputtering chamber 214, in sputtering chamber 214, form IGZO film 15F and barrier layer formation film 16F (in reference to Fig. 2 (B)).Form the barrier layer and form the outside that base material 10 behind the film 16F is moved in the pressure-reducing chamber 215 again and finally is moved to vacuum treatment installation 201.
Sputtering chamber 214 has the sputter cathode Tc that comprises the target that is used for forming IGZO film 15F and comprises and is used for forming the sputter cathode Ts that the barrier layer forms the target of film 16F.The sputtering target that is used for forming IGZO film 15F can use simple In-Ga-Zn-O target, also can use In
2O
3Target, Ga
2O
3A plurality of targets such as target, ZnO target.Be used for forming the sputtering target that the barrier layer forms film 16F and can use silicon oxide target or silicon nitride target, but present embodiment is not limited thereto.
Sputtering chamber 214 has the gas delivery system that is used for to indoor importing oxidizing gas, can adopt to form IGZO film 15F and barrier layer formation film 16F with the sputtering method of oxidizing gas generation chemical reaction.When the gas atmosphere that imports is controlled, can easily control the oxygen concentration in the film.As the gas that is imported in the sputtering chamber 214, though exemplified O
2, O
3, H
2O etc., but present embodiment is not limited thereto.
Employing has the vacuum treatment installation 201,202 o'clock of said structure, form film 16F owing to after forming IGZO film 15F, can under this IGZO film 15F is not exposed to situation in the atmosphere, form the barrier layer, occur so can prevent moisture in the atmosphere or impurity cause the film quality variation attached to the surface of IGZO film 15F situation.In addition, form film 16F, form required man-hour of barrier layer formation film 16F so can shorten, so the present invention helps to enhance productivity owing to after forming IGZO film 15F, can form the barrier layer continuously.
In addition, when adopting vacuum treatment installation 201, also can in IGZO film 15F film forming cavity, form the barrier layer continuously and form film 16F.Therefore, form film 16F because the barrier layer can be formed under need not the situation that base material 10 is taken out of in the IGZO film 15F film forming cavity, so the present invention more helps to enhance productivity.
[second execution mode]
Fig. 7 represents second execution mode of the present invention.In addition, among the figure corresponding to the part of above-mentioned first execution mode, mark identical Reference numeral and omit its detailed description.
Contain a little less than zinc (Zn) the semiconductor layer acid and alkali-resistance ability, thereby be easy to it is carried out etching and processing.Therefore when forming active layer 15, in the trench region of IGZO film 15F, be formed with barrier layer 16 to prevent etched dose of erosion.The effect of dielectric film is also played in the effect that the etching mask of IGZO film 15F had both been played on barrier layer 16, keeps electric insulating state in order to make in active layer 15 upper stratas one side between source electrode 17S and the drain electrode 17D.
But the silicon oxide film that constitutes barrier layer 16 also has can not fully prevent the situation that impurity is sneaked in the atmosphere.When sneaking in the active layer 15, can make transistor characteristic produce deviation from the impurity in the atmosphere.
To this, the double-decker that adopts barrier layer 16 to constitute in the present embodiment by the first dielectric film 16A and the second dielectric film 16B.Wherein, the first dielectric film 16A is made of silicon oxide film or silicon nitride film, and the second dielectric film 16B is formed on the first dielectric film 16A and upward and by metal oxide film constitutes.Guarantee required electrical insulating property by the first dielectric film 16A, guarantee the block that prevents that impurity is sneaked in the atmosphere by the second dielectric film 16B.
The second dielectric film 16B adopts has the higher insulating metal oxide of block that can prevent that impurity is sneaked in the atmosphere.As the second dielectric film 16B, can be by tantalum oxide (TaO
x), aluminium oxide (Al
2O
3), yittrium oxide (Y
2O
3) wait formation.When the upper strata of the first dielectric film 16A, one side forms this second dielectric film 16B, can form barrier layer with the block excellence that can prevent that impurity is sneaked in the atmosphere.Therefore, the present invention helps to make transistor characteristic to become steady.
In addition, also can constitute the first dielectric film 16A, constitute the second dielectric film 16B by silicon oxide film or silicon nitride film by metal oxide film.Even adopt this structure, also can obtain the effect the same with above-mentioned situation.
Among Fig. 8 among (A), Fig. 8 among (B), Fig. 8 (C) be the general configuration figure of vacuum treatment installation of the part of the expression manufacturing process that is used for carrying out above-mentioned transistor unit 101 (field-effect transistor).In addition, among the figure with the corresponding part of Fig. 6, mark identical Reference numeral and omit its detailed description.
Among Fig. 8 among (B) and Fig. 8 the vacuum treatment installation shown in (C) 204,205 also be fork formula (aggregation type) vacuum treatment installation.Vacuum treatment installation 204 has the second sputtering chamber 214B that is used for forming the first sputtering chamber 214A of IGZO film 15F and is used for forming barrier layer formation film 16F (the first dielectric film 16A and the second dielectric film 16B).Vacuum treatment installation 205 has the first sputtering chamber 214A, the second sputtering chamber 214B that is used for forming the first dielectric film 16A that constitutes barrier layer 16 that is used for forming IGZO film 15F, the 3rd sputtering chamber 214C that is used for forming the second dielectric film 16B that constitutes barrier layer 16.
The same with above-mentioned first execution mode, when adopting present embodiment, form film 16F owing to after forming IGZO film 15F, also can under this IGZO film 15F is not exposed to situation in the atmosphere, form the barrier layer, occur so also can prevent moisture in the atmosphere or impurity cause the film quality variation attached to the surface of IGZO film 15F situation.In addition, form film 16F, form required man-hour of barrier layer formation film 16F so also can shorten, so the present invention helps to enhance productivity owing to after forming IGZO film 15F, also can form the barrier layer continuously.
In addition, when adopting vacuum treatment installation 203, also can in IGZO film 15F film forming cavity, form the barrier layer continuously and form film 16F.Therefore, form film 16F because the barrier layer can be formed under need not the situation that base material 10 is taken out of in the IGZO film 15F film forming cavity, so the present invention more helps to enhance productivity.
[the 3rd execution mode]
Fig. 9 represents the 3rd execution mode of the present invention.In addition, among the figure corresponding to the part of above-mentioned first and second execution modes, mark identical Reference numeral and omit its detailed description.
The purpose that forms gate insulating film is the electric insulating state that is used for guaranteeing between gate electrode and the active layer.But because the gate insulating film that is made of silicon oxide film is lower to the block from the diffusion of the impurity of substrate (base material), so, can't guarantee the insulation property of stipulating sometimes when the diffusion of impurities of substrate is in gate insulating film.At this moment, because of obtaining required insulation property by gate insulating film, so following problem might occur, that is, or gate threshold produces deviation, or produces leaky between active layer.
To this, the double-decker that adopts gate insulating film 14 to constitute in the present embodiment by first grid dielectric film 14A and second grid dielectric film 14B.Wherein, first grid dielectric film 14A is made of metal oxide film, and second grid dielectric film 14B is formed on first grid dielectric film 16A and upward and by silicon oxide film or silicon nitride film constitutes.14A guarantees required block by the first grid dielectric film, and 16B guarantees required electrical insulating property by the second grid dielectric film.
First grid dielectric film 14A adopts the insulating metal oxide that the diffusion from the impurity of substrate is had higher block.As first grid dielectric film 14A, can be by tantalum oxide (TaO
x), aluminium oxide (Al
2O
3), yittrium oxide (Y
2O
3) wait formation.When lower floor's one side at second grid dielectric film 14B forms this first grid dielectric film 14A, can form the gate insulating film that the diffusion from the impurity of substrate is had higher block.Therefore, the present invention can make the transistor unit with required transistor characteristic reposefully.
In addition, also can constitute first grid dielectric film 14A, constitute second grid dielectric film 14B by metal oxide film by silicon oxide film or silicon nitride film.Even adopt this structure, also can obtain the effect the same with above-mentioned situation.
Among Figure 10 among (A), Figure 10 among (B), Figure 10 (C) be the general configuration figure of vacuum treatment installation of the part of the expression manufacturing process that is used for carrying out above-mentioned transistor unit 102 (field-effect transistor).In addition, among the figure with Fig. 6 and the corresponding part of Fig. 8, mark identical Reference numeral and omit its detailed description.
Among Figure 10 among (B) and Figure 10 the vacuum treatment installation shown in (C) 207,208 also be fork formula (aggregation type) vacuum treatment installation.Vacuum treatment installation 207 has first sputtering chamber 213, the second sputtering chamber 214A that is used for forming the IGZO film 15F that constitutes active layer 15 that is used for forming first, second gate insulating film 14A, the 14B that constitute gate insulating film 14, the 3rd sputtering chamber 214B that is used for forming first, second dielectric film 16A, the 16B that constitute barrier layer 16.Vacuum treatment installation 208 has the first sputtering chamber 213A, the second sputtering chamber 213B that is used for forming second grid dielectric film 14B, the 3rd sputtering chamber 214A that is used for forming IGZO film 15F, the 4th sputtering chamber 214B that is used for forming the first dielectric film 16A that is used for forming first grid dielectric film 14A, the 5th sputtering chamber 214C that is used for forming the second dielectric film 16B.
The same with above-mentioned first, second execution mode, when adopting present embodiment, form film 16F owing to after forming IGZO film 15F, also can under this IGZO film 15F is not exposed to situation in the atmosphere, form the barrier layer, occur so also can prevent moisture in the atmosphere or impurity cause the film quality variation attached to the surface of IGZO film 15F situation.In addition, form film 16F, form required man-hour of barrier layer formation film 16F, therefore help to enhance productivity so also can shorten owing to after forming IGZO film 15F, also can form the barrier layer continuously.
In addition, when adopting vacuum treatment installation 208, form gate insulating film 14, so need not unstrpped gas import system required in the CVD operation or to the treatment facility of institute's emission gases because of adopting sputtering method.Therefore, the present invention can help to reduce equipment cost and make operation more succinct.
[the 4th execution mode]
Among Figure 11 among (A), Figure 11 among (B) and Figure 11 (C) be the general configuration figure of the manufacturing installation of the described field-effect transistor of expression four embodiment of the invention.In the present embodiment, adopting intraconnected vacuum treatment installation apparatus structure with described manufacturing installation is that example describes.
In addition, vacuum treatment installation can adopt horizontal or vertical structure, wherein, in the horizontal vacuum processing unit with the flat mode carrying substrate that crouches of along continuous straight runs, mode carrying substrate then in the vertical vacuum processing unit roughly to erect.When the size of substrate (base material) is big, help reducing to be provided with area when adopting vertical structure.In addition, carrying out film forming on base material 10 adds and can adopt following any method man-hour, promptly, a kind of is to carry out film forming processing method in the advancing of film forming processing in the process of carrying base material in process chamber, and a kind of is static film forming (film forming under the halted state) processing method that base material is still in carry out film forming processing in the process chamber again.
Vacuum treatment installation 301 shown in (A) among Figure 11 has compression chamber 311, first heating chamber 312, CVD chamber 312, isolation ward 314, first sputtering chamber 315, second heating chamber 316, second sputtering chamber 317 and pressure-reducing chamber 318.Though in vacuum treatment installation 301, illustrate, wherein be provided with and be used for base material 10 is transported to carrying mechanism in the chambers, this carrying mechanism 311 318 is transported to base material 10 chambers towards the pressure-reducing chamber from the compression chamber.Though it is not illustrated, between adjacent process chamber, be fitted with valve members such as gate valve, required valve can be opened when the carrying base material.Chambers all keeps the specified vacuum degree, and the handling process that base material 10 is managed between the chamber 311～218 is throughout all carried out in vacuum environment.
Comparatively typical situation is that the base material 10 (with reference to (F) among Fig. 1) that is formed with gate electrode 11 is moved in the compression chamber 311.The base material 10 that is moved in the compression chamber 311 is moved in first heating chamber 312 again.Base material 10 is heated processing in first heating chamber 312, adheres to or is adsorbed on its lip-deep moisture etc. with removal.Be moved to again after base material 10 is heated in the CVD chamber 313, in CVD chamber 313, form gate insulating film 14 (in reference to Fig. 2 (A)).Form gate insulating film 14 back base materials 10 and be moved to again in first sputtering chamber 314, in first sputtering chamber 314, form IGZO film 15F through isolation ward 314.Base material 10 is moved in second heating chamber 316 again after forming IGZO film 15F, heat-treats in second heating chamber 316, IGZO film 15F is given the transistor characteristic of regulation.Be moved to again after base material 10 is heated in second sputtering chamber 317, in second sputtering chamber 317, form the barrier layer and form film 16F (in reference to Fig. 2 (B)).Form the barrier layer and form the outside that base material 10 behind the film 16F is moved in the pressure-reducing chamber 215 again and finally is moved to vacuum treatment installation 201.
The purpose that isolation ward 314 is set is to isolate the processing environment between the CVD chamber 313 and first sputtering chamber 315.That is, generally speaking, compare, in the CVD chamber, not only under the environment of rough vacuum more, handle, and their processing gas is also inequality with the situation in the sputtering chamber.Therefore, the CVD chamber in the intraconnected vacuum treatment installation is adjacent with sputtering chamber when being provided with, and in the indoor processing gas flow sputtering chamber of CVD, can pollute the environment in the sputtering chamber thus.For preventing this from occurring, when being inserted into the isolation ward that maintains the vacuum degree also higher between CVD chamber and the sputtering chamber, do the processing gas polyphone that can prevent between CVD chamber and the sputtering chamber like this than the vacuum degree of these process chambers.
Use the vacuum treatment installation 302 shown in (B) among Figure 11 when making the transistor unit 101 (with reference to Fig. 7) in above-mentioned second execution mode, wherein, the double-decker that is made of the first dielectric film 16A and the second dielectric film 16B is adopted on the barrier layer 16 of this transistor unit 101.That is, vacuum treatment installation 302 has the sputtering chamber 317B that is used for forming the sputtering chamber 317A of the first dielectric film 16A and is used for forming the second dielectric film 16B.
Use the vacuum treatment installation 303 shown in (C) among Figure 11 when making the transistor unit 102 (with reference to Fig. 9) in above-mentioned the 3rd execution mode, wherein, the gate insulating film 14 of this transistor unit 102 adopts the double-decker that is made of first grid dielectric film 14A and second grid dielectric film 14B, and the double-decker that is made of the first dielectric film 16A and the second dielectric film 16B is adopted on barrier layer 16.That is, vacuum treatment installation 303 has sputtering chamber 313A, the sputtering chamber 313B that is used for forming second grid dielectric film 14A, the sputtering chamber 317A that is used for forming the first dielectric film 16A that is used for forming first grid dielectric film 14A, the sputtering chamber 317B that is used for forming the second dielectric film 16B.
The same with above-mentioned first, second execution mode, when adopting present embodiment, form film 16F owing to after forming IGZO film 15F, also can under this IGZO film 15F is not exposed to situation in the atmosphere, form the barrier layer, occur so also can prevent moisture in the atmosphere or impurity cause the film quality variation attached to the surface of IGZO film 15F situation.In addition, form film 16F, form required man-hour of barrier layer formation film 16F so also can shorten, so the present invention helps to enhance productivity owing to after forming IGZO film 15F, also can form the barrier layer continuously.
In addition, when adopting vacuum treatment installation 303, owing to adopt sputtering method to form gate insulating film 14, so need not unstrpped gas import system required in the CVD operation or to the treatment facility of institute's emission gases.Therefore, the present invention can help to reduce equipment cost and make operation more succinct.Also have, owing to adopt sputtering method to form gate insulating film 14, so need not isolation ward to be set being used for forming between the sputtering chamber of active layer.
Embodiments of the present invention more than have been described, the present invention is not limited to above-mentioned execution mode certainly, in the scope that does not break away from purport of the present invention, can carry out various modification to it.
For example, the manufacture method with the bottom gate type field-effect transistor is that example is illustrated in the above-described embodiment, but the present invention is not limited thereto, in the manufacture method of the present invention applicable to the top gate type field-effect transistor.
In addition, in above-mentioned the 3rd, the 4th execution mode, illustrated that the employing sputtering method forms the first grid dielectric film 14A of formation gate insulating film 14 and the example of second grid dielectric film 14B respectively.But the present invention is not limited thereto, also can adopt the CVD method to form one deck at least among first, second gate insulating film 14A, the 14B.
Also have, the present invention is not limited to be made of the monofilm of silicon oxide film or silicon nitride film the example of gate insulating film 14, for example can constitute gate insulating film by the laminated film of silicon oxide film and silicon nitride film.
[description of reference numerals]
10, base material; 11, gate electrode; 14, gate insulating film; 14A, the first grid dielectric film; 14B, the second grid dielectric film; 15, active layer; 15F, the IGZO film; 16, the barrier layer; 16A, first dielectric film; 16B, second dielectric film; 16F, the barrier layer forms film; 17 (17S, 17D), source/drain electrode; 100,101,102, transistor unit (field-effect transistor); 201～208,301～303, vacuum treatment installation
Claims (19)
1. the manufacture method of a field-effect transistor is characterized in that,
Adopt sputtering method to form active layer on base material, wherein, described active layer has the In-Ga-Zn-O set member,
Adopt sputtering method to form the barrier layer on described active layer, this barrier layer is used for protecting the not etched dose erosion of described active layer,
As mask described active layer is carried out etching and processing with described barrier layer.
2. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
The operation that forms described barrier layer comprises: the operation that forms described barrier layer in active layer film forming cavity behind the described active layer of formation more continuously.
3. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
The operation that forms described barrier layer comprises following operation:
Adopt sputtering method on described active layer, to form the operation of first dielectric film that constitutes by silicon oxide film or silicon nitride film;
Adopt sputtering method on described first dielectric film, to form the operation of second dielectric film that constitutes by metal oxide film.
4. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
The operation that forms described barrier layer comprises following operation:
Adopt sputtering method on described active layer, to form the operation of first dielectric film that constitutes by metal oxide film;
Adopt sputtering method on described first dielectric film, to form the operation of second dielectric film that constitutes by silicon oxide film or silicon nitride film.
5. as the manufacture method of claim 3 or 4 described field-effect transistors, it is characterized in that,
In the operation that forms described barrier layer, described first dielectric film and described second dielectric film form in same cavity continuously.
6. the manufacture method of field-effect transistor as claimed in claim 5 is characterized in that,
In the operation that forms described barrier layer, in active layer film forming cavity, form described barrier layer behind the described active layer of formation more continuously.
7. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
Described base material comprises gate electrode, forms the gate insulating film that covers described gate electrode before forming described active layer.
8. the manufacture method of field-effect transistor as claimed in claim 7 is characterized in that,
In the operation that forms described gate insulating film, adopt sputtering method to form described gate insulating film.
9. the manufacture method of field-effect transistor as claimed in claim 7 is characterized in that,
The operation that forms described gate insulating film comprises following operation:
On described gate electrode, form the operation of the first grid dielectric film that constitutes by metal oxide film;
On described first grid dielectric film, form the operation of the second grid dielectric film that constitutes by silicon oxide film or silicon nitride film.
10. the manufacture method of field-effect transistor as claimed in claim 7 is characterized in that,
The operation that forms described gate insulating film comprises following operation:
On described gate electrode, form the operation of the first grid dielectric film that constitutes by silicon oxide film or silicon nitride film;
On described first grid dielectric film, form the operation of the second grid dielectric film that constitutes by metal oxide film.
11. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
Also form the diaphragm that covers described active layer, and form the source electrode and the drain electrode of this active layer of contact.
12. the manufacturing installation of a field-effect transistor is characterized in that,
Formed active layer on the base material respectively and formed the barrier layer on this active layer by described manufacturing installation, described barrier layer is used for protecting the not etched dose erosion of described active layer,
Described manufacturing installation has first film forming room and second film forming room,
Described first film forming room comprises first sputter cathode that is used for forming described active layer on described base material, and described active layer has the In-Ga-Zn-O set member,
Described second film forming room comprises second sputter cathode that is used for forming described barrier layer on described base material.
13. the manufacturing installation of field-effect transistor according to claim 12 is characterized in that, described first film forming room and described second film forming room are shared film forming room.
14. the manufacturing installation of field-effect transistor according to claim 12 is characterized in that, described second sputter cathode comprises first target that is made of silica or silicon nitride and second target that is made of metal oxide.
15. the manufacturing installation of field-effect transistor according to claim 12 is characterized in that, also has the 3rd film forming room that forms gate insulating film on described base material.
16. the manufacturing installation of field-effect transistor according to claim 12 is characterized in that, also has to be included in the 3rd film forming room that forms the 3rd sputter cathode of gate insulating film on the described base material.
17. the manufacturing installation of field-effect transistor according to claim 16 is characterized in that, described the 3rd sputter cathode comprises the 3rd target that is made of metal oxide and the 4th target that is made of silica or silicon nitride.
18. the manufacturing installation of field-effect transistor according to claim 12 is characterized in that, also has the carrying room that can exhaust becomes vacuum state, this carrying room has the conveying robot of picking described base material to described first film forming room and described second film forming room,
Described first film forming room and described second film forming room be arranged on described carrying room around.
19. the manufacturing installation of field-effect transistor according to claim 12 is characterized in that, also has from described first film forming room to carry the carrying mechanism of described base material to described second film forming room,
The adjacent setting of described first film forming room and described second film forming room.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2008222233 | 2008-08-29 | ||
| JP2008-222233 | 2008-08-29 | ||
| PCT/JP2009/064842 WO2010024279A1 (en) | 2008-08-29 | 2009-08-26 | Method and device for manufacturing field-effect transistor |
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| CN102165570A true CN102165570A (en) | 2011-08-24 |
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|---|---|
| JP (1) | JP5417332B2 (en) |
| KR (2) | KR101273143B1 (en) |
| CN (1) | CN102165570A (en) |
| TW (1) | TWI514478B (en) |
| WO (1) | WO2010024279A1 (en) |
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Also Published As
| Publication number | Publication date |
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| TW201017774A (en) | 2010-05-01 |
| KR20110028393A (en) | 2011-03-17 |
| JP5417332B2 (en) | 2014-02-12 |
| KR20130029454A (en) | 2013-03-22 |
| JPWO2010024279A1 (en) | 2012-01-26 |
| KR101273143B1 (en) | 2013-06-17 |
| WO2010024279A1 (en) | 2010-03-04 |
| TWI514478B (en) | 2015-12-21 |
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