JP5557595B2 - Electronic device manufacturing method, thin film transistor, electro-optical device, and sensor - Google Patents
Electronic device manufacturing method, thin film transistor, electro-optical device, and sensor Download PDFInfo
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- JP5557595B2 JP5557595B2 JP2010112122A JP2010112122A JP5557595B2 JP 5557595 B2 JP5557595 B2 JP 5557595B2 JP 2010112122 A JP2010112122 A JP 2010112122A JP 2010112122 A JP2010112122 A JP 2010112122A JP 5557595 B2 JP5557595 B2 JP 5557595B2
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- 239000010409 thin film Substances 0.000 title claims description 58
- 238000004519 manufacturing process Methods 0.000 title claims description 55
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- 229910052760 oxygen Inorganic materials 0.000 claims description 177
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 176
- 239000001301 oxygen Substances 0.000 claims description 176
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- 239000000758 substrate Substances 0.000 claims description 135
- 239000004065 semiconductor Substances 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 28
- 239000012212 insulator Substances 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 14
- 238000012546 transfer Methods 0.000 claims description 11
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 4
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
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- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 3
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- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052747 lanthanoid Inorganic materials 0.000 description 3
- 150000002602 lanthanoids Chemical class 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- 229910001316 Ag alloy Inorganic materials 0.000 description 2
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- 229910052775 Thulium Inorganic materials 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 2
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- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 230000005291 magnetic effect Effects 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
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- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
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- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
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- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
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- SLIUAWYAILUBJU-UHFFFAOYSA-N pentacene Chemical compound C1=CC=CC2=CC3=CC4=CC5=CC=CC=C5C=C4C=C3C=C21 SLIUAWYAILUBJU-UHFFFAOYSA-N 0.000 description 1
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- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Description
本発明は、電子デバイスの製造方法、薄膜トランジスタ、電気光学装置及びセンサーに関する。 The present invention relates to a method for manufacturing an electronic device, a thin film transistor, an electro-optical device, and a sensor.
近年、電子デバイスとして、Ｉｎ−Ｇａ−Ｚｎ−Ｏ系(ＩＧＺＯ)をはじめとする酸素不定比性のある酸化物半導体膜をチャネル層（活性層）に用いた薄膜トランジスタの研究が盛んである。当該酸化物半導体膜は低温成膜・低温プロセスが可能であり、且つアモルファスシリコンよりも高移動度を示し、更に可視光に透明であることからプラスチック板やフィルム等の基板上にフレキシブルな透明薄膜トランジスタを形成することが可能である。 In recent years, research on thin film transistors using an oxide semiconductor film having an oxygen non-stoichiometry such as an In—Ga—Zn—O-based (IGZO) as a channel layer (active layer) has been actively conducted as an electronic device. The oxide semiconductor film is capable of low-temperature film formation and low-temperature processes, exhibits higher mobility than amorphous silicon, and is transparent to visible light, so that it is a flexible transparent thin film transistor on a substrate such as a plastic plate or film Can be formed.
このような酸化物半導体膜を用いた薄膜トランジスタを製造するに際して、界面の欠陥制御を行うことは、デバイスの安定性・制御性の観点から重要視されている。とりわけ、酸化物半導体膜を用いた活性層とゲート絶縁層の界面における欠陥は、トランジスタ特性における閾値シフトを引き起こすなど、デバイス劣化要因のひとつとされている(非特許文献１)。 In manufacturing a thin film transistor using such an oxide semiconductor film, it is regarded as important from the viewpoint of device stability and controllability to perform interface defect control. In particular, defects at the interface between the active layer and the gate insulating layer using an oxide semiconductor film are considered as one of the causes of device deterioration such as causing a threshold shift in transistor characteristics (Non-Patent Document 1).
また、電子デバイスとして、酸化物をはじめとする絶縁膜に強磁性体や磁性半導体を接合した、トンネル接合素子が近年注目を集めている。このトンネル接合素子は、既に実用化にいたっているＧＭＲ効果よりも大きな磁気抵抗を示すことが知られ、新たな高性能磁気ヘッドや新規不揮発性メモリ(ＭＲＡＭなど)への応用が大いに期待される素子である。このトンネル接合素子をはじめとする、トンネル障壁（絶縁膜）と電極層から成る電子デバイスは、絶縁膜と電極層の界面の状態がその輸送特性に大きな影響を及ぼすことが知られており(非特許文献２)、界面状態の劣化は、磁気抵抗比の低減やリーク電流の増大を招き、電子デバイスとしての価値を大きく損なう。 As an electronic device, a tunnel junction element in which a ferromagnetic material or a magnetic semiconductor is bonded to an insulating film such as an oxide has recently attracted attention. This tunnel junction element is known to exhibit a larger magnetoresistance than the GMR effect already in practical use, and is expected to be applied to new high-performance magnetic heads and new nonvolatile memories (MRAM, etc.). It is an element. In electronic devices consisting of tunnel barrier elements (insulating films) and electrode layers, including this tunnel junction element, the state of the interface between the insulating film and the electrode layer is known to have a significant effect on its transport properties (non- Patent Document 2), the deterioration of the interface state leads to a reduction in magnetoresistance ratio and an increase in leakage current, which greatly impairs the value as an electronic device.
このように、薄膜トランジスタやトンネル接合素子をはじめとする電子デバイスにおいて、活性層／ゲート絶縁層や、絶縁膜／電極層等の界面における欠陥を低減することは、素子の性能や安定性の向上に大きく寄与する。
このため、当該界面の欠陥を低減する取り組みもいくつか報告されている。代表例として薄膜トランジスタにおける報告例を以下に挙げる。
As described above, in electronic devices such as thin film transistors and tunnel junction elements, reducing defects at the interface of the active layer / gate insulating layer, insulating film / electrode layer, etc. improves the performance and stability of the element. A big contribution.
For this reason, some efforts to reduce the defects at the interface have been reported. As a representative example, a report example of a thin film transistor is given below.
特許文献１には、薄膜トランジスタにおいて、活性層形成後に３００℃以上の酸化雰囲気下でアニールすることにより、活性層とゲート絶縁層界面の欠陥となり得る酸素欠損を低減することが開示されている。 Patent Document 1 discloses that in a thin film transistor, annealing is performed in an oxidizing atmosphere at 300 ° C. or higher after forming an active layer, thereby reducing oxygen vacancies that may become defects at the interface between the active layer and the gate insulating layer.
また、特許文献２、３には、薄膜トランジスタにおいて、活性層形成後、当該活性層に酸素又はオゾンプラズマを照射する、所謂プラズマ照射処理を行うことにより、活性層とゲート絶縁層界面、及び活性層中の酸素欠損を低減することが開示されている。 In Patent Documents 2 and 3, in the thin film transistor, after the active layer is formed, the active layer is irradiated with oxygen or ozone plasma, so-called plasma irradiation treatment is performed, so that the interface between the active layer and the gate insulating layer, and the active layer are disclosed. It has been disclosed to reduce oxygen deficiency in it.
しかし、特許文献１の方法のように、高温で基板上の活性層をアニールするためには、耐熱性の高い基板を用いなければならず、基板の選択性を狭め、とりわけ有機等からなるフレキシブル基板の使用を著しく制限する。 However, as in the method of Patent Document 1, in order to anneal the active layer on the substrate at a high temperature, a substrate having high heat resistance must be used, and the selectivity of the substrate is narrowed, and in particular, a flexible made of organic or the like. The use of the substrate is severely limited.
次に、特許文献２の方法では、薄膜トランジスタをアニールすることなく酸素欠損を低減することができるものの、プラズマ照射処理を行うためには、成膜機構とは別にプラズマ発生機構を使用する必要があり、コスト及び簡便な成膜という観点から好ましくない。
また、プラズマ照射は使用法や使用条件により、かえって対象物にダメージを与えて対象物中に欠陥を増大させてしまい、予期せぬ抵抗値の変化や、活性層の低抵抗化によってスイッチ特性が喪失することが報告されている(非特許文献３,非特許文献４)。従って、プラズマ照射処理による欠陥制御は、高度な専門知識とノウハウを必要とし、成膜手法としてプロセスマージンを広くするという観点からも好ましくない。
Next, in the method of Patent Document 2, although oxygen vacancies can be reduced without annealing the thin film transistor, it is necessary to use a plasma generation mechanism in addition to the film formation mechanism in order to perform plasma irradiation processing. In view of cost and simple film formation, it is not preferable.
In addition, plasma irradiation may cause damage to the target object due to usage and usage conditions, increasing defects in the target object, and switching characteristics may be reduced due to unexpected changes in resistance value or low resistance of the active layer. Loss has been reported (Non-Patent Document 3, Non-Patent Document 4). Therefore, defect control by plasma irradiation treatment requires advanced specialized knowledge and know-how, and is not preferable from the viewpoint of widening the process margin as a film forming method.
このように、従来技術では、アニール処理やプラズマ照射処理による欠陥制御手法が用いられてきたが、低温で(例えば２００℃以下のプロセス温度)で、且つ特別な機構と高度な知識を必要とせず、簡便に界面の欠陥を低減する手法は存在しなかった。 As described above, in the prior art, a defect control method using annealing treatment or plasma irradiation treatment has been used, but at a low temperature (for example, a process temperature of 200 ° C. or less) and does not require special mechanisms and advanced knowledge. There is no simple method for reducing the interface defects.
本発明は、簡便に界面の欠陥を低減することが可能な電子デバイスの製造方法、薄膜トランジスタ、電気光学装置及びセンサーを提供することを目的とする。 An object of the present invention is to provide an electronic device manufacturing method, a thin film transistor, an electro-optical device, and a sensor that can easily reduce defects at an interface.
本発明の上記課題は下記の手段によって解決された。
＜１＞大気と遮断された真空成膜室内で、基板上に酸素不定比性のある酸化物半導体を含有する第１層を成膜する第１成膜工程と、前記第１層上に前記第１層と同一材料又は異なる材料からなる第２層を成膜する第２成膜工程と、前記第１成膜工程後前記第２成膜工程前までの間、前記第１層を、前記真空成膜室を含む大気と遮断された室内で、前記第１成膜工程における前記真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する分圧制御工程と、を有する電子デバイスの製造方法。
＜２＞前記分圧制御工程では、前記第１成膜工程後前記第２成膜工程前までの間の酸素分圧を、前記第１成膜工程における酸素分圧に比べ、２．１×１０-3Ｐａ以上高くした、＜１＞に記載の電子デバイスの製造方法。
＜３＞前記真空成膜室は、第１真空成膜室及び前記第１真空成膜室と搬送室を介して接続される第２真空成膜室を含み、前記第１成膜工程では、前記第１真空成膜室で前記第１層を成膜し、前記第２成膜工程では、前記第２真空成膜室で前記第２層を成膜し、前記分圧制御工程では、前記第１真空成膜室内、前記搬送室内、及び前記第２真空成膜室内の酸素分圧を、前記第１成膜工程における前記第１真空成膜室内の酸素分圧よりも高くする、＜１＞又は＜２＞に記載の電子デバイスの製造方法。
＜４＞前記第１成膜工程及び前記第２成膜工程では、前記真空成膜室と、前記真空成膜室内に配置され、ターゲットを保持するターゲットホルダと、前記ターゲットホルダと向き合って配置され、前記基板を保持する基板ホルダと、前記ターゲットホルダと前記基板との間にプラズマ空間を生成するプラズマ生成部とを備えたスパッタ装置により成膜し、前記第１成膜工程及び前記第２成膜工程を同一の前記真空成膜室内で行う場合には、前記第１成膜工程後前記第２成膜工程前までの間、前記分圧制御工程を行うと共に、前記同一の真空成膜室内において前記ターゲットホルダと前記基板との間にシャッターを配置する、＜１＞又は＜２＞に記載の電子デバイスの製造方法。
＜５＞前記第１層は、Ｉｎ,Ｇａ,Ｚｎ及びＳｎのうち少なくとも１種類の元素を含有する酸化物半導体層である、＜１＞〜＜４＞の何れか１つに記載の電子デバイスの製造方法。
＜６＞前記第１層は、ＩｎｘＧａｙＺｎｚＯδ（x,y,z,δ＞０）を含有する酸化物半導体層である、＜５＞に記載の電子デバイスの製造方法。
＜７＞前記基板は、可撓性を有し、前記第１層及び前記第２層は非晶質である、＜６＞に記載の電子デバイスの製造方法。
＜８＞前記第１成膜工程では、半導体からなる前記第１層を成膜し、前記第２成膜工程では、絶縁体からなる前記第２層を成膜する、＜１＞〜＜７＞の何れか１つに記載の電子デバイスの製造方法。
＜９＞前記第１成膜工程の前に、前記真空成膜室内で前記基板上に酸素不定比性のある酸化物半導体を含有する第３層を成膜する成膜工程を含み、前記第１成膜工程では、前記基板上に前記第３層を介して前記第１層を成膜し、かつ、前記第３層の成膜工程後前記第１成膜工程前までの間、前記第３層を、前記第３層の成膜工程における前記真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する、＜１＞〜＜８＞の何れか１つに記載の電子デバイスの製造方法。
＜１０＞＜１＞〜＜９＞の何れか１つに記載の電子デバイスの製造方法を用いて、前記第１層として活性層を成膜して作製された、薄膜トランジスタ。
＜１１＞＜１０＞に記載の薄膜トランジスタを備えた、電気光学装置。
＜１２＞＜１０＞に記載の薄膜トランジスタを備えた、センサー。
The above-described problems of the present invention have been solved by the following means.
<1> A first film formation step of forming a first layer containing an oxide semiconductor having oxygen non-stoichiometry on a substrate in a vacuum film formation chamber cut off from the atmosphere, and the first layer on the first layer Between the second film-forming step of forming a second layer made of the same material as or a different material from the first layer, and after the first film-forming step and before the second film-forming step, the first layer is A partial pressure control step of maintaining the oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation step in a room that is shut off from the atmosphere including the vacuum film formation chamber. Production method.
<2> In the partial pressure control step, the oxygen partial pressure between the first film formation step and before the second film formation step is 2.1 × compared with the oxygen partial pressure in the first film formation step. The method for producing an electronic device according to <1>, which is increased by 10 −3 Pa or more.
<3> The vacuum film formation chamber includes a first vacuum film formation chamber and a second vacuum film formation chamber connected to the first vacuum film formation chamber via a transfer chamber. In the first film formation step, Forming the first layer in the first vacuum film forming chamber; forming the second layer in the second vacuum film forming chamber in the second film forming step; The oxygen partial pressure in the first vacuum film formation chamber, the transfer chamber, and the second vacuum film formation chamber is set higher than the oxygen partial pressure in the first vacuum film formation chamber in the first film formation step, <1 > Or <2> A method for producing an electronic device according to <2>.
<4> In the first film formation step and the second film formation step, the vacuum film formation chamber and the vacuum film formation chamber are disposed so as to face the target holder and the target holder holding the target. Forming a film by a sputtering apparatus including a substrate holder for holding the substrate and a plasma generation unit for generating a plasma space between the target holder and the substrate, and performing the first film forming step and the second film forming step. When the film process is performed in the same vacuum film formation chamber, the partial pressure control process is performed after the first film formation process and before the second film formation process, and the same vacuum film formation chamber is used. The method for manufacturing an electronic device according to <1> or <2>, wherein a shutter is disposed between the target holder and the substrate.
< 5 > The electronic device according to any one of <1> to <4>, wherein the first layer is an oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn. Manufacturing method.
< 6 > The method for manufacturing an electronic device according to < 5 >, wherein the first layer is an oxide semiconductor layer containing In x Ga y Zn z O δ (x, y, z, δ> 0).
< 7 > The method for manufacturing an electronic device according to < 6 >, wherein the substrate has flexibility, and the first layer and the second layer are amorphous.
< 8 > In the first film formation step, the first layer made of a semiconductor is formed, and in the second film formation step, the second layer made of an insulator is formed, <1> to < 7 The manufacturing method of the electronic device as described in any one of>.
< 9 > including a film-forming step of forming a third layer containing an oxide semiconductor having oxygen non-stoichiometry on the substrate in the vacuum film-forming chamber before the first film-forming step, In the first film forming step, the first layer is formed on the substrate via the third layer, and after the third layer forming step and before the first film forming step, the first layer is formed. The electronic device according to any one of <1> to < 8 >, wherein the three layers are maintained under an oxygen partial pressure higher than an oxygen partial pressure in the vacuum film formation chamber in the film formation step of the third layer. Production method.
< 10 > A thin film transistor manufactured by forming an active layer as the first layer using the method for manufacturing an electronic device according to any one of <1> to < 9 >.
< 11 > An electro-optical device provided with the thin film transistor according to < 10 >.
< 12 > A sensor comprising the thin film transistor according to < 10 >.
本発明によれば、簡便に界面の酸素欠損を低減することが可能な電子デバイスの製造方法、薄膜トランジスタ、電気光学装置及びセンサーを提供することができた。 According to the present invention, it is possible to provide an electronic device manufacturing method, a thin film transistor, an electro-optical device, and a sensor that can easily reduce oxygen vacancies at an interface.
以下、本発明の電子デバイスの製造方法、薄膜トランジスタ、電気光学装置及びセンサーの一の実施の形態について、図面を用いて説明する。なお、実質的に同様の機能を有するものには、全図面を通して同じ符号を付して説明し、場合によってはその説明を省略することがある。 Hereinafter, an embodiment of an electronic device manufacturing method, a thin film transistor, an electro-optical device, and a sensor according to the present invention will be described with reference to the drawings. Note that components having substantially the same functions are described with the same reference numerals throughout the drawings, and description thereof may be omitted in some cases.
（第１実施形態）
図１は、本発明の第１実施形態に係る電子デバイスの製造方法の製造手順を示す図である。
−基板の用意−
本発明の第１実施形態に係る電子デバイスの製造方法は、まず図１（Ａ）に示すように基板１０を用意する。基板１０は、後述するプロセスが全て低温（例えば２００℃以下）で行うことが可能なため、可撓性のある樹脂基板等の耐熱性の低い基板も使用でき、幅広い種類の基板を用途に応じて適宜選択できる。
(First embodiment)
FIG. 1 is a diagram showing a manufacturing procedure of an electronic device manufacturing method according to the first embodiment of the present invention.
−Preparation of substrate−
In the method for manufacturing an electronic device according to the first embodiment of the present invention, first, a substrate 10 is prepared as shown in FIG. Since the substrate 10 can perform all the processes described later at a low temperature (for example, 200 ° C. or less), a substrate having low heat resistance such as a flexible resin substrate can be used. Can be selected as appropriate.
−第１成膜工程−
次に、図１（Ｂ）に示すように、大気と遮断された真空成膜室内で、基板１０上に酸素不定比性のある酸化物を含有する第１層１２を成膜する第１成膜工程を行う。
なお、上記真空成膜室の「真空」とは、成膜室内の真空到達度が、１０−８Ｐａ以上１０−１以下Ｐａである場合をいう。また、「酸化物を含有」とは、第１層１２を構成する構成成分のうち全部又は一部が、酸化物である場合の両方を意味する。
-First film formation process-
Next, as shown in FIG. 1B, a first layer 12 for forming a first layer 12 containing an oxide having oxygen non-stoichiometry is formed on a substrate 10 in a vacuum film formation chamber cut off from the atmosphere. A film process is performed.
Note that “vacuum” in the vacuum film formation chamber refers to a case where the degree of vacuum in the film formation chamber is 10 −8 Pa or more and 10 −1 or less Pa. Further, “containing an oxide” means both cases where all or part of the constituent components constituting the first layer 12 is an oxide.
この第１成膜工程では、基板１０上に直接第１層１２を成膜する場合に限定されず、基板１０上に間接的に第１層１２を成膜する場合も含み、間接的に第１層１２を成膜する場合には、例えば基板１０上に成膜された導電体層、半導体層、若しくは絶縁体層上、又これらの積層構造上に成膜する場合が挙げられる。 This first film formation step is not limited to the case where the first layer 12 is directly formed on the substrate 10, but includes the case where the first layer 12 is indirectly formed on the substrate 10. In the case where the single layer 12 is formed, for example, there is a case where the single layer 12 is formed on a conductor layer, a semiconductor layer, or an insulator layer formed on the substrate 10 or on a stacked structure thereof.
基板１０上に成膜する第１層１２は、酸素不定比性を有しているものであれば、導体、半導体又は絶縁体のいずれであっても良い。なお、本実施形態において、「導体」とは、比抵抗値が１０-2Ωｃｍ未満の物質を指し、「半導体」とは比抵抗値が１０-2Ωｃｍ以上１０７Ωｃｍ以下の物質を指し、絶縁体とは比抵抗値が１０７ Ωｃｍ超の物質を指す。
第１層１２が導体である場合には、Ａｌ,Ｓｃ,Ｔｉ,Ｍｎ,Ｆｅ,Ｇａ,Ｙ,Ｉｎ,Ｓｎ,Ｈｏ,Ｅｒ,Ｔｍ,Ｙｂ,Ｌｕ,Ｍｇ,Ｃａ,Ｎｉ,Ｚｎ,Ｓｒ及びＢａからなる群から選ばれた少なくとも１種の元素を含有することが好ましい。
第１層１２が半導体である場合には、第１層１２がＡｌ,Ｓｃ,Ｔｉ,Ｍｎ,Ｆｅ,Ｇａ,Ｙ,Ｉｎ,Ｓｎ,Ｈｏ,Ｅｒ,Ｔｍ,Ｙｂ,Ｌｕ,Ｍｇ,Ｃａ,Ｎｉ,Ｚｎ,Ｓｒ及びＢａからなる群から選ばれた少なくとも１種の元素を含有することが好ましく、Ｉｎ,Ｇａ,Ｚｎ及びＳｎのうち少なくとも１種類の元素を含有することがより好ましく、ＩｎｘＧａｙＺｎｚＯδ（x,y,z,δ＞０）を含有することが更に好ましい。
The first layer 12 formed on the substrate 10 may be a conductor, a semiconductor, or an insulator as long as it has oxygen nonstoichiometry. In this embodiment, “conductor” refers to a substance having a specific resistance value of less than 10 −2 Ωcm, and “semiconductor” refers to a substance having a specific resistance value of 10 −2 Ωcm to 10 7 Ωcm, An insulator refers to a substance having a specific resistance value exceeding 10 7 Ωcm.
When the first layer 12 is a conductor, Al, Sc, Ti, Mn, Fe, Ga, Y, In, Sn, Ho, Er, Tm, Yb, Lu, Mg, Ca, Ni, Zn, Sr and It is preferable to contain at least one element selected from the group consisting of Ba.
When the first layer 12 is a semiconductor, the first layer 12 is made of Al, Sc, Ti, Mn, Fe, Ga, Y, In, Sn, Ho, Er, Tm, Yb, Lu, Mg, Ca, Ni. It is preferable to contain at least one element selected from the group consisting of Zn, Sr, and Ba, more preferably at least one element selected from In, Ga, Zn, and Sn, and In x Ga. y Zn z O δ (x, y, z, δ> 0) is more preferably contained.
また、第１層１２が絶縁体である場合には、ＩｎＧａＺｎＯ４−δ（δ≧０）,ＳｉＯＮ、ＳｉＯ２、Ａｌ２Ｏ３、Ｙ２Ｏ３、ＭｇＯ、ＴｉＯ２、ＧｅＯ２、Ｔａ２Ｏ５、ＨｆＯ２、Ｓｃ２Ｏ３、Ｇａ２Ｏ３、ＺｒＯ２、Ｌｎ２Ｏ３(ランタノイドの酸化物)等又はこれらの化合物を少なくとも二つ以上含有することが好ましい。なお、これら列挙した中でＩｎＧａＺｎＯ４−δ（δ≧０）以外の材料には、酸素欠損量δの表記がないが、例えばヨードメトリーやクーロメトリー等の既存の酸素量決定手法で測定しきれないオーダーであっても多少の酸素不定比性を有していれば、本実施形態の絶縁体として用いることができるものとする。 When the first layer 12 is an insulator, InGaZnO 4-δ (δ ≧ 0), SiON, SiO 2 , Al 2 O 3 , Y 2 O 3 , MgO, TiO 2 , GeO 2 , Ta 2 It is preferable to contain at least two of O 5 , HfO 2 , Sc 2 O 3 , Ga 2 O 3 , ZrO 2 , Ln 2 O 3 (lanthanoid oxide) or the like. In the enumeration, materials other than InGaZnO 4-δ (δ ≧ 0) do not have the oxygen deficit amount δ, but cannot be measured by an existing oxygen amount determination method such as iodometry or coulometry. Even if it is an order, it can be used as an insulator of this embodiment as long as it has some oxygen non-stoichiometry.
また、第１層１２は、結晶相、非晶質相、あるいは微結晶を含有する膜において有効であるが、膜の均一性の観点から非晶質であることが好ましい。理由としては、非晶質の膜は大面積にわたって均一な膜を形成し易く、多結晶のような粒界が存在しないため素子特性のバラツキを抑えることが容易だからである。また、例えば非晶質ＩＧＺＯ膜等の非晶質膜であれば、低温(基板温度２００℃以下)で成膜可能であり、基板１０としてプラスチック基板のような可撓性のある樹脂基板上に形成し易い。従って、第１層１２を有する薄膜トランジスタ等の電子デバイスを搭載した樹脂基板を備えるフレキシブルディスプレイ等への適用がより容易となる。
なお、第１層１２が非晶質であるかどうかは、Ｘ線回折測定により確認することが出来る。即ちＸ線回折測定により、結晶構造を示す明確なピークが検出されなかった場合は、第１層１２は非晶質であると判断することが出来る。
The first layer 12 is effective in a film containing a crystalline phase, an amorphous phase, or a microcrystal, but is preferably amorphous from the viewpoint of film uniformity. The reason is that an amorphous film can easily form a uniform film over a large area, and since there is no grain boundary like a polycrystal, it is easy to suppress variations in device characteristics. Further, for example, an amorphous film such as an amorphous IGZO film can be formed at a low temperature (substrate temperature of 200 ° C. or lower), and the substrate 10 is formed on a flexible resin substrate such as a plastic substrate. Easy to form. Therefore, application to a flexible display or the like including a resin substrate on which an electronic device such as a thin film transistor having the first layer 12 is mounted becomes easier.
Whether or not the first layer 12 is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, it can be determined that the first layer 12 is amorphous.
第１層１２の成膜は、例えば、印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜する。
ここで、第１成膜工程中の真空成膜室内の酸素分圧は、特に限定されないが、例えば１．０×１０-1Ｐａ以下１．０×１０-4Ｐａ以上である。
The film formation of the first layer 12 is, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film is formed according to a method appropriately selected in consideration of suitability with the material to be used.
Here, the oxygen partial pressure in the vacuum film formation chamber during the first film formation step is not particularly limited, but is, for example, 1.0 × 10 −1 Pa or less and 1.0 × 10 −4 Pa or more.
−第２成膜工程−
次に、図１（Ｃ）に示すように、大気と遮断された真空成膜室内で、第１層１２上に当該第１層１２と同一材料又は異なる材料からなる第２層１４を成膜する第２成膜工程を行う。
-Second film formation process-
Next, as shown in FIG. 1C, a second layer 14 made of the same material as or a different material from the first layer 12 is formed on the first layer 12 in a vacuum film formation chamber that is cut off from the atmosphere. A second film forming step is performed.
第２層１４は、第１層１２同様、導体、半導体又は絶縁体のいずれであっても良く、結晶相、非晶質相、あるいは微結晶を含有しても良い。ただし、第１層１２に比べ、第２層１４は特に酸素不定比性のある酸化物を含有していなくてもよい。 Like the first layer 12, the second layer 14 may be a conductor, a semiconductor, or an insulator, and may contain a crystalline phase, an amorphous phase, or a microcrystal. However, compared with the first layer 12, the second layer 14 may not contain an oxide having oxygen nonstoichiometry.
第２層１４の成膜方法については、第１層１２と同様の方法が挙げられるが、第２成膜工程中の諸条件、例えば第２成膜工程中の真空成膜室内の酸素分圧は、第１成膜工程中の真空成膜室内の酸素分圧と同一であっても相違していても良い。また、後述する分圧制御工程で使用する酸素分圧よりも高くしてもよい。 Examples of the method for forming the second layer 14 include the same methods as those for the first layer 12, but various conditions during the second film formation step, for example, the oxygen partial pressure in the vacuum film formation chamber during the second film formation step. These may be the same as or different from the oxygen partial pressure in the vacuum film formation chamber during the first film formation process. Moreover, you may make it higher than the oxygen partial pressure used in the partial pressure control process mentioned later.
ここで、第１成膜工程及び第２成膜工程で使用する「真空成膜室」には、単一の真空成膜室だけでなく、第１真空成膜室及び第１真空成膜室と搬送室を介して接続される第２真空成膜室等の複数の真空成膜室からなる場合を含む。したがって、本発明の第１実施形態に係る電子デバイスの製造方法は、単一の真空成膜室内で第１成膜工程及び第２成膜工程を行っても良いし、第１成膜工程と第２成膜工程を、大気と遮断された搬送室によって接続された２つ以上の真空成膜室内で分けて行われても良い。
なお、大気と遮断された搬送室によって接続された２つ以上の真空成膜室内で成膜を行う場合とは、例えば、第１成膜工程では、第１真空成膜室内で第１層１２を成膜し、第１層１２が積層された基板１０を搬送室を介して第２真空成膜室に搬送し、第２成膜工程では、第２真空成膜室内で第１層１２上に第２層１４を成膜する場合が挙げられる。
単一の真空成膜室内にて全ての成膜工程を行った場合には、基板１０の搬送工程に付随するコストの削減や、成膜工程の時間短縮が期待できる。一方で、大気と遮断された搬送室によって接続された２つ以上の真空成膜室内で成膜を行う場合は、例えば一つの真空成膜室内において必ず特定材料の成膜のみを行うことによって、不純物の混入を防ぎ膜特性の向上が期待できる。
Here, the “vacuum film forming chamber” used in the first film forming process and the second film forming process includes not only a single vacuum film forming chamber but also the first vacuum film forming chamber and the first vacuum film forming chamber. And a plurality of vacuum film forming chambers such as a second vacuum film forming chamber connected via a transfer chamber. Therefore, in the method for manufacturing an electronic device according to the first embodiment of the present invention, the first film formation step and the second film formation step may be performed in a single vacuum film formation chamber. The second film formation step may be performed separately in two or more vacuum film formation chambers connected by a transfer chamber that is cut off from the atmosphere.
Note that the case where film formation is performed in two or more vacuum film formation chambers connected by a transfer chamber cut off from the atmosphere is, for example, in the first film formation step, the first layer 12 in the first vacuum film formation chamber. The substrate 10 on which the first layer 12 is laminated is transferred to the second vacuum film forming chamber through the transfer chamber. In the second film forming step, the first layer 12 is formed on the first layer 12 in the second vacuum film forming chamber. In the case where the second layer 14 is formed.
In the case where all the film forming steps are performed in a single vacuum film forming chamber, it is possible to reduce the cost associated with the transporting process of the substrate 10 and shorten the time of the film forming process. On the other hand, in the case where film formation is performed in two or more vacuum film formation chambers connected by a transfer chamber that is cut off from the atmosphere, for example, by performing only film formation of a specific material in one vacuum film formation chamber, It can be expected to improve the film properties by preventing impurities from entering.
−分圧制御工程−
図２は、本発明の第１実施形態に係る電子デバイスの製造方法における各工程中の基板１０周囲の酸素分圧の状態を示した図である。
図２に示すように、図１（Ｂ）に示す工程と図１（Ｃ）に示す工程までの間、すなわち第１成膜工程後第２成膜工程前までの間は、真空成膜室を含む大気と遮断された室内で、第１層１２を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する分圧制御工程を行う。
-Partial pressure control process-
FIG. 2 is a diagram showing the state of oxygen partial pressure around the substrate 10 during each step in the method for manufacturing an electronic device according to the first embodiment of the present invention.
As shown in FIG. 2, a vacuum film formation chamber is provided between the step shown in FIG. 1B and the step shown in FIG. 1C, that is, after the first film formation process and before the second film formation process. A partial pressure control process is performed in which the first layer 12 is kept under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation step.
この分圧制御工程では、第１成膜工程後第２成膜工程前までの間、第１層１２を、第１成膜工程における真空成膜室内の酸素分圧よりも、２．１×１０-3Ｐａ以上高い酸素分圧下に保持することが好ましい。また、絶対値として、５．９×１０-3Ｐａ以上であることが好ましい。理由としては、後述する第１層１２と第２層１４との界面の酸素欠損を確実に低減することが可能となるからである。 In this partial pressure control process, between the first film formation process and before the second film formation process, the first layer 12 is 2.1 × than the oxygen partial pressure in the vacuum film formation chamber in the first film formation process. It is preferable to maintain under an oxygen partial pressure which is 10 −3 Pa or higher. Moreover, it is preferable that it is 5.9 * 10 < -3 > Pa or more as an absolute value. The reason is that oxygen vacancies at the interface between the first layer 12 and the second layer 14 described later can be reliably reduced.
なお、「第１成膜工程後第２成膜工程前までの間」とは、酸素欠損を確実に低減するという観点から、第１成膜工程直後第２成膜工程直前までの間であることが好ましいが、第１成膜工程後第２成膜工程前までの少なくとも一部の間であっても良い。
実際、第１成膜工程及び第２成膜工程に使用する成膜装置の種類によっては、第２成膜工程の直前に、第２成膜工程で使用する酸素分圧に切り替えるための時間が必要で、第１成膜工程後第２成膜工程前までの間でも、第２成膜工程で使用する酸素分圧と同じ酸素分圧になっている時間（例えば２〜５秒）が存在する場合がある。このような場合において、第２成膜工程で使用する酸素分圧が、第１成膜工程で使用する酸素分圧以下であると、第１成膜工程後第２成膜工程前までの間のうち、第２成膜工程直前の一期間は、第１層１２を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持することにはならないが、第１成膜工程後第２成膜工程前までの間のうち、少なくともその他の期間は、第１層１２を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持できる。無論、上記切り替え時間の必要がない成膜装置を用いれば、上述のように第１成膜工程直後第２成膜工程直前までの間、第１層１２を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持することも可能である。
Note that “between the first film formation process and before the second film formation process” is a period immediately after the first film formation process and immediately before the second film formation process from the viewpoint of reliably reducing oxygen vacancies. Although it is preferable, it may be at least partly between the first film formation process and the second film formation process.
In fact, depending on the type of film forming apparatus used in the first film forming process and the second film forming process, the time for switching to the oxygen partial pressure used in the second film forming process immediately before the second film forming process. Necessary, there is a time (for example, 2 to 5 seconds) in which the oxygen partial pressure used in the second film forming step is the same as the oxygen partial pressure before the second film forming step. There is a case. In such a case, when the oxygen partial pressure used in the second film forming step is equal to or lower than the oxygen partial pressure used in the first film forming step, the period after the first film forming step and before the second film forming step is reached. Among these, the first layer 12 is not held under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation step for one period immediately before the second film formation step. The first layer 12 is kept under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation process during at least other periods after the first film formation process and before the second film formation process. Can hold. Needless to say, if a film forming apparatus that does not require the switching time is used, the first layer 12 is vacuum-formed in the first film forming process immediately after the first film forming process and immediately before the second film forming process as described above. It is also possible to keep the oxygen partial pressure higher than the oxygen partial pressure in the membrane chamber.
また、図２では、第１成膜工程直後に、基板１０周囲の酸素分圧を第１成膜工程における酸素分圧から所定の酸素分圧に急激に高くなるよう制御しているが、徐々に高くなるよう制御しても良い。同様に、基板１０周囲の酸素分圧を当該高くした所定の酸素分圧から、第２成膜工程における酸素分圧に急激に低くなるよう制御しているが、徐々に低くなるよう制御しても良い。 In FIG. 2, immediately after the first film formation step, the oxygen partial pressure around the substrate 10 is controlled so as to increase rapidly from the oxygen partial pressure in the first film formation step to a predetermined oxygen partial pressure. You may control so that it may become high. Similarly, the oxygen partial pressure around the substrate 10 is controlled so as to rapidly decrease from the predetermined oxygen partial pressure that has been increased to the oxygen partial pressure in the second film forming step, but is controlled so as to gradually decrease. Also good.
また、第１成膜工程後第２成膜工程前までの間、第１層１２を、真空成膜室を含む大気と遮断された室内で、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持するには、単一の真空成膜室内で第１成膜工程及び第２成膜工程を行う場合は、当該単一の真空成膜室内のみを第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧に制御する。また、上述のような第１成膜工程と第２成膜工程を、大気と遮断された搬送室によって接続された２つ以上の真空成膜室内で分けて行う場合には、第１真空成膜室内、搬送室内及び第２真空成膜室内の全ての室内を第１成膜工程における第１真空成膜室内の酸素分圧よりも高い酸素分圧に制御する。 In addition, the oxygen in the vacuum film formation chamber in the first film formation step is formed in a room that is cut off from the atmosphere including the vacuum film formation chamber after the first film formation process and before the second film formation process. In order to maintain the oxygen partial pressure higher than the partial pressure, when the first film forming step and the second film forming step are performed in a single vacuum film forming chamber, only the single vacuum film forming chamber is the first. The oxygen partial pressure is controlled to be higher than the oxygen partial pressure in the vacuum film forming chamber in the film forming process. Further, when the first film forming process and the second film forming process as described above are performed separately in two or more vacuum film forming chambers connected by a transfer chamber that is cut off from the atmosphere, the first vacuum forming process is performed. All the chambers in the film chamber, the transfer chamber, and the second vacuum film forming chamber are controlled to have an oxygen partial pressure higher than the oxygen partial pressure in the first vacuum film forming chamber in the first film forming step.
−成膜終了−
第２成膜工程後は、第１層１２及び第２層１４が積層された基板１０を、真空成膜室から大気中に取り出す。この結果、図３に示すような、電子デバイス２０を得ることができる。
-Finish film formation-
After the second film formation step, the substrate 10 on which the first layer 12 and the second layer 14 are laminated is taken out from the vacuum film formation chamber to the atmosphere. As a result, an electronic device 20 as shown in FIG. 3 can be obtained.
得られる電子デバイス２０には、例えば薄膜トランジスタ、トンネル接合素子、電気光学装置及びメモリデバイス等が含まれる。
これらの電子デバイスの中で電気光学装置とは、電気的作用によって発光するあるいは外部からの光の状態を変化させる電気光学素子を備えた装置一般をいい、自ら光を発するものと外部からの光の通過を制御するもの双方を含む。例えば、電気光学素子として、液晶素子、電気泳動粒子が分散した分散媒体を有する電気泳動素子、ＥＬ（エレクトロルミネッセンス）素子、電界の印加により発生した電子を発光板に当てて発光させる電子放出素子を備えたアクティブマトリクス型の表示装置等をいう。
The obtained electronic device 20 includes, for example, a thin film transistor, a tunnel junction element, an electro-optical device, a memory device, and the like.
Among these electronic devices, an electro-optical device is a general device equipped with an electro-optical element that emits light by an electric action or changes the state of light from the outside. Including those that control the passage of For example, as an electro-optical element, a liquid crystal element, an electrophoretic element having a dispersion medium in which electrophoretic particles are dispersed, an EL (electroluminescence) element, and an electron-emitting element that emits light by applying electrons generated by applying an electric field to a light-emitting plate An active matrix display device provided.
−効果−
ここで、第１成膜工程後第２成膜工程前までの間、基板１０を例えば第１成膜工程と同じ酸素分圧下のまま保持していると、第１層１２の表面から酸素の一部が抜け出し、そのまま第２成膜工程を行うと、第１層１２の表面（第１層１２と第２層１４との界面）からは酸素の出入りが抑制され、第１層１２の表面から一部の酸素が抜け出した状態、すなわち酸素欠損量が大きい状態で第１層１２表面の酸素含有量がほぼ固定されてしまう。
-Effect-
Here, during the period from the first film formation process to the second film formation process, if the substrate 10 is held under the same oxygen partial pressure as that in the first film formation process, for example, oxygen is released from the surface of the first layer 12. If a part of the surface is removed and the second film forming process is performed as it is, the entry and exit of oxygen is suppressed from the surface of the first layer 12 (the interface between the first layer 12 and the second layer 14), and the surface of the first layer 12 Thus, the oxygen content on the surface of the first layer 12 is almost fixed in a state where a part of oxygen escapes from the surface, that is, in a state where the oxygen deficiency amount is large.
これに対し、本発明の第１実施形態の電子デバイス２０の製造方法によれば、第１成膜工程後第２成膜工程前までの間は、真空成膜室を含む大気と遮断された室内で、第１層１２を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する分圧制御工程を行うことによって、第１成膜工程後第２成膜工程前までの間に第１層１２の表面から酸素の一部が抜け出すことが抑制される。この後は、第２成膜工程により第２層１４が第１層１２上に成膜されるため、第１層１２の表面（第１層１２と第２層１４との界面）からは酸素が抜け難くなり、酸素欠損量がゼロ又は小さい状態で第１層１２表面の酸素含有量がほぼ固定される。
従って、第１層１２と第２層１４との界面の欠陥としての酸素欠損を低減した電子デバイス２０を得ることができる。
そして、このような製造方法の場合、プラズマ照射処理に比べ、特別な機構と高度な知識を必要としないため、簡便に第１層１２と第２層１４との界面の欠陥を低減した電子デバイス２０を得ることが可能となる。また、プラズマ照射処理に比べ、プラズマを直接第１層１２表面に照射しないため、当該第１層１２表面にプラズマダメージを与えることを抑制でき、プラズマダメージによる第１層１２と第２層１４との界面の欠陥を低減することができる。
また、第１層１２をアニールする場合に比べ、第１層や第２層の材料にもよるが、例えば非晶質ＩＧＺＯ等を第１層１２及び第２層１４の材料とする場合、低温で(例えば２００℃以下のプロセス温度)で製造方法の全工程を実施することが可能となる。従って、基板１０として、可撓性のある樹脂基板等の耐熱性の低い基板も使用でき、幅広い種類の基板を用途に応じて適宜選択できる。
On the other hand, according to the manufacturing method of the electronic device 20 of the first embodiment of the present invention, the atmosphere including the vacuum film forming chamber was shut off after the first film forming process and before the second film forming process. By performing a partial pressure control step in which the first layer 12 is maintained under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation step, the second layer is formed after the first film formation step. It is suppressed that a part of oxygen escapes from the surface of the first layer 12 before the film process. Thereafter, since the second layer 14 is formed on the first layer 12 by the second film formation step, oxygen is introduced from the surface of the first layer 12 (interface between the first layer 12 and the second layer 14). The oxygen content on the surface of the first layer 12 is substantially fixed in a state where the amount of oxygen deficiency is zero or small.
Therefore, the electronic device 20 in which oxygen vacancies as defects at the interface between the first layer 12 and the second layer 14 are reduced can be obtained.
In the case of such a manufacturing method, a special mechanism and advanced knowledge are not required as compared with the plasma irradiation treatment, and thus an electronic device in which defects at the interface between the first layer 12 and the second layer 14 are simply reduced. 20 can be obtained. Further, since the plasma is not directly irradiated on the surface of the first layer 12 as compared with the plasma irradiation treatment, it is possible to suppress the plasma damage to the surface of the first layer 12, and the first layer 12 and the second layer 14 caused by the plasma damage Defects at the interface can be reduced.
Also, compared with the case where the first layer 12 is annealed, depending on the materials of the first layer and the second layer, for example, when amorphous IGZO or the like is used as the material of the first layer 12 and the second layer 14, the temperature is low. (For example, at a process temperature of 200 ° C. or lower), all the steps of the manufacturing method can be performed. Therefore, a substrate having low heat resistance such as a flexible resin substrate can be used as the substrate 10, and a wide variety of substrates can be appropriately selected according to the application.
−その他の工程−
本発明の第１実施形態に係る電子デバイス２０の製造方法では、以上の工程の他に様々な工程を適宜追加することが可能である。
例えば、第１成膜工程の前に、真空成膜室内で基板１０上に酸素不定比性のある酸化物を含有する第３層（不図示）を成膜する成膜工程を追加することができ、この場合には、第１成膜工程で、基板１０上に第３層を介して第１層１２を成膜し、かつ、第３層の成膜工程後第１成膜工程前までの間、第３層を、第３層の成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する。
同様に、第２成膜工程の後に、真空成膜室内で第２層１４上に第４層（不図示）を成膜する成膜工程を追加することができる。そして、第２層１４が酸素不定比性のある酸化物を含有する場合には、第２層１４の成膜工程後第４層の成膜工程前までの間、第２層１４を、第２層１４の成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する。
このように、３層以上の複数の層構造からなる電子デバイスにおいて、酸素不定比性のある酸化物の層上に所定の層を積層する場合には、本発明の第１実施形態に係る電子デバイスの製造方法を適用することが可能である。
-Other processes-
In the method for manufacturing the electronic device 20 according to the first embodiment of the present invention, various steps can be added as appropriate in addition to the above steps.
For example, before the first film forming process, a film forming process for forming a third layer (not shown) containing an oxide having oxygen non-stoichiometry on the substrate 10 in the vacuum film forming chamber may be added. In this case, in the first film formation step, the first layer 12 is formed on the substrate 10 via the third layer, and after the third layer formation step and before the first film formation step. Meanwhile, the third layer is held under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the third layer film formation step.
Similarly, a film forming process for forming a fourth layer (not shown) on the second layer 14 in the vacuum film forming chamber can be added after the second film forming process. When the second layer 14 contains an oxygen non-stoichiometric oxide, the second layer 14 is formed between the second layer 14 and the fourth layer before the fourth layer. It is kept under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film forming chamber in the film forming process of the two layers 14.
As described above, in the electronic device having a plurality of layer structures of three or more layers, when a predetermined layer is stacked on the oxide non-stoichiometric oxide layer, the electron according to the first embodiment of the present invention is used. It is possible to apply a device manufacturing method.
ここで、図３に示す電子デバイス２０を含め、複数の層構造からなる電子デバイスにおいて、層構造の最上層が、酸素不定比性のある酸化物を含有する場合には、電子デバイスが大気中に取り出されると、大気中の酸素分圧は、２．０×１０4Ｐａ程度と真空成膜室内の酸素分圧に比べ非常に高く、かつ当該最上層は大気中に露出しているため、当該最上層に酸素が入り、当該最上層の酸素欠損は補償され得るので、上述のような分圧制御工程は必要としない。
ただし、第１成膜工程後第２成膜工程前までの間に、一旦基板１０を大気中に取り出しても、上述のような分圧制御工程は必要である。なぜなら、基板１０上に成膜された第１層１２の表面は、大気中に取り出すことによって酸素欠損が補償されても、基板１０を再度真空成膜室内に入れると、その酸素分圧の低さによって、第１層１２表面から酸素が抜けるからでる。したがって、上述の分圧制御工程の「第１成膜工程後第２成膜工程前までの間」とは、第１成膜工程後第２成膜工程前までの間に一旦基板１０を大気中に取り出す場合も含むものとする。
また、本第１実施形態では、酸素欠損を有する酸化物について有効である場合を説明したが、過剰酸素を有する酸化物についても有効である。
Here, in an electronic device having a plurality of layer structures including the electronic device 20 shown in FIG. 3, when the uppermost layer of the layer structure contains an oxide having oxygen nonstoichiometry, the electronic device is in the atmosphere. The oxygen partial pressure in the atmosphere is about 2.0 × 10 4 Pa, which is very high compared to the oxygen partial pressure in the vacuum film formation chamber, and the uppermost layer is exposed to the atmosphere. Since oxygen enters the uppermost layer and oxygen vacancies in the uppermost layer can be compensated, the partial pressure control step as described above is not necessary.
However, even if the substrate 10 is once taken out into the atmosphere before the second film forming process after the first film forming process, the partial pressure control process as described above is necessary. This is because even if the surface of the first layer 12 formed on the substrate 10 is compensated for oxygen vacancies by taking it out into the atmosphere, the oxygen partial pressure is reduced when the substrate 10 is placed in the vacuum film formation chamber again. This is because oxygen is released from the surface of the first layer 12. Therefore, the term “between the first film formation process and before the second film formation process” in the above-described partial pressure control process means that the substrate 10 is temporarily placed in the atmosphere between the first film formation process and before the second film formation process. Including the case of taking out inside.
In the first embodiment, the case of being effective for an oxide having oxygen deficiency has been described. However, the case of being effective for an oxide having excess oxygen is also described.
また、第１成膜工程及び第２成膜工程は、以下のようなスパッタ装置により成膜することができる。 In addition, the first film formation step and the second film formation step can be formed by the following sputtering apparatus.
図４は、スパッタ装置の一部概略断面図を示す図である。
図４に示すように、スパッタ装置１００は、基板１０を保持すると共に基板１０を所定温度に加熱することができるヒーター１０２Ａを内部に備えた静電チャック等の基板ホルダ１０２と、プラズマを発生させるプラズマ電極（カソード電極）１０４と、基板ホルダ１０２とターゲットホルダであるプラズマ電極１０４との間に出入自在なシャッター１０６と、それらを内包する真空成膜室１０８から概略構成されている。なお、このプラズマ電極１０４は、ターゲットＴを保持するターゲットホルダに相当する。
FIG. 4 is a partial schematic cross-sectional view of the sputtering apparatus.
As shown in FIG. 4, the sputtering apparatus 100 generates a plasma with a substrate holder 102 such as an electrostatic chuck that includes a heater 102 </ b> A that holds the substrate 10 and can heat the substrate 10 to a predetermined temperature. A plasma electrode (cathode electrode) 104, a shutter 106 that can be freely inserted and removed between the substrate holder 102 and the plasma electrode 104 that is a target holder, and a vacuum film forming chamber 108 that contains them are generally constituted. The plasma electrode 104 corresponds to a target holder that holds the target T.
基板１０には、基板１０の電位を制御するための電源１１０が接続されている。
また、基板ホルダ１０２とプラズマ電極１０４とは互いに対向するように離間配置され、プラズマ電極１０４上に成膜する膜の組成に応じた組成のターゲットＴが装着されるようになっている。プラズマ電極１０４は高周波電源１１２に接続されている。
なお、プラズマ電極１０４と高周波電源１１２をプラズマ生成部という。また、図４では、基板ホルダ１０２とプラズマ電極１０４とは対向、すなわち基板ホルダ１０２の面とプラズマ電極１０４の面が平行して互いに向かい合っているが、基板ホルダ１０２の面とプラズマ電極１０４の面が平行ではなくある角度を持って向かい合っていても良い。
A power source 110 for controlling the potential of the substrate 10 is connected to the substrate 10.
Further, the substrate holder 102 and the plasma electrode 104 are spaced apart so as to face each other, and a target T having a composition corresponding to the composition of the film to be formed on the plasma electrode 104 is mounted. The plasma electrode 104 is connected to a high frequency power source 112.
The plasma electrode 104 and the high frequency power source 112 are referred to as a plasma generation unit. In FIG. 4, the substrate holder 102 and the plasma electrode 104 face each other, that is, the surface of the substrate holder 102 and the surface of the plasma electrode 104 face each other in parallel. May face each other with an angle rather than parallel.
真空成膜室１０８には、真空成膜室１０８内に成膜に必要なガス（成膜ガス）Ｇを導入するガス導入管１１４と、真空成膜室１０８内のガスの排気Ｖを行うガス排出管１１６とが取り付けられている。ガスＧとしては、Ａｒ／Ｏ２混合ガス等が使用される。また、真空成膜室１０８は接地されている。 In the vacuum film forming chamber 108, a gas introduction pipe 114 for introducing a gas (film forming gas) G necessary for film formation into the vacuum film forming chamber 108 and a gas for exhausting the gas V in the vacuum film forming chamber 108. A discharge pipe 116 is attached. As the gas G, Ar / O 2 mixed gas or the like is used. The vacuum film formation chamber 108 is grounded.
真空成膜室１０８の底面１０８Ａに、プラズマ電極１０４を囲むように立設されたアースシールドすなわち接地部材１１８が設けられている。この接地部材１１８は、プラズマ電極１０４から側方或いは下方に向けて真空成膜室１０８に放電しないようにするためのものである。 On the bottom surface 108 </ b> A of the vacuum film forming chamber 108, an earth shield, i.e., a ground member 118, is provided so as to surround the plasma electrode 104. The ground member 118 is for preventing discharge from the plasma electrode 104 to the vacuum film forming chamber 108 sideward or downward.
成膜時には、シャッター１０６をターゲット上から退避させた状態で、高周波電源１１２によりプラズマ電極１０４に高周波の交流電圧が印加され、真空成膜室１０８とプラズマ電極１０４とがそれぞれアノードとカソードとして作用して両者間に放電が生じ、真空成膜室１０８内に導入されたガスＧがプラズマ化され、Ａｒイオン等のプラスイオンＩｐが生成される。生成されたプラスイオンＩｐはターゲットＴをスパッタする。プラスイオンＩｐにスパッタされたターゲットＴの構成元素Ｔｐは、ターゲットから放出され中性あるいはイオン化された状態で基板１０に蒸着される。この蒸着を所定時間実施することで、所定厚の膜が成膜される。図中、符号Ｐがプラズマ空間を示している（ただし、成膜時には、シャッター１０６が退避されているため、シャッター１０６上部の空間もプラズマ空間である）。 At the time of film formation, a high frequency AC voltage is applied to the plasma electrode 104 by the high frequency power source 112 with the shutter 106 retracted from the target, and the vacuum film formation chamber 108 and the plasma electrode 104 function as an anode and a cathode, respectively. As a result, a discharge is generated between them, and the gas G introduced into the vacuum film forming chamber 108 is turned into plasma, and positive ions Ip such as Ar ions are generated. The generated positive ions Ip sputter the target T. The constituent element Tp of the target T sputtered by the positive ions Ip is emitted from the target and deposited on the substrate 10 in a neutral or ionized state. By performing this vapor deposition for a predetermined time, a film having a predetermined thickness is formed. In the drawing, a symbol P indicates a plasma space (however, since the shutter 106 is retracted during film formation, the space above the shutter 106 is also a plasma space).
そして、このようなスパッタ装置１００を用いて、上述の第１成膜工程及び第２成膜工程を同一の真空成膜室１０８内で行う場合には、第１成膜工程後第２成膜工程前までの間、分圧制御工程を行う他、シャッター１０６を移動し、このシャッター１０６を真空成膜室１０８内においてターゲットホルダと基板１０との間に配置する。 When the first film forming process and the second film forming process described above are performed in the same vacuum film forming chamber 108 using such a sputtering apparatus 100, the second film forming process is performed after the first film forming process. In addition to performing the partial pressure control process before the process, the shutter 106 is moved, and the shutter 106 is disposed between the target holder and the substrate 10 in the vacuum film forming chamber 108.
このような工程を、本発明の第１実施形態に係る電子デバイス２０の製造方法に追加することで、第１成膜工程後第２成膜工程前までの間、ターゲットホルダ上の空間にプラズマＰが発生していても、基板１０側に向かうプラズマＰはシャッター１０６によって遮断されるため、シャッター１０６上部にある基板１０に積層された第１層１２表面にプラズマダメージを与えることを防止することができる。また、成膜に使用したスパッタ装置１００はシャッター１０６を挿入することで、プラズマの電位を０Ｖにすることができ、加速電位の観点からもプラズマダメージが防止される。
この結果、プラズマダメージによる第１層１２と第２層１４との界面の欠陥をより低減することができる。
なお、シャッター１０６は、ターゲットホルダと基板１０との間に一個配置される場合を説明したが、カソード用のシャッターと、基板１０用のシャッターが別々にある場合には、より確実にプラズマダメージを防止するという観点から、その両方をターゲットホルダと基板１０との間に配置することが好ましい。
By adding such a process to the method for manufacturing the electronic device 20 according to the first embodiment of the present invention, plasma is generated in the space on the target holder after the first film formation process and before the second film formation process. Even if P is generated, the plasma P directed toward the substrate 10 is blocked by the shutter 106, so that it is possible to prevent plasma damage to the surface of the first layer 12 laminated on the substrate 10 above the shutter 106. Can do. Further, the sputtering apparatus 100 used for film formation can insert the shutter 106 to make the plasma potential 0 V, and plasma damage can be prevented from the viewpoint of acceleration potential.
As a result, defects at the interface between the first layer 12 and the second layer 14 due to plasma damage can be further reduced.
In addition, although the case where one shutter 106 is disposed between the target holder and the substrate 10 has been described, when the cathode shutter and the substrate 10 shutter are separately provided, plasma damage is more reliably performed. From the viewpoint of preventing both, it is preferable to dispose both of them between the target holder and the substrate 10.
（第２実施形態）
次に、第２実施形態では、図３に示す電子デバイス２０として薄膜トランジスタを一例に挙げて、電子デバイス２０についてより具体的に説明する。
(Second Embodiment)
Next, in the second embodiment, the electronic device 20 will be described more specifically by taking a thin film transistor as an example of the electronic device 20 shown in FIG.
本発明の第２実施形態に係る薄膜トランジスタは、少なくとも、ゲート電極、ゲート絶縁層、活性層、ソース電極及びドレイン電極を有し、ゲート電極に電圧を印加して、活性層に流れる電流を制御し、ソース電極とドレイン電極間の電流をスイッチングする機能を有するアクテイブ素子である。 The thin film transistor according to the second embodiment of the present invention includes at least a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, and controls a current flowing through the active layer by applying a voltage to the gate electrode. An active element having a function of switching a current between the source electrode and the drain electrode.
薄膜トランジスタの素子構造としては、ゲート電極の位置に基づいた、いわゆる逆スタガ構造（ボトムゲート型とも呼ばれる）及びスタガ構造（トップゲート型とも呼ばれる）のいずれの態様であってもよい。また、活性層とソース電極及びドレイン電極（適宜、「ソース・ドレイン電極」という。）との接触部分に基づき、いわゆるトップコンタクト型、ボトムコンタクト型のいずれの態様であってもよい。
なお、トップゲート型とは、ゲート絶縁層の上側にゲート電極が配置され、ゲート絶縁層の下側に活性層が形成された形態であり、ボトムゲート型とは、ゲート絶縁層の下側にゲート電極が配置され、ゲート絶縁層の上側に活性層が形成された形態である。また、ボトムコンタクト型とは、ソース・ドレイン電極が活性層よりも先に形成されて活性層の下面がソース・ドレイン電極に接触する形態であり、トップコンタクト型とは、活性層がソース・ドレイン電極よりも先に形成されて活性層の上面がソース・ドレイン電極に接触する形態である。
The element structure of the thin film transistor may be either a so-called inverted stagger structure (also referred to as a bottom gate type) or a stagger structure (also referred to as a top gate type) based on the position of the gate electrode. Further, based on the contact portion between the active layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be used.
The top gate type is a form in which a gate electrode is disposed on the upper side of the gate insulating layer and an active layer is formed on the lower side of the gate insulating layer. The bottom gate type is a type on the lower side of the gate insulating layer. The gate electrode is disposed and the active layer is formed on the gate insulating layer. The bottom contact type is a mode in which the source / drain electrodes are formed before the active layer and the lower surface of the active layer is in contact with the source / drain electrodes. The top contact type is the type in which the active layer is the source / drain. In this embodiment, the upper surface of the active layer is in contact with the source / drain electrodes.
図５は、本発明の第２実施形態に係る薄膜トランジスタであって、トップゲート構造で且つボトムコンタクト型の薄膜トランジスタの一例を示す模式図である。薄膜トランジスタ２００は、基板１０上にソース電極２０４及びドレイン電極２０６が互いに離間して設置され、更にこれらの上に活性層２０８を積層し、当該活性層２０８上にゲート絶縁層２１０と、ゲート電極２１２とを順に積層した構成である。 FIG. 5 is a schematic view showing an example of a thin film transistor of the top gate structure and bottom contact type according to the second embodiment of the present invention. In the thin film transistor 200, a source electrode 204 and a drain electrode 206 are spaced apart from each other on a substrate 10, an active layer 208 is further stacked thereon, a gate insulating layer 210, and a gate electrode 212 are formed on the active layer 208. Are sequentially stacked.
また、図６は、本発明の第２実施形態に係る薄膜トランジスタであって、トップゲート構造で且つトップコンタクト型の薄膜トランジスタの一例を示す模式図である。薄膜トランジスタ３００は、基板１０の表面上に活性層３０２を積層し、活性層３０２上にソース電極３０４及びドレイン電極３０６が互いに離間して設置され、更にこれらの上にゲート絶縁層３０８と、ゲート電極３１０とを順に積層した構成である。 FIG. 6 is a schematic view showing an example of a top contact type thin film transistor which is a thin film transistor according to the second embodiment of the present invention. In the thin film transistor 300, an active layer 302 is stacked on the surface of the substrate 10, and a source electrode 304 and a drain electrode 306 are spaced apart from each other on the active layer 302, and a gate insulating layer 308 and a gate electrode are further formed thereon. 310 in this order.
また、図７は、本発明の実施形態に係る薄膜トランジスタであって、ボトムゲート構造で且つトップコンタクト型の薄膜トランジスタの一例を示す模式図である。薄膜トランジスタ４００は、基板１０の上にゲート電極４０２と、ゲート絶縁層４０４と、活性層４０６とを順に積層して有し、活性層４０６の表面上にソース電極４０８及びドレイン電極４１０が互いに離間して設置された構成である。
なお、本発明の第２実施形態に係る薄膜トランジスタは、上記以外にも、様々な構成をとることが可能であり、適宜、活性層上に保護層や基板上に絶縁層等を備える構成であってもよい。
FIG. 7 is a schematic view showing an example of a top contact type thin film transistor having a bottom gate structure, which is a thin film transistor according to an embodiment of the present invention. The thin film transistor 400 includes a gate electrode 402, a gate insulating layer 404, and an active layer 406 stacked in order on the substrate 10, and the source electrode 408 and the drain electrode 410 are separated from each other on the surface of the active layer 406. It is a configuration installed.
In addition to the above, the thin film transistor according to the second embodiment of the present invention can have various configurations, and appropriately includes a protective layer on the active layer and an insulating layer on the substrate. May be.
次に、本発明の実施形態に係る薄膜トランジスタの製造方法について、図５に示すようなトップゲート構造で且つボトムコンタクト型の薄膜トランジスタ２００を例に挙げて説明する。
−基板の用意−
まず、薄膜トランジスタ２００を形成するための基板１０を用意する。
基板１０の形状、構造、大きさ等については特に制限はなく、目的に応じて適宜選択することが出来る。基板１０の構造は単層構造であってもよいし、積層構造であってもよい。
Next, a method for manufacturing a thin film transistor according to an embodiment of the present invention will be described using a top gate structure and bottom contact type thin film transistor 200 as shown in FIG. 5 as an example.
−Preparation of substrate−
First, the substrate 10 for forming the thin film transistor 200 is prepared.
There is no restriction | limiting in particular about the shape of the board | substrate 10, a structure, a magnitude | size, etc., It can select suitably according to the objective. The structure of the substrate 10 may be a single layer structure or a laminated structure.
基板１０の材質は特に限定はなく、例えばＹＳＺ(イットリウム安定化ジルコニウム)、ガラス等の無機基板や、可撓性を有する基板として、飽和ポリエステル／ポリエチレンテレフタレート（ＰＥＴ）系樹脂基板、ポリエチレンナフタレート（ＰＥＮ）樹脂基板、架橋フマル酸ジエステル系樹脂基板、ポリカーボネート（ＰＣ）系樹脂基板、ポリエーテルスルフォン（ＰＥＳ）樹脂基板、ポリスルフォン（ＰＳＦ,ＰＳＵ）樹脂基板、ポリアリレート（ＰＡＲ）樹脂基板、環状ポリオレフィン（ＣＯＰ,ＣＯＣ）樹脂基板、セルロース系樹脂基板、ポリイミド（ＰＩ）樹脂基板、ポリアミドイミド（ＰＡＩ）樹脂基板、マレイミド−オレフィン樹脂基板、ポリアミド（ＰＡ）樹脂基板、アクリル系樹脂基板、フッ素系樹脂基板、エポキシ系樹脂基板、シリコーン系樹脂フィルム基板、ポリベンズアゾール系樹脂基板、エピスルフィド化合物による基板、液晶ポリマー（ＬＣＰ）基板、シアネート系樹脂基板、芳香族エーテル系樹脂基板、酸化ケイ素粒子との複合プラスチック材料からなる基板、金属ナノ粒子、無機酸化物ナノ粒子、無機窒化物ナノ粒子などのナノ粒子との複合プラスチック材料からなる基板、金属系・無機系のナノファイバーおよびマイクロファイバーとの複合プラスチック材料からなる基板、カーボン繊維、カーボンナノチューブとの複合プラスチック材料からなる基板、ガラスフェレーク、ガラスファイバー、ガラスビーズとの複合プラスチック材料からなる基板、粘土鉱物や、雲母派生結晶構造を有する粒子との複合プラスチック材料からなる基板、薄いガラスと上記単独有機材料との間に少なくとも１回の接合界面を有する積層プラスチック材料からなる基板、無機層（例えば、ＳｉＯ２、Ａｌ２Ｏ３、ＳｉＯｘＮｙ）と有機層を交互に積層することで、少なくとも１回以上の接合界面を有するバリア性能を有する複合材料からなる基板、ステンレス基板、ステンレスと異種金属を積層した金属多層基板、アルミニウム基板、表面に酸化処理（例えば、陽極酸化処理）を施すことで、表面の絶縁性を向上してある酸化被膜付きのアルミニウム基板などが挙げられる。 The material of the substrate 10 is not particularly limited, and examples thereof include inorganic substrates such as YSZ (yttrium stabilized zirconium) and glass, and flexible substrates such as saturated polyester / polyethylene terephthalate (PET) resin substrates, polyethylene naphthalate ( PEN) resin substrate, crosslinked fumaric acid diester resin substrate, polycarbonate (PC) resin substrate, polyether sulfone (PES) resin substrate, polysulfone (PSF, PSU) resin substrate, polyarylate (PAR) resin substrate, cyclic polyolefin (COP, COC) resin substrate, cellulose resin substrate, polyimide (PI) resin substrate, polyamideimide (PAI) resin substrate, maleimide-olefin resin substrate, polyamide (PA) resin substrate, acrylic resin substrate, fluorine resin substrate , Epoxy resin group Board, silicone resin film substrate, polybenzazole resin substrate, substrate made of episulfide compound, liquid crystal polymer (LCP) substrate, cyanate resin substrate, aromatic ether resin substrate, substrate made of composite plastic material with silicon oxide particles , Substrates made of composite plastic materials with nanoparticles such as metal nanoparticles, inorganic oxide nanoparticles, inorganic nitride nanoparticles, substrates made of composite plastic materials with metal and inorganic nanofibers and microfibers, carbon Substrates made of composite plastic materials with fibers and carbon nanotubes, substrates made of composite plastic materials with glass ferkes, glass fibers and glass beads, substrates made of composite plastic materials with clay minerals and particles having a mica-derived crystal structure Thin glass Substrate made of laminated plastic material having a bonding interface at least once between the single organic material, inorganic layer (e.g., SiO 2, Al 2 O 3 , SiO x N y) and laminating an organic layer alternately Then, a substrate made of a composite material having a barrier performance having at least one bonding interface, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate, and an oxidation treatment (for example, anodization treatment) on the surface By applying, an aluminum substrate with an oxide film whose surface insulation is improved can be used.
また、本発明における基板の厚みは５０μｍ以上５００μｍ以下であることが好ましい。基板の厚みが５０μｍ以上であると、基板自体の平坦性がより向上する。又、基板の厚みが５００μｍ以下であると、基板自体の可撓性がより向上し、フレキシブルディスプレイ用基板としての使用がより容易となる。 Moreover, it is preferable that the thickness of the board | substrate in this invention is 50 micrometers or more and 500 micrometers or less. When the thickness of the substrate is 50 μm or more, the flatness of the substrate itself is further improved. Further, when the thickness of the substrate is 500 μm or less, the flexibility of the substrate itself is further improved, and the use as a substrate for a flexible display becomes easier.
−ソース・ドレイン電極の形成−
次に、基板１０上に、ソース・ドレイン電極２０４,２０６を形成する。
具体的には、ソース・ドレイン電極２０４,２０６となる導電膜を、例えば印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜する。前記導電膜の膜厚は成膜性、エッチングやリフトオフ法によるパターンニング性、導電性等を考慮すると、１０ｎｍ以上１０００ｎｍ以下とすることが好ましく、５０ｎｍ以上１００ｎｍ以下とすることがより好ましい。次いで前記導電膜をエッチング又はリフトオフ法により所定の形状にパターンニングし、ソース電極・ドレイン電極２０４,２０６を形成する。この際、ソース・ドレイン電極２０４,２０６及びこれらの電極２０４,２０６に接続する配線を同時にパターンニングすることが好ましい。
-Formation of source / drain electrodes-
Next, source / drain electrodes 204 and 206 are formed on the substrate 10.
Specifically, the conductive film to be the source / drain electrodes 204 and 206 is formed by, for example, a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, CVD, plasma CVD. The film is formed according to a method appropriately selected in consideration of suitability with the material to be used among chemical methods such as a method. The film thickness of the conductive film is preferably 10 nm or more and 1000 nm or less, and more preferably 50 nm or more and 100 nm or less in consideration of film formability, patterning property by etching or lift-off method, conductivity, and the like. Next, the conductive film is patterned into a predetermined shape by etching or lift-off method to form source / drain electrodes 204 and 206. At this time, it is preferable to pattern the source / drain electrodes 204 and 206 and the wiring connected to these electrodes 204 and 206 simultaneously.
ソース・ドレイン電極２０４,２０６は、高い導電性を有するものを用いる。例えばＡｌ,Ｍｏ,Ｃｒ,Ｔａ,Ｔｉ,Ａｕ,Ａｕなどの金属、Ａｌ−Ｎｄ,ＡＰＣ（(株)フルヤ金属製のＡｇ合金）、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫(ＩＴＯ)、酸化亜鉛インジウム(ＩＺＯ)等の金属酸化物導電膜等を用いて形成することが出来る。ソース・ドレイン電極２０４,２０６としてはこれらの導電膜を単層構造又は２層以上の積層構造として用いることが出来る。 The source / drain electrodes 204 and 206 have high conductivity. For example, metals such as Al, Mo, Cr, Ta, Ti, Au, Au, Al-Nd, APC (Ag alloy made by Furuya Metal Co., Ltd.), tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) Alternatively, a metal oxide conductive film such as zinc indium oxide (IZO) can be used. As the source / drain electrodes 204 and 206, these conductive films can be used as a single layer structure or a laminated structure of two or more layers.
−活性層の形成（第１成膜工程）−
次に、大気と遮断された真空成膜室内で、基板１０上及びソース・ドレイン電極２０４,２０６上に、酸素不定比性のある酸化物を含有する第１層１２としての活性層２０８を形成する。
具体的には、まず活性層２０８となる酸化物半導体膜を成膜する第１成膜工程を行う。この第１成膜工程では、例えば印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜する。次いで前記酸化物半導体膜をエッチング又はリフトオフ法により所定の形状にパターンニングし、活性層２０８を形成する。
-Formation of active layer (first film formation step)-
Next, the active layer 208 as the first layer 12 containing an oxide having oxygen non-stoichiometry is formed on the substrate 10 and the source / drain electrodes 204 and 206 in a vacuum film formation chamber that is cut off from the atmosphere. To do.
Specifically, first, a first film formation step for forming an oxide semiconductor film to be the active layer 208 is performed. In this first film forming step, for example, a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as a CVD method or a plasma CVD method is used. The film is formed according to a method appropriately selected in consideration of suitability with the material to be used. Next, the oxide semiconductor film is patterned into a predetermined shape by etching or a lift-off method to form an active layer 208.
活性層２０８の厚みは、５ｎｍ以上２００ｎｍ以下程度が好ましい。これは、５ｎｍ以下では、均一性の良好な膜が得られない可能性があるためである。
活性層２０８の構成材料は、上述した第１層１２が半導体である場合の材料を適宜選択できる。
The thickness of the active layer 208 is preferably about 5 nm to 200 nm. This is because a film with good uniformity may not be obtained at 5 nm or less.
As a constituent material of the active layer 208, a material in the case where the first layer 12 described above is a semiconductor can be appropriately selected.
−分圧制御工程−
次に、第１成膜工程後、後述する第２層１４としてのゲート絶縁層２１０を成膜する第２成膜工程前までの間は、真空成膜室を含む大気と遮断された室内で、第１層１２としての活性層２０８を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する分圧制御工程を行う。
なお、この分圧制御工程は、上述の酸化物半導体膜のパターニングの間も行われることが好ましい。
-Partial pressure control process-
Next, after the first film formation step and before the second film formation step for forming a gate insulating layer 210 as a second layer 14 to be described later, it is in a room cut off from the atmosphere including the vacuum film formation chamber. Then, a partial pressure control step is performed in which the active layer 208 as the first layer 12 is held under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation step.
Note that this partial pressure control step is preferably performed also during the above-described patterning of the oxide semiconductor film.
−ゲート絶縁層の形成（第２成膜工程）−
次に、活性層２０８上に、第２層１４としてのゲート絶縁層２１０を形成する。
具体的には、まずゲート絶縁層２１０となる絶縁膜を成膜する第２成膜工程を行う。この第２成膜工程では、印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜する。成膜した前記絶縁膜はフォトリソグラフィー及びエッチングによって所定の形状にパターンニングし、ゲート絶縁層２１０を形成する。
-Formation of gate insulating layer (second film formation step)-
Next, the gate insulating layer 210 as the second layer 14 is formed on the active layer 208.
Specifically, first, a second film formation step for forming an insulating film to be the gate insulating layer 210 is performed. In this second film forming process, a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as CVD or plasma CVD method is used. The film is formed according to a method appropriately selected in consideration of suitability for the material to be used. The formed insulating film is patterned into a predetermined shape by photolithography and etching to form a gate insulating layer 210.
なお、ゲート絶縁層２１０は、リーク電流の低下及び電圧耐性の向上のための厚みを有する必要がある一方、ゲート絶縁層２１０の厚みが大きすぎると駆動電圧の上昇を招いてしまう。ゲート絶縁層２１０の厚みは材質にもよるが、１０ｎｍ以上１０μｍ以下が好ましく、５０ｎｍ以上１０００ｎｍ以下がより好ましく、１００ｎｍ以上４００ｎｍ以下が特に好ましい。また、ゲート絶縁層２１０としては成膜した膜を単層構造又は２層以上の積層構造として用いることが出来る。
ゲート絶縁層２１０は、高い絶縁性を有するものが好ましい。例えばＳｉＮｘ、ＩｎＧａＺｎＯ４−δ（δ≧０）、ＳｉＯＮ、ＳｉＯ２、Ａｌ２Ｏ３、Ｙ２Ｏ３、ＭｇＯ、ＴｉＯ２、ＧｅＯ２、Ｔａ２Ｏ５、ＨｆＯ２、Ｓｃ２Ｏ３、Ｇａ２Ｏ３、ＺｒＯ２、Ｌｎ２Ｏ３(ランタノイドの酸化物)等の絶縁膜又はこれらの化合物を少なくとも二つ以上含む絶縁膜としてもよい。
Note that the gate insulating layer 210 needs to have a thickness for reducing leakage current and improving voltage resistance. On the other hand, if the thickness of the gate insulating layer 210 is too large, driving voltage is increased. Although depending on the material, the thickness of the gate insulating layer 210 is preferably 10 nm or more and 10 μm or less, more preferably 50 nm or more and 1000 nm or less, and particularly preferably 100 nm or more and 400 nm or less. As the gate insulating layer 210, a deposited film can be used as a single layer structure or a stacked structure of two or more layers.
The gate insulating layer 210 preferably has high insulating properties. For example, SiN x , InGaZnO 4-δ (δ ≧ 0), SiON, SiO 2 , Al 2 O 3 , Y 2 O 3 , MgO, TiO 2 , GeO 2 , Ta 2 O 5 , HfO 2 , Sc 2 O 3 , An insulating film such as Ga 2 O 3 , ZrO 2 , Ln 2 O 3 (lanthanoid oxide) or an insulating film containing at least two of these compounds may be used.
−ゲート電極の形成−
次に、ゲート絶縁層２１０上にゲート電極２１２を形成する。
具体的には、ゲート電極２１２となる導電膜を、例えば印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、ＣＶＤ、プラズマＣＶＤ法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜する。前記導電膜の膜厚は成膜性、エッチングやリフトオフ法によるパターンニング性、導電性等を考慮すると、１０ｎｍ以上１０００ｎｍ以下とすることが好ましく、５０ｎｍ以上２００ｎｍ以下とすることがより好ましい。成膜後は、エッチング又はリフトオフ法により所定の形状にパターンニングし、ゲート電極２１２を形成する。この際、ゲート電極２１２及びゲート配線を同時にパターンニングすることが好ましい。
-Formation of gate electrode-
Next, the gate electrode 212 is formed over the gate insulating layer 210.
Specifically, the conductive film to be the gate electrode 212 is formed by, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film is formed according to a method appropriately selected in consideration of suitability with the material to be used from among other methods. The film thickness of the conductive film is preferably 10 nm or more and 1000 nm or less, and more preferably 50 nm or more and 200 nm or less in consideration of film forming properties, patterning properties by etching or lift-off methods, conductivity, and the like. After the film formation, the gate electrode 212 is formed by patterning into a predetermined shape by etching or a lift-off method. At this time, it is preferable to pattern the gate electrode 212 and the gate wiring at the same time.
ゲート電極２１２は、高い導電性を有するものが好ましい。例えばＡｌ,Ｍｏ,Ｃｒ,Ｔａ,Ｔｉ,Ａｕなどの金属、Ａｌ−Ｎｄ,ＡＰＣ((株)フルヤ金属製のＡｇ合金）、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫(ＩＴＯ)、酸化亜鉛インジウム(ＩＺＯ)等の金属酸化物導電膜等を用いる。ゲート電極２１２としてはこれらの導電膜を単層構造又は２層以上の積層構造として用いることもできる。 The gate electrode 212 preferably has high conductivity. For example, metals such as Al, Mo, Cr, Ta, Ti, Au, Al-Nd, APC (Ag alloy made by Furuya Metal Co., Ltd.), tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), oxidation A metal oxide conductive film such as zinc indium (IZO) is used. As the gate electrode 212, these conductive films can be used as a single-layer structure or a stacked structure of two or more layers.
−効果−
ここで、第１層１２が酸化物半導体からなる活性層２０８である場合には、上記[背景技術]の欄で示したものの他（閾値シフトの発生）、第１層１２の酸素欠損によって比抵抗、キャリア濃度、キャリア移動度が大きく変化することが知られている(A. Takagi, et al., Thin Solid Films, 486 (2005) 38, H. Hosono, J. Non-cryst Solid, 352 (2006) 851参照）。これは、酸素欠陥によって生じるキャリアが酸化物の伝導機構に支配的であるためである。
-Effect-
Here, when the first layer 12 is the active layer 208 made of an oxide semiconductor, in addition to what is shown in the above [Background Art] column (occurrence of a threshold shift), the ratio of the first layer 12 depends on the oxygen deficiency of the first layer 12. It is known that resistance, carrier concentration, and carrier mobility change greatly (A. Takagi, et al., Thin Solid Films, 486 (2005) 38, H. Hosono, J. Non-cryst Solid, 352 ( 2006) 851). This is because carriers generated by oxygen defects are dominant in the conduction mechanism of the oxide.
そのため、一般的に活性層２０８となる酸化物半導体膜を成膜する際には、成膜時の酸素分圧を制御し、膜中の酸素欠損を制御することで、酸化物半導体膜の電気伝導特性を制御する手法が用いられる。しかしながら、酸化物半導体膜成膜後の真空成膜室内の酸素分圧を制御する手法に関してはこれまで検討されていなかった。 Therefore, in general, when an oxide semiconductor film serving as the active layer 208 is formed, the oxygen partial pressure during film formation is controlled, and oxygen vacancies in the film are controlled. A technique for controlling the conduction characteristics is used. However, a method for controlling the oxygen partial pressure in the vacuum film formation chamber after forming the oxide semiconductor film has not been studied so far.
本発明の第２実施形態に係る電子デバイスの製造方法は、真空成膜室内において酸化物半導体膜の成膜を行い、その後該真空成膜室内の酸素分圧を制御することで、酸化物半導体膜表面の酸素欠損を制御する技術であり、それに伴って該酸化物半導体膜の比抵抗、キャリア濃度を制御することが可能である。
具体的には、第１成膜工程後第２成膜工程前までの間、真空成膜室を含む大気と遮断された室内で、第１層１２としての活性層２０８を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する分圧制御工程を行うことで、活性層２０８表面の酸素欠損の増大を抑制することが可能である。また、活性層２０８表面に生じる余剰キャリアの発生を抑制することが可能である。そして、分圧制御工程後は、ゲート絶縁層２１０となる絶縁膜を成膜すれば、活性層２０８表面の酸素欠損の増大が低減された状態が維持（酸素含有量が固定）された積層膜が得られる。このように作製した積層膜を備える薄膜トランジスタ２００は、活性層２０８とゲート絶縁層２１０界面の欠陥準位の増大が抑制されているため、閾値シフト等のデバイス劣化が極めて少ない。また、活性層２０８表面からの余剰キャリアの発生を抑制しているために、ノーマリーオフの薄膜トランジスタを作製することが容易になる。ノーマリーオフの薄膜トランジスタとは、試料に印加するゲート電圧が０Ｖの時にオフと成るようなスイッチング素子のことを指し、ノーマリーオンのトランジスタに比べ低消費電力であり、より需要が高い。
In the method for manufacturing an electronic device according to the second embodiment of the present invention, an oxide semiconductor film is formed in a vacuum film formation chamber, and then an oxygen partial pressure in the vacuum film formation chamber is controlled. This is a technique for controlling oxygen vacancies on the film surface, and accordingly, the specific resistance and carrier concentration of the oxide semiconductor film can be controlled.
Specifically, the active layer 208 as the first layer 12 is formed in the first film formation in a room cut off from the atmosphere including the vacuum film formation chamber after the first film formation process and before the second film formation process. By performing the partial pressure control step of maintaining the oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the step, it is possible to suppress an increase in oxygen vacancies on the surface of the active layer 208. In addition, it is possible to suppress the generation of excess carriers generated on the surface of the active layer 208. After the partial pressure control step, if an insulating film to be the gate insulating layer 210 is formed, a laminated film in which the increase in oxygen vacancies on the surface of the active layer 208 is maintained (the oxygen content is fixed). Is obtained. In the thin film transistor 200 including the stacked film manufactured as described above, an increase in the defect level at the interface between the active layer 208 and the gate insulating layer 210 is suppressed, so that device deterioration such as threshold shift is extremely small. In addition, since generation of excess carriers from the surface of the active layer 208 is suppressed, it is easy to manufacture a normally-off thin film transistor. A normally-off thin film transistor refers to a switching element that is turned off when a gate voltage applied to a sample is 0 V, and has lower power consumption than a normally-on transistor, and is in high demand.
−薄膜トランジスタの変形例−
本発明の第２実施形態に係る電子デバイスの製造方法は、異なる電気特性を持つ複数の酸化物半導体膜の積層から成る活性層を有する薄膜トランジスタ(特開２００７−７３７０１参照)において、当該複数の積層膜を成膜する場合にも有効である。この場合、第１層１２及び第２層１４共に酸化物半導体膜となる。
具体的には、真空成膜室内において基板上に酸化物半導体膜の成膜する第１成膜工程を行い、第１成膜工程後の該真空成膜室内における酸素分圧を該酸化物半導体膜の成膜時よりも高めた状態にした後（第１層１２としての活性層２０８を、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する）、再び異なる電気特性を示す酸化物半導体膜を成膜すれば、酸化物半導体膜と酸化物半導体膜の界面における酸素欠損の低減が可能である。このような酸化物半導体膜の積層膜を活性層に有する薄膜トランジスタは、本発明の第２実施形態に係る電子デバイスの製造方法を用いずに順次成膜した酸化物半導体膜の積層膜を活性層に有する薄膜トランジスタと比較して、閾値シフト等のデバイス劣化因子及び余剰キャリアの発生を低減し、安定性が高くなる。
-Modification of thin film transistor-
A method for manufacturing an electronic device according to a second embodiment of the present invention includes a thin film transistor (see Japanese Patent Application Laid-Open No. 2007-73701) having an active layer formed of a stack of a plurality of oxide semiconductor films having different electrical characteristics. This is also effective when forming a film. In this case, both the first layer 12 and the second layer 14 are oxide semiconductor films.
Specifically, a first film formation step of forming an oxide semiconductor film over a substrate is performed in a vacuum film formation chamber, and an oxygen partial pressure in the vacuum film formation chamber after the first film formation step is changed to the oxide semiconductor. After making the state higher than that at the time of film formation (the active layer 208 as the first layer 12 is maintained under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation step) When an oxide semiconductor film having different electrical characteristics is formed again, oxygen vacancies at the interface between the oxide semiconductor film and the oxide semiconductor film can be reduced. A thin film transistor having such a stacked film of oxide semiconductor films as an active layer is obtained by sequentially forming the stacked film of oxide semiconductor films without using the electronic device manufacturing method according to the second embodiment of the present invention. Compared with the thin film transistor included in the device, the device deterioration factors such as threshold shift and the generation of surplus carriers are reduced, and the stability is improved.
また、本発明の第２実施形態に係る電子デバイスの製造方法は、酸化物絶縁体膜の成膜に対しても有効である。例えば、図７に示すようなボトムゲート構造の薄膜トランジスタ４００では、基板１０上にゲート電極４０２を有する構造体の上に酸化物絶縁体膜からなるゲート絶縁層４０４と活性層４０６を順次成膜する場合がある。そして、このような構成の場合、ゲート絶縁層４０４を構成する酸化物絶縁体膜の酸素欠損が増大することによって、ゲートリーク電流が増大するなど、絶縁特性が酸素欠損によって変化することが知られている(K. Shiraishi, et al., Thin Solid Films 508 (2006) 305-310参照)。
そこで、本発明の第２実施形態に係る電子デバイスの製造方法である、該構造体上に、第１層１２としてのゲート絶縁層４０４となる酸化物絶縁体膜を成膜する第１成膜工程を行った後、第２層１４としての活性層４０６となる半導体膜を成膜する第２成膜工程までの間、ゲート絶縁層４０４を、真空成膜室を含む大気と遮断された室内で、第１成膜工程における真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する分圧制御工程を行うことで、ゲート絶縁層４０４表面の酸素欠損を低減でき、その後活性層４０６を構成する半導体膜を成膜することにより、ゲート絶縁層４０４と活性層４０６の界面の欠陥準位を低減でき、絶縁耐性が高く、良好な安定性を示す薄膜トランジスタの提供が可能になる。
なお、このような酸化物絶縁体膜からなるゲート絶縁層４０４は、ＩｎＧａＺｎＯ４−δ（δ≧０）、ＳｉＯＮ、ＳｉＯ２、Ａｌ２Ｏ３、Ｙ２Ｏ３、ＭｇＯ、ＴｉＯ２、ＧｅＯ２、Ｔａ２Ｏ５、ＨｆＯ２、Ｓｃ２Ｏ３、Ｇａ２Ｏ３、ＺｒＯ２、Ｌｎ２Ｏ３(ランタノイドの酸化物)等の絶縁膜又はこれらの化合物を少なくとも二つ以上含む絶縁膜としてもよい。また、この場合、活性層４０６は、酸化物である必要はなく、例えばアモルファスシリコン、低温多結晶シリコン等のIV族系半導体や、ＧａＡｓ,ＧａＮ,ＩｎＰ,ＳｉＣなどの化合物半導体、ダイヤモンド等のカーボン系半導体、金属酸化物半導体又はペンタセン等の有機半導体等の半導体材料を用いることができる。
In addition, the method for manufacturing an electronic device according to the second embodiment of the present invention is also effective for forming an oxide insulator film. For example, in a bottom-gate thin film transistor 400 as shown in FIG. 7, a gate insulating layer 404 and an active layer 406 made of an oxide insulating film are sequentially formed on a structure having a gate electrode 402 on a substrate 10. There is a case. In such a structure, it is known that the insulating characteristics change due to oxygen vacancies, such as an increase in gate leakage current due to an increase in oxygen vacancies in the oxide insulator film constituting the gate insulating layer 404. (See K. Shiraishi, et al., Thin Solid Films 508 (2006) 305-310).
Therefore, in the method for manufacturing an electronic device according to the second embodiment of the present invention, a first film formation is performed in which an oxide insulator film serving as the gate insulating layer 404 as the first layer 12 is formed on the structure. After the process is performed, the gate insulating layer 404 is separated from the atmosphere including the vacuum film formation chamber until the second film formation process for forming the semiconductor film to be the active layer 406 as the second layer 14. Thus, by performing a partial pressure control step of maintaining the oxygen partial pressure higher than the oxygen partial pressure in the vacuum film formation chamber in the first film formation step, oxygen vacancies on the surface of the gate insulating layer 404 can be reduced, and then the active layer 406 By forming the semiconductor film forming the structure, it is possible to reduce the defect level at the interface between the gate insulating layer 404 and the active layer 406, to provide a thin film transistor having high insulation resistance and good stability.
Note that the gate insulating layer 404 formed of such an oxide insulator film includes InGaZnO 4-δ (δ ≧ 0), SiON, SiO 2 , Al 2 O 3 , Y 2 O 3 , MgO, TiO 2 , and GeO 2. An insulating film such as Ta 2 O 5 , HfO 2 , Sc 2 O 3 , Ga 2 O 3 , ZrO 2 , Ln 2 O 3 (lanthanoid oxide) or an insulating film containing at least two of these compounds Good. In this case, the active layer 406 does not need to be an oxide. For example, a group IV semiconductor such as amorphous silicon or low-temperature polycrystalline silicon, a compound semiconductor such as GaAs, GaN, InP, or SiC, or a carbon such as diamond. Semiconductor materials such as organic semiconductors, metal oxide semiconductors, or organic semiconductors such as pentacene can be used.
なお、本発明の第２実施形態に係る電子デバイスが、図６に示すようなトップコンタクト型の薄膜トランジスタ３００であり、活性層３０２を第１層１２とし、ゲート絶縁層３０８を形成する前に、活性層３０２上にソース・ドレイン電極３０４,３０６を形成する場合、活性層３０２を形成した後ソース・ドレイン電極３０４,３０６を形成する前までの間だけでなく、ソース・ドレイン電極３０４,３０６を形成した後ゲート絶縁層３０８を形成する前までの間も、活性層３０２の一部が露出する。従って、このような場合には、上述の分圧制御工程をそれぞれの非成膜時（成膜中断時）において行うことが好ましい。図７のトップコンタクト型の薄膜トランジスタ３００の場合も同様である。ただし、トップコンタクト型の薄膜トランジスタの場合でも、活性層３０２上にゲート絶縁層３０８を先に形成し、後にコンタクトホールを開けてソース・ドレイン電極３０４,３０６を形成するような場合にはこの限りでない（１回の分圧制御工程だけでも良い）。 Note that the electronic device according to the second embodiment of the present invention is a top contact type thin film transistor 300 as shown in FIG. 6, wherein the active layer 302 is the first layer 12 and the gate insulating layer 308 is formed before the gate insulating layer 308 is formed. When the source / drain electrodes 304 and 306 are formed on the active layer 302, the source / drain electrodes 304 and 306 are not only formed after the active layer 302 is formed but before the source / drain electrodes 304 and 306 are formed. Part of the active layer 302 is exposed even after the formation and before the gate insulating layer 308 is formed. Therefore, in such a case, it is preferable to perform the partial pressure control process described above at the time of non-film formation (when film formation is interrupted). The same applies to the top contact type thin film transistor 300 of FIG. However, even in the case of a top contact type thin film transistor, this is not the case when the gate insulating layer 308 is formed on the active layer 302 first, and then the contact holes are opened to form the source / drain electrodes 304 and 306. (Only one partial pressure control step may be used).
また、本発明の第２実施形態に係る電子デバイスは、薄膜トランジスタである場合を説明したが、本発明の第２実施形態に係る電子デバイスの製造方法はトンネル接合素子をはじめとする酸化物絶縁体層と電極層からなる電子デバイスにも有効である。本発明の第２実施形態に係る電子デバイスの製造方法を用いることによって、磁気抵抗比の向上、リーク電流の減少、及びそれに付随するノイズの低減が期待できるからである。 In addition, although the electronic device according to the second embodiment of the present invention has been described as a thin film transistor, the method for manufacturing the electronic device according to the second embodiment of the present invention includes an oxide insulator including a tunnel junction element. It is also effective for an electronic device comprising a layer and an electrode layer. This is because the use of the electronic device manufacturing method according to the second embodiment of the present invention can be expected to improve the magnetoresistance ratio, reduce the leakage current, and reduce the noise accompanying it.
以下に、本発明に係る電子デバイスの製造方法、薄膜トランジスタ、電気光学装置及びセンサーについて、実施例により説明するが、本発明はこれら実施例により何ら限定されるものではない。 Hereinafter, the electronic device manufacturing method, the thin film transistor, the electro-optical device, and the sensor according to the present invention will be described with reference to examples, but the present invention is not limited to these examples.
図８（Ａ）は、本発明の実施例に係る電子デバイスの一例としてのホール素子を示す模式図である。図８（Ｂ）は、図８（Ａ）のホール素子の比較例を示す模式図である。
図８（Ａ）に示すように、本実施例では、上述した電子デバイスの製造方法を用い、単一の真空成膜室内で基板５０２上に、以下の表１のような成膜条件でＩｎ,Ｇａ,Ｚｎ及びＯから成る第１層５０４、第２層５０６及び第３層５０８（複合酸化物半導体(ＩＧＺＯ)の積層膜５１０）を順次形成し、これら積層膜５１０に電気特性評価のため４端子電極を蒸着法によって接合したホール素子５００を６通り作製した。基板５０２としては、合成石英ガラス基板(コバレントマテリアル社製、品番Ｔ−４０４０)を用いた。
FIG. 8A is a schematic diagram showing a Hall element as an example of an electronic device according to an embodiment of the present invention. FIG. 8B is a schematic diagram illustrating a comparative example of the Hall element of FIG.
As shown in FIG. 8A, in this embodiment, the above-described electronic device manufacturing method is used to form In on a substrate 502 in a single vacuum film formation chamber under the film formation conditions shown in Table 1 below. , Ga, Zn, and O, a first layer 504, a second layer 506, and a third layer 508 (stacked film 510 of a composite oxide semiconductor (IGZO)) are sequentially formed, and the stacked film 510 is evaluated for electrical characteristics. Six types of Hall elements 500 in which four-terminal electrodes were joined by vapor deposition were produced. As the substrate 502, a synthetic quartz glass substrate (manufactured by Covalent Materials, product number T-4040) was used.
図９は、本発明の実施例に係る電子デバイスの製造方法における各工程中の基板５０２周囲の酸素分圧の状態を示した図である。
図９に示すように、これら６通りのホール素子５００は、ＩＧＺＯ積層膜５１０を形成するにあたって、第１層５０４の成膜工程後第２層５０６の成膜工程までの間、及び第２層５０６の成膜工程後第３層５０８の成膜工程までの間、１分間真空成膜室内の酸素分圧を、以下の１．０×１０−７Ｐａ〜２.８×１０−２Ｐａの間のある酸素分圧に制御してそれぞれ実施例１〜３又は比較例１〜３の素子として作製している。
表２に、各実施例及び比較例の素子における、非成膜時（第１層５０４の成膜工程後第２層５０６の成膜工程までの間、及び第２層５０６の成膜工程後第３層５０８の成膜工程までの間）の制御した酸素分圧の値を示す。なお、表２では、この非成膜時の酸素分圧と、第１層５０４及び第２層５０６の成膜時の酸素分圧との対比の欄も設けている。
FIG. 9 is a diagram showing a state of oxygen partial pressure around the substrate 502 during each step in the method of manufacturing an electronic device according to the example of the present invention.
As shown in FIG. 9, when forming the IGZO laminated film 510, these six Hall elements 500 are formed between the first layer 504 and the second layer 506, and the second layer. The oxygen partial pressure in the vacuum film formation chamber is set to the following 1.0 × 10 −7 Pa to 2.8 × 10 −2 Pa for 1 minute after the film formation step 506 until the film formation step of the third layer 508. The device is manufactured as an element of Examples 1 to 3 or Comparative Examples 1 to 3 by controlling the oxygen partial pressure in between.
Table 2 shows the non-film formation time (after the film formation process of the first layer 504 to the film formation process of the second layer 506 and after the film formation process of the second layer 506) in the elements of the examples and comparative examples. The value of the oxygen partial pressure controlled until the film formation step of the third layer 508 is shown. In Table 2, a column for comparing the oxygen partial pressure during non-film formation with the oxygen partial pressure during film formation of the first layer 504 and the second layer 506 is also provided.
また、比較として、図８（Ｂ）に示すように、上述のような非成膜時に分圧制御を用いず、第１層５０４,第２層５０６,第３層５０８と全く同じ条件下でＩＧＺＯ単独膜６０２を、基板５０２上に７０ｎｍ成膜して、ホール素子６００を作製した。異なるのは成膜を途切れさせることなく連続で成膜を行ったという点である。 For comparison, as shown in FIG. 8B, the partial pressure control is not used when the film is not formed as described above, under exactly the same conditions as the first layer 504, the second layer 506, and the third layer 508. An IGZO single film 602 was formed to a thickness of 70 nm on the substrate 502 to produce the Hall element 600. The difference is that the film formation was performed continuously without interruption.
そして、各ホール素子５００,６００について、ホール測定装置(東陽テクニカ社製)を用い、van der pauw法によって、比抵抗、キャリア濃度及びホール移動度を評価した。 For each of the Hall elements 500 and 600, the specific resistance, carrier concentration, and Hall mobility were evaluated by a van der pauw method using a Hall measuring device (manufactured by Toyo Corporation).
図１０は、非成膜時の真空成膜室内の酸素分圧を変化させて成膜したＩＧＺＯ積層膜５１０の比抵抗値を、横軸を酸素分圧にとりプロットしたものである。なお、ＩＧＺＯ単独膜６０２の比抵抗値は、約１．３×１０Ω・ｃｍであった。 FIG. 10 is a plot of the specific resistance value of the IGZO laminated film 510 formed by changing the oxygen partial pressure in the vacuum film formation chamber during non-film formation, with the horizontal axis representing the oxygen partial pressure. The specific resistance value of the IGZO single film 602 was about 1.3 × 10 Ω · cm.
酸素分圧を４.４×１０−３Ｐａ以下にした比較例１,２,３についてはＩＧＺＯ単独膜６０２と比較して比抵抗が一桁以上低下していることがわかる。この結果から、二層以上の膜を成膜中断を挟んで成膜する際、成膜中断時（非成膜時）の酸素分圧によってＩＧＺＯ膜界面の酸素欠損が変化することが明らかとなった。特に成膜中断時の酸素分圧を、成膜時の酸素分圧と同じにした場合にも低抵抗化が起こることから、成膜中断時の酸素分圧を一切制御しなかった場合（成膜時の酸素分圧をそのまま保持した場合）には、膜の低抵抗化が起こり所望の電気特性が得られないことを意味している。 It can be seen that in Comparative Examples 1, 2, and 3 in which the oxygen partial pressure was 4.4 × 10 −3 Pa or less, the specific resistance decreased by one digit or more as compared with the IGZO single film 602. From these results, it is clear that when two or more layers are formed with the interruption of film formation, oxygen vacancies at the interface of the IGZO film change depending on the oxygen partial pressure at the time of film formation interruption (non-film formation). It was. In particular, when the oxygen partial pressure at the time of film formation interruption is the same as the oxygen partial pressure at the time of film formation, the resistance is lowered. In the case where the oxygen partial pressure at the time of film is kept as it is, this means that the resistance of the film is lowered and desired electrical characteristics cannot be obtained.
一方で、成膜中断時の真空成膜室における酸素分圧を４.４×１０−３Ｐａ超にした実施例１,２,３についてはＩＧＺＯ単独膜６０２と同等の比抵抗を示した。このことから成膜中断時に起こる、ＩＧＺＯ膜表面の酸素欠損の増加は、成膜中断時の酸素分圧を、成膜時よりも高めることで抑制させることが可能であることが明らかとなった。
なお、ＩＧＺＯ単独膜６０２の比抵抗値が、約１．３×１０Ω・ｃｍであったことから、ＩＧＺＯ積層膜５１０の比抵抗値が、ＩＧＺＯ単独膜６０２の比抵抗値により近い値の範囲の例えば１．３Ω・ｃｍ以上１．３×１０３Ω・ｃｍ以下の範囲内（図中のエラーバー）にあることが好ましく、この比抵抗値の下限値に対応する酸素分圧は、４.４×１０−３Ｐａよりも多少高い４.７×１０−３Ｐａとなる（図中○印）。また、確実性の観点から、実施例１の非成膜時の酸素分圧から成膜時の酸素分圧４.４×１０−３Ｐａを差引いた２．１×１０−３Ｐａ以上、非成膜時の酸素分圧を成膜時より高くすることが好ましい。
On the other hand, Examples 1, 2, and 3 in which the oxygen partial pressure in the vacuum film formation chamber at the time of film formation interruption was over 4.4 × 10 −3 Pa showed a specific resistance equivalent to that of the IGZO single film 602. From this, it became clear that the increase in oxygen vacancies on the surface of the IGZO film that occurs when the film formation is interrupted can be suppressed by increasing the oxygen partial pressure during the film formation interruption more than during film formation. .
In addition, since the specific resistance value of the IGZO single film 602 was about 1.3 × 10 Ω · cm, the specific resistance value of the IGZO laminated film 510 is in a range close to the specific resistance value of the IGZO single film 602. For example, it is preferably in the range of 1.3 Ω · cm to 1.3 × 10 3 Ω · cm (error bar in the figure), and the oxygen partial pressure corresponding to the lower limit value of the specific resistance value is 4. It becomes 4.7 × 10 −3 Pa which is slightly higher than 4 × 10 −3 Pa (circle mark in the figure). Further, from the viewpoint of certainty, 2.1 × 10 −3 Pa or more, which is obtained by subtracting the oxygen partial pressure 4.4 × 10 −3 Pa during film formation from the oxygen partial pressure during non-film formation in Example 1, It is preferable that the oxygen partial pressure during film formation is higher than that during film formation.
図１１は、非成膜時の真空成膜室内の酸素分圧を変えて成膜したＩＧＺＯ積層膜５１０のキャリア濃度について、横軸を酸素分圧にしてプロットしたものである。なお、ＩＧＺＯ単独膜６０２のキャリア濃度は、約４．２×１０１６ｃｍ−３であった。 FIG. 11 is a plot of the carrier concentration of the IGZO laminated film 510 formed by changing the oxygen partial pressure in the vacuum film formation chamber during non-film formation, with the horizontal axis representing the oxygen partial pressure. The carrier concentration of the IGZO single film 602 was about 4.2 × 10 16 cm −3 .
非成膜時の真空成膜室内の酸素分圧を４.４×１０−３Ｐａ超にすることで、キャリア濃度はほぼ一定値をとっている様子がわかる(実施例１,２,３)。この酸素分圧４.４×１０−３Ｐａ超の領域におけるキャリア濃度は、連続成膜にて得られたＩＧＺＯ単独膜６０２のキャリア濃度とほぼ同等の値である。従ってこのことは、非成膜時の酸素分圧を成膜時よりも高めることで、ＩＧＺＯ膜界面の酸素欠損がＩＧＺＯ単独膜６０２の膜中と同程度になり、酸素欠損増大による余剰キャリアの発生を抑制していることを意味している。 It can be seen that the carrier concentration is almost constant by setting the oxygen partial pressure in the vacuum film formation chamber at non-film formation to over 4.4 × 10 −3 Pa (Examples 1, 2, and 3). . The carrier concentration in the region where the oxygen partial pressure exceeds 4.4 × 10 −3 Pa is substantially equal to the carrier concentration of the IGZO single film 602 obtained by continuous film formation. Therefore, by increasing the oxygen partial pressure at the time of non-film formation as compared with that at the time of film formation, oxygen vacancies at the interface of the IGZO film become the same as those in the film of the IGZO single film 602. It means that the occurrence is suppressed.
次に、実施例４、５として、実施例１とは成膜時の酸素分圧のみを４.４×１０−３Ｐａから２.２×１０−３Ｐａに変化させ、非成膜時の真空成膜室内の酸素分圧を８．６×１０−３Ｐａ又は２.８×１０−２Ｐａの酸素分圧にしたＩＧＺＯ積層膜（第１層、第２層、第３層）を基板上に有するホール素子を２つ作製した。比較のため、第１,２,３層と全く同じ組成、成膜条件で同基板上にＩＧＺＯ単独膜を７０ｎｍ成膜した。実施例４，５と比較対象になるＩＧＺＯ単独膜の比抵抗は約２．９×１０−２Ω・ｃｍ、キャリア濃度は約１．２×１０１９ｃｍ−３であった。 Next, as Examples 4 and 5, in Example 1, only the oxygen partial pressure at the time of film formation was changed from 4.4 × 10 −3 Pa to 2.2 × 10 −3 Pa. IGZO laminated film (first layer, second layer, third layer) in which the oxygen partial pressure in the vacuum film-forming chamber is 8.6 × 10 −3 Pa or 2.8 × 10 −2 Pa is used as the substrate Two Hall elements were prepared. For comparison, an IGZO single film of 70 nm was formed on the same substrate with the same composition and film formation conditions as the first, second and third layers. The specific resistance of the IGZO single film to be compared with Examples 4 and 5 was about 2.9 × 10 −2 Ω · cm, and the carrier concentration was about 1.2 × 10 19 cm −3 .
図１２は、非成膜時の酸素分圧を８．６×１０−３Ｐａ又は２.８×１０−２Ｐａの酸素分圧にして成膜した、ＩＧＺＯの積層膜２素子の比抵抗について、非成膜時の真空成膜室内の酸素分圧を横軸にプロットしたものである。図１３は、非成膜時の酸素分圧を８．６×１０−３Ｐａ又は２.８×１０−２Ｐａの酸素分圧にして成膜した、ＩＧＺＯの積層膜２素子のキャリア濃度について、非成膜時の真空成膜室内の酸素分圧を横軸にプロットしたものである。
図１２によると、非成膜時の真空成膜室内の酸素分圧を成膜時より高めることで積層膜の比抵抗値は、単独膜の比抵抗値とほぼ一致していることがわかる。また、図１３によると、非成膜時の真空成膜室内の酸素分圧を成膜時より高めることで、積層膜のキャリア濃度は、単独膜のキャリア濃度とほぼ一致していることがわかる。この事実は、非成膜時の真空成膜室内の酸素分圧を高めることで、ＩＧＺＯ膜界面の酸素欠損がＩＧＺＯ単独膜の膜中と同程度になり、余剰キャリアの発生を抑制していることを意味している。また、非成膜時の酸素分圧を制御することによる酸素欠損制御手法が、異なる成膜条件で成膜した酸化物半導体の積層膜においても可能な、普遍的な制御技術であることを示している。
FIG. 12 shows the specific resistance of two IGZO multilayer films formed with an oxygen partial pressure during non-film formation of 8.6 × 10 −3 Pa or 2.8 × 10 −2 Pa. The oxygen partial pressure in the vacuum film formation chamber during non-film formation is plotted on the horizontal axis. FIG. 13 shows the carrier concentration of the IGZO multilayer film 2 element formed by setting the oxygen partial pressure at the time of non-film formation to an oxygen partial pressure of 8.6 × 10 −3 Pa or 2.8 × 10 −2 Pa. The oxygen partial pressure in the vacuum film formation chamber during non-film formation is plotted on the horizontal axis.
According to FIG. 12, it can be seen that the specific resistance value of the laminated film substantially matches the specific resistance value of the single film by increasing the oxygen partial pressure in the vacuum film formation chamber during non-film formation as compared to during film formation. In addition, according to FIG. 13, it can be seen that the carrier concentration of the laminated film substantially matches the carrier concentration of the single film by increasing the oxygen partial pressure in the vacuum film formation chamber during non-film formation as compared to during film formation. . The fact is that by increasing the oxygen partial pressure in the vacuum film formation chamber during non-film formation, the oxygen vacancies at the interface of the IGZO film become the same as in the film of the IGZO single film, and the generation of excess carriers is suppressed. It means that. In addition, it is shown that the oxygen deficiency control method by controlling the oxygen partial pressure during non-film formation is a universal control technology that can be applied to oxide semiconductor stacked films formed under different film formation conditions. ing.
次に、上述した電子デバイスの製造方法を用い、以下表３のような各層の組成及び成膜時の酸素分圧を変調したＩＧＺＯ積層膜を有したホール素子を２通り作製した。２通りのうち、一方は、このような組成・酸素変調を施した積層膜について、各層成膜中の酸素分圧と各層成膜工程後（非成膜時）の酸素分圧が同じである比較例４のホール素子であり、他方は、各層成膜中の酸素分圧よりも各層成膜工程後の酸素分圧を２.８×１０−２Ｐａに高めた実施例６のホール素子である。なお、基板及び評価方法は上述した実施例・比較例と同様である。膜組成及び、成膜中の酸素分圧は比較例４、実施例６共に全く同じである。表４に、比較例４と実施例６の成膜時と非成膜時の酸素分圧を示す。 Next, using the electronic device manufacturing method described above, two Hall elements having IGZO laminated films in which the composition of each layer and the oxygen partial pressure during film formation were modulated as shown in Table 3 below were produced. One of the two types has the same oxygen partial pressure during film formation and oxygen partial pressure after each film formation process (when no film is formed) in the laminated film subjected to such composition / oxygen modulation. The other is the Hall element of Comparative Example 4, and the other is the Hall element of Example 6 in which the oxygen partial pressure after each layer deposition step is increased to 2.8 × 10 −2 Pa than the oxygen partial pressure during each layer deposition. is there. The substrate and the evaluation method are the same as those in the above-described examples and comparative examples. The film composition and the oxygen partial pressure during film formation are exactly the same in Comparative Example 4 and Example 6. Table 4 shows the partial pressures of oxygen during film formation and non-film formation in Comparative Example 4 and Example 6.
図１４は、比較例４と実施例６の積層膜の比抵抗をプロットした図である。また、図１５は、比較例４と実施例６の積層膜のキャリア濃度をプロットした図である。
図１４に示すように、比較例４に対して、実施例６の方が比抵抗値は一桁弱高くなっていることが分かる。また、図１５に示すように、比較例４に対して、実施例６の方がキャリア濃度は一桁弱低くなっていることが分かる。これらの結果は、非成膜時の酸素分圧を高めることで、膜組成及び成膜時の酸素分圧を変調した積層膜においても、各ＩＧＺＯ膜界面の酸素欠損の増大による低抵抗化を抑制し、かつ、余剰キャリアの発生を抑制していることを意味している。
また、実施例６の第３層のみの比抵抗値を測定すると、１．４×１０７Ω・ｃｍであることを確認した。この結果、図１４の比抵抗値を考慮すると、実施例６に係るＩＧＺＯ積層膜は、半導体の層の上に絶縁体の層を有していることになり、このような半導体の層と絶縁体の層の層構成においても半導体の層の余剰キャリアの発生を抑制できることがわかった。
FIG. 14 is a graph plotting the specific resistances of the laminated films of Comparative Example 4 and Example 6. FIG. 15 is a graph plotting the carrier concentration of the laminated films of Comparative Example 4 and Example 6.
As shown in FIG. 14, it can be seen that the specific resistance value of Example 6 is slightly lower than that of Comparative Example 4 by an order of magnitude. Further, as shown in FIG. 15, it can be seen that the carrier concentration in Example 6 is slightly lower than that in Comparative Example 4 by an order of magnitude. These results show that by increasing the oxygen partial pressure at the time of non-film formation, even in a laminated film in which the film composition and the oxygen partial pressure at the time of film formation are modulated, the resistance is reduced by increasing oxygen vacancies at each IGZO film interface. This means that the generation of excess carriers is suppressed.
Moreover, when the specific resistance value of only the third layer of Example 6 was measured, it was confirmed to be 1.4 × 10 7 Ω · cm. As a result, when the specific resistance value of FIG. 14 is taken into consideration, the IGZO multilayer film according to Example 6 has an insulator layer on the semiconductor layer, and is insulated from such a semiconductor layer. It was found that the generation of surplus carriers in the semiconductor layer can be suppressed even in the layer structure of the body layer.
１０ 基板
１２ 第１層
１４ 第２層
２０ 電子デバイス
１００ スパッタ装置
１０２ 基板ホルダ
１０４ プラズマ電極（ターゲットホルダ）
１０６ シャッター
１０８ 真空成膜室
２００ 薄膜トランジスタ
２０８ 活性層（第１層）
２１０ ゲート絶縁層（第２層）
３００ 薄膜トランジスタ
３０２ 活性層（第１層）
３０８ ゲート絶縁層（第２層）
４００ 薄膜トランジスタ
４０４ ゲート絶縁層（第２層又は第１層）
４０６ 活性層（第１層）
５００ ホール素子（電子デバイス）
５０２ 基板
５０４ 第１層（第３層）
５０６ 第２層（第１層）
５０８ 第３層（第２層）
６００ ホール素子（電子デバイス）
10 substrate 12 first layer 14 second layer 20 electronic device 100 sputtering apparatus 102 substrate holder 104 plasma electrode (target holder)
106 Shutter 108 Vacuum deposition chamber 200 Thin film transistor 208 Active layer (first layer)
210 Gate insulation layer (second layer)
300 Thin Film Transistor 302 Active Layer (First Layer)
308 Gate insulation layer (second layer)
400 Thin film transistor 404 Gate insulating layer (second layer or first layer)
406 Active layer (first layer)
500 Hall element (electronic device)
502 substrate 504 first layer (third layer)
506 Second layer (first layer)
508 Third layer (second layer)
600 Hall element (electronic device)
Claims (12)
前記第１層上に前記第１層と同一材料又は異なる材料からなる第２層を成膜する第２成膜工程と、
前記第１成膜工程後前記第２成膜工程前までの間、前記第１層を、前記真空成膜室を含む大気と遮断された室内で、前記第１成膜工程における前記真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する分圧制御工程と、
を有する電子デバイスの製造方法。 A first film-forming step of forming a first layer containing an oxide semiconductor having oxygen non-stoichiometry on a substrate in a vacuum film-forming chamber cut off from the atmosphere;
A second film forming step of forming a second layer made of the same material or a different material as the first layer on the first layer;
The vacuum film formation in the first film formation step is performed in a chamber isolated from the atmosphere including the vacuum film formation chamber, after the first film formation step and before the second film formation step. A partial pressure control step for maintaining the oxygen partial pressure higher than the oxygen partial pressure in the room;
Manufacturing method of electronic device having
請求項１に記載の電子デバイスの製造方法。 In the partial pressure control step, the oxygen partial pressure after the first film formation step and before the second film formation step is 2.1 × 10 −3 compared to the oxygen partial pressure in the first film formation step. Higher than Pa,
The manufacturing method of the electronic device of Claim 1.
前記第１成膜工程では、前記第１真空成膜室で前記第１層を成膜し、
前記第２成膜工程では、前記第２真空成膜室で前記第２層を成膜し、
前記分圧制御工程では、前記第１真空成膜室内、前記搬送室内、及び前記第２真空成膜室内の酸素分圧を、前記第１成膜工程における前記第１真空成膜室内の酸素分圧よりも高くする、
請求項１又は請求項２に記載の電子デバイスの製造方法。 The vacuum film formation chamber includes a first vacuum film formation chamber and a second vacuum film formation chamber connected to the first vacuum film formation chamber via a transfer chamber,
In the first film formation step, the first layer is formed in the first vacuum film formation chamber,
In the second film formation step, the second layer is formed in the second vacuum film formation chamber,
In the partial pressure control step, the oxygen partial pressure in the first vacuum film formation chamber, the transfer chamber, and the second vacuum film formation chamber is set to the oxygen partial pressure in the first vacuum film formation chamber in the first film formation step. Higher than pressure,
The manufacturing method of the electronic device of Claim 1 or Claim 2.
前記第１成膜工程及び前記第２成膜工程を同一の前記真空成膜室内で行う場合には、前記第１成膜工程後前記第２成膜工程前までの間、前記分圧制御工程を行うと共に、前記同一の真空成膜室内において前記ターゲットホルダと前記基板との間にシャッターを配置する、
請求項１又は請求項２に記載の電子デバイスの製造方法。 In the first film formation step and the second film formation step, the substrate is disposed in the vacuum film formation chamber, the vacuum film formation chamber, holds a target, and faces the target holder, and the substrate A film is formed by a sputtering apparatus including a substrate holder for holding a plasma, and a plasma generation unit that generates a plasma space between the target holder and the substrate,
When the first film formation step and the second film formation step are performed in the same vacuum film formation chamber, the partial pressure control step is performed after the first film formation step and before the second film formation step. And arranging a shutter between the target holder and the substrate in the same vacuum film formation chamber,
The manufacturing method of the electronic device of Claim 1 or Claim 2.
請求項１〜請求項４の何れか１項に記載の電子デバイスの製造方法。 The first layer is an oxide semiconductor layer containing at least one element of In, Ga, Zn, and Sn.
The manufacturing method of the electronic device of any one of Claims 1-4 .
請求項５に記載の電子デバイスの製造方法。 The first layer is an oxide semiconductor layer containing In x Ga y Zn z O δ (x, y, z, δ> 0).
The manufacturing method of the electronic device of Claim 5 .
請求項６に記載の電子デバイスの製造方法。 The substrate has flexibility, and the first layer and the second layer are amorphous.
The manufacturing method of the electronic device of Claim 6 .
前記第２成膜工程では、絶縁体からなる前記第２層を成膜する、
請求項１〜請求項７の何れか１項に記載の電子デバイスの製造方法。 In the first film formation step, the first layer made of the oxide semiconductor is formed ,
In the second film formation step, the second layer made of an insulator is formed.
The method of manufacturing an electronic device according to any one of claims 1 to 7.
前記第１成膜工程では、前記基板上に前記第３層を介して前記第１層を成膜し、かつ、前記第３層の成膜工程後前記第１成膜工程前までの間、前記第３層を、前記第３層の成膜工程における前記真空成膜室内の酸素分圧よりも高い酸素分圧下に保持する、
請求項１〜請求項８の何れか１項に記載の電子デバイスの製造方法。 Before the first film forming step, including a film forming step of forming a third layer containing an oxide semiconductor having oxygen non-stoichiometry on the substrate in the vacuum film forming chamber;
In the first film forming step, the first layer is formed on the substrate via the third layer, and after the third layer forming step and before the first film forming step, Holding the third layer under an oxygen partial pressure higher than the oxygen partial pressure in the vacuum film forming chamber in the film forming step of the third layer;
The manufacturing method of the electronic device of any one of Claims 1-8 .
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| KR101273143B1 (en) * | 2008-08-29 | 2013-06-17 | 가부시키가이샤 아루박 | Method and device for manufacturing field-effect transistor |
| JP5537787B2 (en) * | 2008-09-01 | 2014-07-02 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
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