CN102403225B - Manufacturing method and device of channel double-diffusion metal oxide semiconductor - Google Patents
Manufacturing method and device of channel double-diffusion metal oxide semiconductor Download PDFInfo
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- CN102403225B CN102403225B CN 201010275941 CN201010275941A CN102403225B CN 102403225 B CN102403225 B CN 102403225B CN 201010275941 CN201010275941 CN 201010275941 CN 201010275941 A CN201010275941 A CN 201010275941A CN 102403225 B CN102403225 B CN 102403225B
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Abstract
The invention relates to a manufacturing method and a device of a channel double-diffusion metal oxide semiconductor. The manufacturing method comprises the following steps of: doping; glue-injecting and grinding; etching; cleaning; heat treatment; and spattering. In a treatment process on the back, after the heat treatment process is adopted, the situation that the source and drain (source electrode and drain electrode) soft breakdown failure does not occur in the channel double-diffusion metal oxide semiconductor is effectively improved by detecting the data of a wafer. Meanwhile, the adopted device can be realized correspondingly by the existing high-temperature furnace without specially purchasing new equipment or special equipment, so that the cost is saved, and the economic benefit is improved.
Description
[technical field]
The present invention relates to a kind of manufacture method and device of semiconductor device, relate in particular to a kind of manufacture method and device of irrigation canals and ditches double diffusion metal-oxide semiconductor.
[background technology]
The develop rapidly of scientific and technological level, electronics and semiconductor technology also obtain fast development.Adopt a large amount of fields such as communication, office, commercial affairs that are applied in of electronic devices and components of semiconductor technology manufacturing, as computer, mobile phone, television set etc.Along with expanding economy, above-mentioned field constantly increases the demand of electronic devices and components, has also produced to wish that these products can become littler, demand, motor-driven more flexible such as be easier to carry.
Because the size of these products will constantly reduce, the components and parts that constitute these products also must diminish.That corresponding integrated circuit size, transistorized size are also more and more littler.Irrigation canals and ditches (trench) double diffusion metal-oxide semiconductor (Double Metal Oxide Semiconductor DMOS) transistor is that a kind of metal oxide semiconductor field effect is answered transistor (MOSFETs), and the DMOS transistor unit is also more and more littler.
Therefore the manufacture process requirement of the wafer of being made up of trench dmos is very high, also very easy damage of while.In application number is 200810119488.4 Chinese patent, disclose a kind of two kinds of different atoms that mix at the wafer back side, and then improved contact resistance between wafer back metal and the wafer and reduce to leak the diode forward conducting voltage with the source and reduce.As seen the problem of soft breakdown is leaked in the inreal solution of this method source, the wafer back side.In the back process of traditional trench dmos, shown in Fig. 6 and 7,15 some position measurements at wafer, there is the test of 4 points soft breakdown (series 12,13,14 and 15) to occur as can be known, as seen the probability of the inefficacy appearance due to the source of the product leakage soft breakdown is very high, causes the electrical inefficacy of product.
[summary of the invention]
In view of this, be necessary to leak the very high problem of probability that the inefficacy due to the soft breakdown occurs at the source, a kind of irrigation canals and ditches double diffusion metal-oxide semiconductor manufacture method is provided.
In addition, also necessity provides a kind of irrigation canals and ditches double diffusion metal-oxide semiconductor producing device at the very high problem of probability that the inefficacy due to the leakage soft breakdown of source occurs.
A kind of irrigation canals and ditches double diffusion metal-oxide semiconductor manufacture method comprises the steps: to mix; Injecting glue and grinding; Etching; Clean; Heat treatment; Sputter.
Preferably, the temperature in the described heat treatment process is 170 ℃～210 ℃.
Preferably, described temperature is 180 ℃.
Preferably, described heat treatment period is 15～60 minutes.
Preferably, the described time is 40 minutes.
Preferably, the chemical solution that adopts in the described etching process is that sulfuric acid, nitric acid and ammonium acid fluoride mix the solution of formation or the mixing material of hydrofluoric acid, nitric acid and water.
Preferably, adopt the mixed solution of ethylene glycol and hydrofluoric acid to clean spot in the described cleaning process.
Preferably, described sputter is sputtered titanium, nickel, the silver to wafer back side layering successively; Chromium, yellow gold or chromium, nickel, silver.
A kind of irrigation canals and ditches double diffusion metal-oxide semiconductor producing device comprises lithographic equipment, cleaning device and sputter equipment, also comprises annealing device; Wafer carries out back-etching by lithographic equipment and by after the cleaning device cleaning drying, handles through annealing device again, finishes the wafer back spatter by sputter equipment at last.
Preferably, described annealing device also comprises loading stage and high temperature furnace, and described loading stage loads wafer, and described high temperature furnace is heat-treated wafer.
Through treatment process overleaf, after adopting heat treatment process, by to the wafer detection data, effectively improve irrigation canals and ditches double diffusion metal-oxide semiconductor and the situation that (source electrode and drain electrode) soft breakdown inefficacy is leaked in the source do not occur, improve the quality of wafer slice, improved output and economic benefit.
The wafer that the device of the above-mentioned wafer of process back side treatment process obtains, this device just can be realized by existing oven or high temperature furnace, does not need to buy especially new equipment or special equipment, provides cost savings, and has improved economic benefit.
[description of drawings]
Fig. 1 is wafer back side processing technological flow figure;
Fig. 2 is that an embodiment wafer heat treatment temperature is 170 ℃ experimental data figure;
Fig. 3 is that an embodiment wafer heat treatment temperature is 210 ℃ experimental data figure;
Fig. 4 is that an embodiment wafer heat treatment time is the experimental data figure of 15min;
Fig. 5 is that an embodiment wafer heat treatment time is the experimental data figure of 60min;
Fig. 6 is the resolution chart of an embodiment wafer detection position point 1 to 15;
Fig. 7 is the experiment effect figure that an embodiment wafer position probing adopts conventional method;
Fig. 8 is the experiment effect figure that an embodiment wafer position probing adopts this patent method.
[embodiment]
By in the process of wafer back side flow process, increasing by a heat treatment step, the probability that makes the soft breakdown of irrigation canals and ditches (trench) double diffusion metal-oxide semiconductor (Double Metal Oxide Semiconductor DMOS) lose efficacy by heat treatment lowers or this phenomenon can not occur, and then obtains high-quality wafer product.
Shown in Fig. 1～7, a kind of irrigation canals and ditches double diffusion metal-oxide semiconductor manufacture method comprises the steps:
At first, step S110 mixes to the wafer back side, and the control certain energy is injected the wafer back side to atom or ion, thereby forms the superficial layer with special nature in selected zone, reaches the purpose of doping.
Step S120 attaches protective tapes in the wafer front, and the thickness of described protective tapes is limited to the poor of predetermined wafer thickness more than or equal to the minimum grinding thickness of lapping device.Then the wafer back side is ground, make wafer reach leveling.
Step S130, etching after the film exposure and developing, adopts chemical liquid to carry out etching, thus figure or groove that acquisition needs.Described chemical solution can be sulfuric acid (H
2SO
4), nitric acid (HNO
3) and ammonium acid fluoride (NH
4HF
2) solution that mix to form, or hydrofluoric acid (HF), nitric acid (HNO
3) and the mixing material of water.
Step S140 cleans, to grind or in etching process institute's particle that carries over or spot, clean or dry by EGBHF (mixed solution of ethylene glycol and BHF hydrofluoric acid).
Step S150, heat treatment is sent in the stove wafer and to be heat-treated.Temperature control in the stove is at 170 ℃～210 ℃, and preferred temperature is 180 ℃; Heat treatment period control was at 15～60 minutes, and the preferred time is 40 minutes.
Step S160, sputter, through heat treated wafer, sputtered titanium, nickel, the silver to wafer back side layering successively (can be chromium, yellow gold then; Or chromium, nickel, silver) step.
Through the treatment process at the above-mentioned wafer back side, by to the wafer centre position, especially survey in the edge of wafer.The back process flow process of this method is not used in contrast, prove that at 14 location points (Fig. 2～5 and Fig. 7) of gathering above-mentioned technology effectively improved trench dmos, trench dmos metal-oxide semiconductor the source do not occur and leaks the situation that (source electrode and drain electrode) soft breakdown was lost efficacy, and then improved the quality of wafer slice, improved output and economic benefit.
In addition, also provide a kind of irrigation canals and ditches double diffusion metal-oxide semiconductor producing device.Described device comprises doper, lapping device, lithographic equipment, cleaning device, annealing device and sputter equipment.Described annealing device comprises loading stage and high temperature furnace.Doper mixes to the wafer back side; then lapping device grinds in the front and to the back side of wafer the wafer attaching protective tapes that mixes; clean to the wafer back-etching and at cleaning device by lithographic equipment then; dry; clean wafer is loaded on the regular loading stage; send loading good wafer into high temperature furnace by conveyer belt; process is at 170 ℃～210 ℃; 15～60 minutes heat treatment; by sputter equipment wafer rear is carried out the sputtered titanium of layering at last; nickel; silver; chromium; yellow gold or chromium; nickel; silver is finished back process.
The wafer that the device of the above-mentioned wafer back process of process obtains, by partly being led, the trench dmos irrigation canals and ditches double diffusion metal oxide layer on the wafer carries out manual probe test, especially pass through 170 ℃～210 ℃ of temperature, in 15～60 minutes the heat treatment process not the discovery source leak the situation that soft breakdown was lost efficacy, especially leak the wafer edge that soft breakdown lost efficacy and also do not find in the easiest source that occurs.This device just can be realized by existing high temperature furnace, does not need to buy especially new equipment or special equipment, therefore provides cost savings, and has improved economic benefit.
The above embodiment has only expressed embodiments of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (1)
1. an irrigation canals and ditches double diffusion metal-oxide semiconductor manufacture method is characterized in that, comprises the steps:
Mix;
Injecting glue and grinding;
Etching; The chemical solution that adopts in the described etching process is that sulfuric acid, nitric acid and ammonium acid fluoride mix the solution of formation or the mixing material of hydrofluoric acid, nitric acid and water;
Clean; Adopt the mixed solution of ethylene glycol and hydrofluoric acid to clean spot in the described cleaning process;
Heat treatment, the temperature in the described heat treatment process are 180 ℃, and described heat treatment period is 40 minutes;
Sputter; Described sputter is to the sputtered titanium at wafer back side layering successively, nickel, silver, chromium, yellow gold, or chromium, nickel, silver.
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| CN 201010275941 CN102403225B (en) | 2010-09-07 | 2010-09-07 | Manufacturing method and device of channel double-diffusion metal oxide semiconductor |
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| CN102403225B true CN102403225B (en) | 2013-08-14 |
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| CN103157620B (en) * | 2011-12-14 | 2016-04-06 | 北大方正集团有限公司 | The cleaning fluid of cleaning before a kind of silicon wafer back face metalization and cleaning method |
| JP6493095B2 (en) * | 2014-09-18 | 2019-04-03 | セントラル硝子株式会社 | Wafer cleaning method and chemical solution used for the cleaning method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574353A (en) * | 2003-06-11 | 2005-02-02 | 株式会社瑞萨科技 | Semiconductor device and method of manufacturing the same |
| CN101276767A (en) * | 2007-03-26 | 2008-10-01 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN101399196A (en) * | 2007-09-29 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Coarsening processing method for backing side of wafer |
| CN101494167A (en) * | 2008-01-25 | 2009-07-29 | 株式会社瑞萨科技 | Method of manufacturing a semiconductor device |
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| KR20110028393A (en) * | 2008-08-29 | 2011-03-17 | 가부시키가이샤 아루박 | Method and device for manufacturing field-effect transistor |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574353A (en) * | 2003-06-11 | 2005-02-02 | 株式会社瑞萨科技 | Semiconductor device and method of manufacturing the same |
| CN101276767A (en) * | 2007-03-26 | 2008-10-01 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN101399196A (en) * | 2007-09-29 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Coarsening processing method for backing side of wafer |
| CN101494167A (en) * | 2008-01-25 | 2009-07-29 | 株式会社瑞萨科技 | Method of manufacturing a semiconductor device |
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Effective date of registration: 20171011 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214000 No. 5 Hanjiang Road, national hi tech Industrial Development Zone, Wuxi, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |