CN102158336B - Multi-channel isolated high-speed intelligent transmitting-receiving device and method for power electronic system - Google Patents
Multi-channel isolated high-speed intelligent transmitting-receiving device and method for power electronic system Download PDFInfo
- Publication number
- CN102158336B CN102158336B CN 201110083880 CN201110083880A CN102158336B CN 102158336 B CN102158336 B CN 102158336B CN 201110083880 CN201110083880 CN 201110083880 CN 201110083880 A CN201110083880 A CN 201110083880A CN 102158336 B CN102158336 B CN 102158336B
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- data
- sampling
- receiving element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
The invention discloses a multi-channel isolated high-speed intelligent transmitting-receiving device and method for a power electronic system. The device comprises transmitting units, receiving units and isolated transmission mediums. Each transmitting unit comprises a data sampling and signal conditioning module, an A/D (Analog/Digital) conversion module, a transmitting main control unit and a transmitting unit signal conversion module; each receiving unit comprises a receiving unit signal conversion module, a receiving unit signal conditioning module, a receiving main control unit and a memory output module. The device can perform digital coding on multi-channel analog sampling and switch sampling, and transmits through the isolated transmission mediums; each receiving unit can be connected with a plurality of the transmitting units for simultaneously decoding. The multi-channel isolated high-speed intelligent transmitting-receiving device has the advantages of prominent high-reliable electrical isolation performance, instantaneity and intelligent performance.
Description
Technical field
The present invention relates to a kind of Multichannel isolation high-speed intelligent transmitter-receiver device for power electronic system and method, be specially adapted to the sampling Design of complicated medium-and-large-sized power power electronic system.
Background technology
At present, a development trend of power electronic equipment is complex system and high power, the main power device of power electronic equipment produces very high electric current and voltage change ratio in switching process, they produce electromagnetic noise by electric capacity parasitic in circuit and inductance, easily sampling circuit is produced and disturb, affect sampling precision.The control unit of conventional power converters is most directly to be docked with sampling unit through metallic cable, and electromagnetic environment very easily affects the signal transmission in cable.Digital signal processor is made a response by sampled signal, is transferred to power cell and does corresponding actions.If mistake appears in sampling, can greatly affect systematic function, even may cause the paralysis of whole system.
Current, traditional sensors mostly is simple passive sampling and signal transmission, does not have from master-priority judgement and error correcting capability, and lower floor's control unit amount of calculation is increased, and drags slow system response time.And traditional sensors only transmits for a signal, for three-phase or heterogeneous application scenario, needs simultaneously a plurality of voltage and current signals to be monitored, and wiring complexity and cost are obviously increased.From present development, the numerically controlled mode of the general employing of Complex Power electronic system main control unit, applicable traditional sensors can carry out the one-off pattern number conversion at control end, and this process easily produces error or introduces and disturb.
Along with the development of high voltage isolation techniques and digital processing technology, adopt digital transmission means to replace analogue transmission mode, high isolation medium to replace the technology of common metal cable ripe in the modern power electronic sampling system.With traditional sampling transmission means relatively, the digital transmission mode of high isolation has that electrical insulation properties is good, dynamic range large, be difficult for the advantages such as saturated.The replacement of metallic cable makes communication quicker more reliable.
Based on above analysis, be necessary to invent a kind of Multichannel isolation high-speed intelligent transmitter-receiver device, make it keep sampling simple in structure to have simultaneously accurately the characteristics such as high isolation, high reliability and high real-time.
Summary of the invention
Purpose of the present invention provides a kind of Multichannel isolation high-speed intelligent transmitter-receiver device for power electronic system and method.
for achieving the above object, the technical solution adopted in the present invention is: the Multichannel isolation high-speed intelligent transmitter-receiver device that should be used for power electronic system comprises transmitting element, receiving element and isolation transmission medium, described transmitting element comprises data sampling and signal condition module, A/D modular converter, sends main control unit and transmitting element signal conversion module, and described transmission main control unit comprises controlling of sampling module, data coding module and check code implant module, described receiving element comprises receiving element signal conversion module, receiving element signal condition module, receives main control unit and storage output module, and described reception main control unit comprises that Clock Extraction and synchronization module, initial order judge module, data decode module conciliate the code check module, described data sampling and signal condition module are connected with the input of A/D modular converter, the output of A/D modular converter is connected with control end and is connected with described controlling of sampling module, described controlling of sampling module is connected with described check code implant module, described check code implant module is connected with data coding module, and data coding module is connected with described transmitting element signal conversion module, the input of described receiving element signal conversion module is connected with the transmitting element signal conversion module by described isolation transmission medium, the output of described receiving element signal conversion module is connected with the input of described receiving element signal condition module, output while and described Clock Extraction and the synchronization module of described receiving element signal condition module, described initial order judge module connects, output while and the described initial order judge module of described Clock Extraction and synchronization module, described decoding correction verification module, described data decode module connects, the output of described initial order judge module is connected with the input of described data decode module, the output of described decoding correction verification module is connected with the input of described data decode module, the output of described data decode module is connected with described storage output module.
Further, transmission main control unit of the present invention and reception main control unit are field programmable logic array.
Further, the analog quantity sampling channel quantity of the data sampling of transmitting element of the present invention and signal condition module is 1～4.
Further, the switching value sampling channel quantity of transmitting element of the present invention is 1～3.
The method that the present invention uses above-mentioned Multichannel isolation high-speed intelligent transmitter-receiver device to carry out data transmit-receive comprises the steps:
(1) gathered analog signals and sent to the A/D modular converter by data sampling and signal condition module, the A/D modular converter converts described analog signals digital quantity signal to and sends to the controlling of sampling module; And/or
Gather the switching value signal by the controlling of sampling module;
(2) the controlling of sampling module expands described switching value signal and/or received digital quantity signal so that the signal after expanding comprises beginning flag, address bit, data bit, switching value position and finishes flag; Signal after the post-sampling control module will be expanded sends to the check code implant module;
(3) the check code implant module is implanted check digit to the signal after received expansion and is formed new Frame; Rear check code implant module sends to data coding module with described new Frame;
(4) data coding module will convert the high-low level signal to from the new Frame that the check code implant module receives; Rear data coding module sends to the transmitting element signal conversion module with described high-low level signal;
(5) the transmitting element signal conversion module sends in the receiving element signal conversion module by the isolation transmission medium after converting received high-low level signal to signal that corresponding isolation transmission medium can support;
(6) the receiving element signal conversion module sends to receiving element signal condition module after converting all received data-signals to the signal of telecommunication;
(7) described receiving element signal condition module is being carried out the received signal of telecommunication to be converted to the TTL signal after the voltage magnitude coupling, and rear described receiving element signal condition module sends to respectively Clock Extraction and synchronization module and initial order judge module with described TTL signal;
(8) described Clock Extraction and synchronization module extract synchronizing clock signals from received TTL signal; Described Clock Extraction and synchronization module send to decoding correction verification module and initial order judge module simultaneously with described synchronizing clock signals and TTL signal, and described Clock Extraction and synchronization module send to described data decode module with described synchronizing clock signals, and described initial order judge module sends to described data decode module after extracting initial order according to described synchronizing clock signals from received TTL signal; Described decoding correction verification module carries out verification and check results and this TTL signal is sent to described data decode module received TTL signal according to described synchronizing clock signals;
(9) described data decode module is decoded to received TTL signal according to described initial order, synchronizing clock signals and described check results and is obtained address bit and data bit information in this TTL signal, and described address bit and data bit information are sent in the register of storage output module.
Compared with prior art, the invention has the beneficial effects as follows:
(1) the isolation transmission medium can be isolated for optical fiber, rf wireless signal isolation, multicore cable and light-coupled isolation combination or multicore cable and transformer isolation make up, replace the classical signal transmission cable by the non-contact transmission mode, thoroughly solve wiring and be subject to the problems such as electromagnetic interference, improved accuracy and the reliability of system.
(2 transmitting elements can gather analog quantity or switching value, and will both make up.Namely can simplied system structure, reduce the sampling cost, can effectively utilize communication bandwidth again.
(3) improved signal transmission structure.In the modern power electronic system, control device mostly is digital device, need to be through over-sampling maintenance, multicircuit switch and analog-to-digital conversion when traditional sample circuit analog output signal is transferred to described digital device.Apparatus of the present invention leave the storage output module in sampled signal in through transmission and after processing, and can directly be read use by described digital device, omit the signal conversion process, simplify hardware configuration, and reduce the signal interference channel.
(4) sending main control unit is field programmable logic array (FPGA) with receiving main control unit, realizes the data processing by Programmable Design.Prior art mostly is hardware designs or single-chip microcomputer design, and apparatus of the present invention have the characteristics simple, that expandability is strong of safeguarding in contrast.
(5) line between sampling unit and control device is more simple.In the conventional electric power electronic system, when needing multiple spot is sampled, need to carry out complicated line.And apparatus of the present invention can realize multi-channel sampling, and by point-to-point, multi-multipoint and multiple spot, the single-point communication mode are reduced a large amount of lines, simplify communication process, improve the accuracy of system.
(6) traditional isolation signals transmitting device transmitting-receiving two-end needs ad hoc clock transfer circuit, and is perhaps synchronous by GPS, so that the two ends clock phase is identical.Apparatus of the present invention directly extract clock by further improved Clock Extraction and synchronization module from the transmission of data, do not need ad hoc clock line and GPS synchronous, can reduce design complexities like this, can reduce costs again.
(7) the present invention and method are applicable to the Complex Power electronic system, and be applicable equally to electric power system, has outstanding highly reliable electrical separation, real-time.
Description of drawings
Fig. 1 is the structural representation of intelligent receive-transmit device of the present invention;
Fig. 2 is the structural representation of the transmitting element of intelligent receive-transmit device of the present invention;
Fig. 3 is the structural representation of the receiving element of intelligent receive-transmit device of the present invention;
Fig. 4 is the structure chart of the defined Frame of intelligent receive-transmit device of the present invention;
Fig. 5 is the extraction of intelligent receive-transmit device of the present invention and the work schematic diagram of synchronization module;
Fig. 6 is the working method schematic diagram of the storage output module of intelligent receive-transmit device of the present invention.
Fig. 7 is the data sampling of intelligent receive-transmit device of the present invention and the schematic diagram of signal condition module.
Fig. 8 is the schematic diagram of the receiving element signal condition module of intelligent receive-transmit device of the present invention.
Fig. 9 is the work schematic diagram that in intelligent receive-transmit device of the present invention, receiving element is joined a plurality of transmitting elements.
Embodiment
In Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention, isolation transmission medium 4 can be isolated for optical fiber, rf wireless signal isolation, multicore cable and light-coupled isolation combination or multicore cable and transformer isolation make up.The form that signal exists in different isolation transmission mediums is also different, for example adopts laser to transmit in optical fiber, is the magnetic field alternating signal in transformer isolation.The present invention solves thoroughly that in power electronic system, the signal transmission wiring easily is subjected to the problems such as electromagnetic interference, has improved accuracy and the reliability of system.
Transmission main control unit 13 of the present invention and the module that receives in main control unit 23 exist with the programmable module form, and its definition content comprises data transaction form, data frame structure, data check, Clock management and initial synchronizing information.The module that sends main control unit 13 and receive in main control unit 23 is cured in field programmable logic array (FPGA).
Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention has the high-voltage isolating characteristic, if in sampling unit, the sampled voltage signal can directly adopt electric resistance partial pressure or capacitance partial pressure sampling; If the sample rate current signal can use high-power precision resistance series connection to access institute's sampling circuit, power taking resistance both end voltage difference is as current sampling signal, have so the expensive characteristics such as low of precision, sampled signal also can obtain by Hall element or current/voltage special integrated chip.Transmitting element can be inputted the multi-channel sampling data, and sampled signal can be voltage signal, current signal, temperature signal, tach signal, wind flow signal or switching value signal etc.If tradition every profession and trade transducer simulation univoltage amount output port is connected to realize high isolation Digital Transmission after also can mating by voltage magnitude with transmitting element.
The analog quantity sampling channel number of criteria of the data sampling in transmitting element and signal condition module 11 is designed to 4 passages; Switching value sampling channel number of criteria is designed to 3 passages, can adjust by switching value position in the adjustment Frame, consider that every increase One-position switch amount position can increase a clock cycle time-delay, so the scope that arranges of the switching value sampling channel in multichannel isolated intelligent R-T unit of the present invention is preferably 1～3.Require low occasion can increase analog quantity and switching value sampling channel number in sample rate, reduce analog quantity and switching value sampling channel number in the demanding occasion of sample rate.Increase the purpose that number of active lanes can play the economize on hardware cost.The order of several analog quantity sampling channels of data sampling and signal condition module 11 can be adjusted by controlling of sampling module 131.Switching value sampling reality is digital quantity signal, the corresponding digital quantity ' 1 ' of logic high, the corresponding digital quantity ' 0 ' of logic low.Then unit of conventional electric power electronics sample mode signal of can only sampling is connected to key-course by complicated secondary connection, and the passive reception signal of controller judges the running status of power electronic system, then sends the subsequent action instruction.Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention is controlled at sampling end, by adjusting the different signal of sampling order transmission significance level, can make timely reflection to system running state like this, can reduce again the burden of controller, and reduce in a large number the secondary line and reduce costs.
As shown in Figure 9, each receiving element 2 of Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention can connect one or more transmitting elements 1, relatively independent being independent of each other between the receiving element signal conversion module 21 of corresponding different transmitting elements 1, relatively independent being independent of each other between the receiving element signal condition module 22 of same corresponding different transmitting elements 1; The reception main control unit 23 of corresponding different transmitting element 1 can be present in a FPGA module jointly with modular form.Obviously, can expand number is determined by FPGA resource utilization and FPGA running status.
The special feature of Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention is that also the data that receiving element decodes are digital quantity, leave in storage output module 24, can directly offer digital device uses, thereby omit output stage analog signal conditioner circuit, reduce the error the way of production, and can simplify circuit design.Simultaneously, the storage output module 24 of receiving element of the present invention can also provide one or more analog signal output, measures for observing.
The contribution of Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention is also that the switch acquisition signal of same time point and analog sampling signal are included in same frame data and transmits, can effectively improve the passage utilization ratio.
Moreover, Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention carries out when synchronous at clock, and transmitting element does not need to send synchronizing clock signals specially or GPS is synchronous, but directly extracts bit synchronization signal from the digital signal that receives, can effectively reduce system complexity, reduce costs.
According to the function of above-mentioned required realization, device of the present invention is divided into 3 parts, as shown in Figure 1, comprises transmitting element 1, receiving element 2 and isolation transmission medium 4.The transmitting element structure as shown in Figure 2, comprise data sampling and signal condition module 11, A/D modular converter 12, send main control unit 13 and transmitting element signal conversion module 14, send main control unit 13 and comprise controlling of sampling module 131, data coding module 132 and check code implant module 133.the receiving element structure comprises receiving element signal conversion module 21, receiving element signal condition module 22, receives main control unit 23 and storage output module 24 as shown in Figure 3, receive main control unit 23 and comprise that Clock Extraction and synchronization module 231, initial order judge module 232, data decode module 233 conciliate code check modules 234, data sampling and signal condition module 11 are connected with the input of A/D modular converter 12, the output of A/D modular converter 12 is connected with control end and is connected with controlling of sampling module 131, controlling of sampling module 131 is connected with check code implant module 133, check code implant module 133 is connected with data coding module 132, and data coding module 132 is connected with transmitting element signal conversion module 14, the input of receiving element signal conversion module 21 is connected with transmitting element signal conversion module 14 by isolation transmission medium 4, the output of receiving element signal conversion module 21 is connected with the input of receipts cell signal conditioning module 22, output while and Clock Extraction and the synchronization module 231 of receiving element signal condition module 22, initial order judge module 232 connects, output while and the initial order judge module 232 of Clock Extraction and synchronization module 231, decoding correction verification module 234, data decode module 233 connects, the output of initial order judge module 232 is connected with the input of data decode module 233, the output of decoding correction verification module 234 is connected with the input of data decode module 233, the output of data decode module 233 is connected with storage output module 24.
As one embodiment of the present invention, the modulate circuit of data sampling and signal condition module 11 can adopt the amplifier chip LM358 realization of ST company, as shown in Figure 7, and the positive input termination bias voltage of amplifier, the input of negative input termination signal; A/D modular converter 12 can adopt the ADS7950 of American TI Company, has 4 sampling channels, and output form is serial output, and sampling precision is 12, sampling time-delay 800ns; Send main control unit 13 and receive main control unit 23 and can adopt the Cyclone of U.S. altera corp
TMSeries FPGA is as core, and input clock frequency is 20MHz, and FPGA internal work clock frequency reaches as high as 320MHz; In transmitting element, the analog quantity sampling channel is connected with modulate circuit in sampling and signal condition module 11, and the switching value sampling channel directly is connected with the I/O mouth of FPGA.Isolation transmission medium 4 adopts the mode of optical fiber isolation, transmitting element signal conversion module 11 and receiving element signal conversion module 21 can adopt respectively optical fiber sending module HFBR-1527 and the optic fiber transceiver module HFBR-2526 of U.S. AVAGO company, the optical fiber sending module is converted to light signal with the signal of telecommunication, optic fiber transceiver module is converted to the signal of telecommunication with light signal, and the highest communication speed of both supporting is 125Mbps; The isolation transmission medium can adopt the single mode plastic fiber, has high noise immunity, is responsible for connecting transmitting element and receiving element, transmission of digital signals.Receiving element signal condition module is comprised of the ON chip 10H116 of company and MC100ELT as shown in Figure 8, is responsible for the PECL signal condition of receiving unit signal conversion module output is converted to the TTL signal; The storage output module can adopt the FPGA internal register by the D/A converter chip ADS5342 of the external ADI of FPGA I/O mouth company, to reach the purpose of digital signal storage and analog signal output.In present embodiment, the module that sends main control unit 131 and receive in main control unit 23 is present in FPGA with the programmable module form, connect by the FPGA internal logic unit between them, the function of realization comprises definition data transaction form, data frame structure, data check, Clock management and initial synchronizing information.
The course of work of apparatus of the present invention is as follows:
At first, analog sampled data is input to the transmission main control unit by signal condition and A/D conversion with serial mode, and the switching value sampling directly enters the transmission main control unit.Send main control unit same time point sampled data is put into a Frame, before the sampling channel geocoding is placed on sampled data, then add initial order in the Frame first place, the back adds check information and stop bit.The data frame structure that the present invention adopts comprises as shown in Figure 4: 1 of beginning flag; 4 of address bits are encoded to each sampling channel; 12 of data bit, data bit length is by the decision of A/D modular converter, and the data sampling of A/D is generally with 12 definition at present; 5 of check digit; Other 3 is the switching value position, can be the switching value data of number of different types, as the running status of protection information, fault or module; Finish 1 of flag.
The auxiliary cyclic redundancy check (CRC) that realizes after the high-pressure side sampled data is reduced of the check information that transmitting element adds.Because electromagnetic environment is more abominable, the data that intelligent receive-transmit device data sampling of the present invention and signal condition module obtain in the high-pressure side easily are interfered, for the check code implant module in the accuracy transmitting element that guarantees data can be implanted check code in Frame.Consider the amount of calculation that needs minimizing FPGA and reduce taking of transmission bandwidth, in the present invention, the verification generator polynomial adopts common CRC-5=x5+x4+x2+1, and namely corresponding code is 110101, and CRC generation picket code is 5 like this.The process of utilizing CRC to carry out error detection can simply be described as: the k position binary code data sequence that transmits with transmitting element is carried out the computing of computer mould double division method to code corresponding to above-mentioned generator polynomial, be to do XOR between divisor and dividend, the alignment of divisor and dividend highest order, step-by-step XOR from left to right successively when carrying out computing.Obtain at last 5 remainders and be the CRC picket code, be attached to original character string back, consist of the binary code sequence number of a new k+5 position.
Frame replenishes and to be converted to the CMI coding by data coding module after complete, and this coding replaces in initial data ' 0 ' with ' 01 '; With ' 00 ' and ' 11 ' replacement data in ' 1 ', if upper one the cycle with ' 00 ' expression, next cycle use ' 11 ' expression, both hocket; ' 10 ' is unused code.Can avoid so long-time high level and long-time low level situation to exist, make code stream be tending towards balanced, be beneficial to Error detection.Moreover the CMI coded system can be made high-low level conversion as much as possible, for the Clock Extraction of back is provided convenience, reduces the error code probability.Fiber optical transceiver adopts the difference serial I/O high speed signal of PECL standard, and antijamming capability is strong.
Data flow is transformed into light signal via the transmitting element signal conversion module after encoding through CMI, then is transferred to receiving element through optical fiber as the isolation transmission medium.The receiving element signal conversion module of receiving element is reduced to the signal of telecommunication with light signal, transfers to receive the main control unit processing.
The receiving element data transaction is the inverse process of transmitting element, is responsible for receiving and restoring data, then the data storage is read for follow-up secondary device.After obtaining data flow, receive main control unit and at first will produce the clock of synchronizeing with data.The mentioned receiving element clock synchronous of the present invention does not need special synchronised clock line, and concrete implementing method is to utilize digital phase-locked loop DPLL to recover the received bit synchronised clock from the serial bit stream data by Clock Extraction and synchronization module.Designed digital phase-locked loop is a kind of control system with phase feedback, mainly is comprised of along testing circuit, phase discriminator, clock multiplier circuit and frequency divider clock.Its implementation procedure is as follows, and as shown in Figure 5: at first the data with input code flow just change along extracting, and comprising rising edge and trailing edge, the variation that extracts is continued to use very short pulse of time and showed.If the frequency of transmitting element transfer of data is f, be the clock of 16 * f in FPGA internal pair production one frequency.Then rush along the pulse as beginning flag take the data variation of extracting the clock of 16 frequencys multiplication is counted.Often count down to 8 or be input as pulse change along the hour counter output switching activity once, so just obtain one with input data same frequency and the roughly the same clock f of phase place
outAt this moment phase discriminator produces clock f with institute
outAlong comparing, judge f with data jump
outBe leading or hysteresis, then counter is sent control command, if f
outIncrease in advance rolling counters forward, delay output switching activity opportunity; If f
outLag behind and reduce rolling counters forward, make its output upset in advance.By the feedback regulation that continues, dynamically adjust the count results of high-speed counter, finally make output clock f
outPhase place with the input data that is to say the transmitting element clock synchronous.
After extracting synchronised clock, in receiving element, the CMI coded data that receives is reduced to initial data, process is as follows: at first every CMI character string corresponding to initial data will be separated, because CMI coding two bits represents an initial data, and only corresponding ' 00 ' ' 11 ' ' 01 ' the three kind of form of each initial data is some change-over time of two initial data so find from high level to low level hopping edge ' 10 ' in the CMI code.So from this hopping edge, with the CMI code shift register that divides into groups in twos to put into, then reduce according to the contrary rule of CMI coding, just obtain the data flow identical with initial data at last.Apparatus of the present invention are also monitored shift register data in each cycle, if unused code ' 10 ' appears in the inside, mistake appears in the explanation displacement, in time corrects.
Next the initial order judge module will judge the job initiation state of transmitting element, then every frame data in original data stream is separated.As long Distance Transmission device, the electric sequence of transmitting element and the receiving element inconsistent system that can not affect moves.And system increases and reduces the normal operation that continues that transmitting element should not affect whole system midway, and namely transmitting element is supported hot plug (Plug and Play).Whether in the present invention, transmitting element adds initial order in the transmission of data, access so that receiving element judges transmitting element at any time, thereby system can be correctly decoded.Transmitting element of the present invention sends initial order with frame data ' a 1 ' conduct, receiving element starts counter when possible initial order arrives after the transmitting element access, take the synchronised clock fout that extracts as standard logarithmic according in ' 1 ' count, when reaching 15 ' 1 ', the counter continuous counter both can guarantee reliably to judge the transmitting element initial order, can effectively extract the initial order of every frame data again in follow-up, the possibility that herein is disturbed is minimum, at this moment starts decoding program.Send initial order and can adopt other character strings, but the character string repetition in sampled data when working of will guaranteeing to get along well, in order to avoid obscure, and make receiving element accurate and effective extract start bit.Transmitting element of the present invention can send initial order again after every transmission 10 frame valid data in addition, and receiving element rejudges, to reduce the accumulation of error.
In receiving element, after every frame data separated, the decoding correction verification module carried out CRC check to the valid data section of every frame data.With the CRC check multinomial identical with transmitting element, the valid data section is calculated, regenerated 5 CRC codes, then compare with 5 bit check codes that transmitting element inserts, if identical, data are correct, if different, illustrate that mistake appears in data in transmitting procedure.When the CRC check data were incorrect, intelligent receive-transmit device of the present invention output can be kept one group of data, and informed that mistake appears in this sampled data of secondary device.If mistake occurs continuously, judged whether to shut down maintenance by the secondary device controller.
Storing at last output module deposits in correct data in register.8 addressing modes are adopted in data storages, comprise the serial number information of each passage in the serial number information of each transmitting element and transmitting element.Because each circuit-switched data passage is separate, can divide different memory modules in the memory block and distinguish, same passage keeps 3 continuous time point data, automatically replaces the oldest data when having new data to come in.Facilitate like this secondary device to extract simply accurately data, and can effectively utilize memory space.Simultaneously, measuring to observe as need needs, and receiving element can be reduced into digital signal analog signal and use.The storage way of output of data represents by Fig. 6, and secondary device is connected with bus form with register, comprises address wire, data wire and control line; Control line sends read/write signal, then according to the address information on address wire, carries out register read/write operation by data wire.
As shown in Figure 9, each receiving element 2 of Multichannel isolation high-speed intelligent transmitter-receiver device of the present invention can connect one or more transmitting elements 1, relatively independent being independent of each other between the receiving element signal conversion module 21 of corresponding different transmitting elements 1, relatively independent being independent of each other between the receiving element signal condition module 22 of same corresponding different transmitting elements 1; The reception main control unit 23 of corresponding different transmitting element 1 can be present in a FPGA module jointly with modular form.Obviously, can expand number is determined by FPGA resource utilization and FPGA running status.In the present invention, when connecting a transmitting element, receiving element FPGA resource utilization is 6%, in the situation that operating temperature allows to carry out the decoding of sampling simultaneously of 6 groups of transmitting elements.
The number of active lanes of transmitting element data sampling and signal condition module 11 and sampling order are determined by the concrete model of employing A/D modular converter, the speed of institute's sampled signal and the rate request of system.Take typical three-phase VSI control system as example, the variable of required transmission has: the operating state signal of each switching tube gate electrode drive signals, each switching tube, the voltage and current signal of feedback.For gate electrode drive signals, the rise time of hypothesis driven signal is far smaller than switching frequency, and the minimal communications bandwidth that each switch needs can be approximately following formula:
In formula (1), f
swBe system switching frequency, n
dMaximal accuracy for pulse-width modulation (PWM) signal.Select n in example
d=12, f
sw=10kHz.The minimal communications bandwidth B that needs is 41Mbps.The driving signal is switching value, in transport process without data sampling and signal condition module and A/D modular converter, so its speed only is subjected to optical fiber to transmit limit bandwidth.Because the optical fiber communication bandwidth that adopts in example is 125Mbps, institute thinks the assurance communication capacity, preferably only sends the signal of a passage if transmitting switch drives each transmitting element.Be all the operating state signal of the switching tube of switching value, each switch periods only needs transmission primaries to get final product, in the situation that switching frequency much smaller than communication bandwidth, can be expanded in a large number.In addition, each switch periods also needs to feed back primary voltage and current sampling data at least to controller, and both speed is slower, and required channel capacity C can be represented by the formula:
C=N
noden
bf
sw （2）
In formula (2): C is channel capacity; n
bFigure place for every frame data; f
swIt is the system switching frequency; N
NodePort number for sampling unit.In the design, the length of every frame data is 25, and each transmitting element has 4 passages, i.e. n
b=4.The switching frequency of supposing the VSI system is 10kHz, and can calculate the minimum data channel capacity that needs is 1Mbps/s.Adopt the 125Mbps bandwidth for transmission in Experiment Platform Design, satisfy the requirement that 4 passages are sampled simultaneously far away.Owing to being the analog signal sampling, system speed also is limited by A/D conversion and transfer of data time-delay.If system's output waveform does not produce distortion, the transfer of data time-delay must be satisfied following formula:
t
d=T
sw/N
node （3）
T wherein
dBe A/D conversion and transfer of data time-delay, T
swThe system switching cycle.When frequency is 10kHz, switch periods T
sw=100us, as adopt 4 channel sample, transmission delay t
dShould be much smaller than 25us.Intelligent transmitting device time-delay of the present invention is 1.8us, the demand of adaptive system.Based on above analysis, the present invention has relatively high expectations for switching frequency and has applicable equally than the occasion of high dynamic response demand.
The present invention proposes a kind of Multichannel isolation high-speed intelligent transmitter-receiver device that is used for power electronic system of novelty, great advantage of the present invention is high-voltage isolating, and has Multitasking ability and the characteristics such as high reliability, real-time.Be applicable to the Complex Power electronic equipment, applicable too for other occasion that switching frequency and isolation Level are had relatively high expectations.
Above content is in conjunction with instantiation further description made for the present invention, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (5)
1. a Multichannel isolation high-speed intelligent transmitter-receiver device that is used for power electronic system, is characterized in that: comprise transmitting element (1), receiving element (2) and isolation transmission medium (4); Described transmitting element (1) comprises data sampling and signal condition module (11), A/D modular converter (12), sends main control unit (13) and transmitting element signal conversion module (14), and described transmission main control unit (13) comprises controlling of sampling module (131), data coding module (132) and check code implant module (133); Described receiving element (2) comprises receiving element signal conversion module (21), receiving element signal condition module (22), receives main control unit (23) and storage output module (24), and described reception main control unit (23) comprises Clock Extraction and synchronization module (231), initial order judge module (232), data decode module (233) reconciliation code check module (234); Described data sampling and signal condition module (11) are connected with the input of A/D modular converter (12), the output of A/D modular converter (12) is connected with control end and is connected with described controlling of sampling module (131), described controlling of sampling module (131) is connected with described check code implant module (133), described check code implant module (133) is connected with data coding module (132), and data coding module (132) is connected with described transmitting element signal conversion module (14); the input of described receiving element signal conversion module (21) is connected with transmitting element signal conversion module (14) by described isolation transmission medium (4), the output of described receiving element signal conversion module (21) is connected with the input of described receiving element signal condition module (22), output while and described Clock Extraction and the synchronization module (231) of described receiving element signal condition module (22), described initial order judge module (232) connects, output while and the described initial order judge module (232) of described Clock Extraction and synchronization module (231), described decoding correction verification module (234), described data decode module (233) connects, the output of described initial order judge module (232) is connected with the input of described data decode module (233), the output of described decoding correction verification module (234) is connected with the input of described data decode module (233), the output of described data decode module (233) is connected with described storage output module (24).
2. Multichannel isolation high-speed intelligent transmitter-receiver device according to claim 1 is characterized in that: described transmission main control unit (13) and receive main control unit (23) and be field programmable logic array.
3. Multichannel isolation high-speed intelligent transmitter-receiver device according to claim 1 and 2, it is characterized in that: the analog quantity sampling channel quantity of the data sampling of described transmitting element and signal condition module (11) is 1～4.
4. Multichannel isolation high-speed intelligent transmitter-receiver device according to claim 1 and 2, it is characterized in that: the switching value sampling channel quantity of described transmitting element is 1～3.
5. the Multichannel isolation high-speed intelligent transmitter-receiver device of a right to use requirement 1 carries out the method for data transmit-receive, it is characterized in that comprising the steps:
(1) gathered analog signals and sent to A/D modular converter (12) by data sampling and signal condition module (11), A/D modular converter (12) converts described analog signals to digital quantity signal and sends to controlling of sampling module (131); And/or
Gather the switching value signal by controlling of sampling module (131);
(2) controlling of sampling module (131) expands described switching value signal and/or received digital quantity signal so that the signal after expanding comprises beginning flag, address bit, data bit, switching value position and finishes flag; Signal after post-sampling control module (131) will be expanded sends to check code implant module (133);
(3) check code implant module (133) is implanted check digit to the signal after received expansion and is formed new Frame; Rear check code implant module (133) sends to data coding module (132) with described new Frame;
(4) data coding module (132) will convert the high-low level signal to from the new Frame that check code implant module (133) receive; Rear data coding module (132) sends to transmitting element signal conversion module (14) with described high-low level signal;
(5) transmitting element signal conversion module (14) sends in receiving element signal conversion module (21) by isolation transmission medium (4) after converting received high-low level signal to signal that corresponding isolation transmission medium (4) can support;
(6) receiving element signal conversion module (21) sends to receiving element signal condition module (22) after converting all received data-signals to the signal of telecommunication;
(7) described receiving element signal condition module (22) is being carried out the received signal of telecommunication to be converted to the TTL signal after the voltage magnitude coupling, and rear described receiving element signal condition module (22) sends to respectively Clock Extraction and synchronization module (231) and initial order judge module (232) with described TTL signal;
(8) described Clock Extraction and synchronization module (231) extract synchronizing clock signals from received TTL signal; Described Clock Extraction and synchronization module (231) send to decoding correction verification module (234) and initial order judge module (232) simultaneously with described synchronizing clock signals and TTL signal, and described Clock Extraction and synchronization module (231) send to described data decode module (233) with described synchronizing clock signals, and described initial order judge module (232) sends to described data decode module (233) after extracting initial order according to described synchronizing clock signals from received TTL signal; Described decoding correction verification module (234) carries out verification and check results and this TTL signal is sent to described data decode module (233) received TTL signal according to described synchronizing clock signals;
(9) described data decode module (233) is decoded to received TTL signal according to described initial order, synchronizing clock signals and described check results and is obtained address bit and data bit information in this TTL signal, and described address bit and data bit information are sent in the register of storage output module (24).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110083880 CN102158336B (en) | 2011-04-04 | 2011-04-04 | Multi-channel isolated high-speed intelligent transmitting-receiving device and method for power electronic system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110083880 CN102158336B (en) | 2011-04-04 | 2011-04-04 | Multi-channel isolated high-speed intelligent transmitting-receiving device and method for power electronic system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102158336A CN102158336A (en) | 2011-08-17 |
| CN102158336B true CN102158336B (en) | 2013-11-06 |
Family
ID=44439539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110083880 Expired - Fee Related CN102158336B (en) | 2011-04-04 | 2011-04-04 | Multi-channel isolated high-speed intelligent transmitting-receiving device and method for power electronic system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102158336B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102542785A (en) * | 2011-11-25 | 2012-07-04 | 中国船舶重工集团公司第七二四研究所 | Design and implementation method of multi-channel broadband electronic signal synchronous acquiring system |
| CN102548380A (en) * | 2012-01-06 | 2012-07-04 | 北京雍华和讯信息技术有限公司 | Electronic equipment and anti-interference method for same |
| CN103825696B (en) * | 2014-03-11 | 2017-08-01 | 华中科技大学 | A kind of device that high speed fibre real-time Communication for Power is realized based on FPGA |
| CN105048787A (en) * | 2015-06-09 | 2015-11-11 | 江苏镇安电力设备有限公司 | Fiber integrated communication method for multi-level cascading type high-voltage frequency converter |
| JP6361589B2 (en) * | 2015-06-11 | 2018-07-25 | 株式会社デンソー | Communications system |
| CN107276053B (en) * | 2017-07-13 | 2019-09-20 | 天津凯发电气股份有限公司 | A kind of equipment for protecting optical fibre longitudinal difference and method of data synchronization |
| CN110032126B (en) * | 2019-05-14 | 2024-03-05 | 哈尔滨理工大学 | Multichannel strain signal synchronous acquisition system and method |
| CN113179522A (en) * | 2021-03-31 | 2021-07-27 | 德氪微电子(深圳)有限公司 | Method and device for data transmission between unmanned aerial vehicle main body and suspension camera |
| CN113589020A (en) * | 2021-09-29 | 2021-11-02 | 湖北傲云电气有限公司 | Voltage-sharing measurement device and method for power device of high-isolation voltage-withstanding series circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885749A (en) * | 2006-05-18 | 2006-12-27 | 浙江大学 | Novel communication network topology structure for power electronic system |
| CN201004633Y (en) * | 2007-01-30 | 2008-01-09 | 深圳市共进电子有限公司 | A network adapter for power line communication |
| CN202034996U (en) * | 2011-04-04 | 2011-11-09 | 浙江大学 | Multichannel isolation high-speed intelligent transmitter-receiver device for power electronic systems |
-
2011
- 2011-04-04 CN CN 201110083880 patent/CN102158336B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885749A (en) * | 2006-05-18 | 2006-12-27 | 浙江大学 | Novel communication network topology structure for power electronic system |
| CN201004633Y (en) * | 2007-01-30 | 2008-01-09 | 深圳市共进电子有限公司 | A network adapter for power line communication |
| CN202034996U (en) * | 2011-04-04 | 2011-11-09 | 浙江大学 | Multichannel isolation high-speed intelligent transmitter-receiver device for power electronic systems |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102158336A (en) | 2011-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102158336B (en) | Multi-channel isolated high-speed intelligent transmitting-receiving device and method for power electronic system | |
| CN202034996U (en) | Multichannel isolation high-speed intelligent transmitter-receiver device for power electronic systems | |
| US9118392B2 (en) | Isolated serializer-deserializer | |
| EP2740235B1 (en) | Serial communication protocols | |
| US9369237B2 (en) | Run-length detection and correction | |
| US20150236844A1 (en) | Synchronization signal transmitting device, method thereof and power electronic apparatus having the device | |
| US10547438B2 (en) | Signal edge location encoding | |
| JP2012257035A (en) | Transceiver | |
| CN108631898A (en) | A kind of fiber optic serial data communications method | |
| CN106292409B (en) | Real-time simulation system based on FPGA multi-rate optical fiber communication and simulation method thereof | |
| CN108471303A (en) | Programmable nanosecond timing precision pulse generator based on FPGA | |
| CN102819282A (en) | Clock recovery circuit device and corresponding method | |
| CN105246186A (en) | LED drive chip output current accurate control technology | |
| CN108449086B (en) | Method and circuit for synchronizing parallel ports of multi-channel high-speed serial bus sending end | |
| CN100438350C (en) | Receiving circuit for receiving information signal | |
| CN102063401B (en) | TDMOW serial bus structure of distributed oscillograph and encoding method | |
| CN101814976A (en) | Multi-type network data transmission method and device | |
| CN110365710A (en) | Multi-protocols aggregation transfer device, system and method | |
| CN110780650A (en) | Communication bus protocol conversion method and system | |
| JPH07273675A (en) | Precoded waveform shaping transmitter | |
| CN201422114Y (en) | Error code rate test module based on PXI bus | |
| CN110266303A (en) | Refresh circuit, method, chip and data transmission system | |
| CN203406870U (en) | Coding and decoding system for optical fiber communication of controllable high-voltage paralleling reactor | |
| CN103401747A (en) | Distributed floating controller local area network communication system | |
| CN103051386A (en) | Communication realizing method and communication realizing system for chain type energy storage system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131106 Termination date: 20200404 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |