CN110266303A - Refresh circuit, method, chip and data transmission system - Google Patents
Refresh circuit, method, chip and data transmission system Download PDFInfo
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- CN110266303A CN110266303A CN201910647827.4A CN201910647827A CN110266303A CN 110266303 A CN110266303 A CN 110266303A CN 201910647827 A CN201910647827 A CN 201910647827A CN 110266303 A CN110266303 A CN 110266303A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application provides a kind of refresh circuit, method, chip and data transmission system, and refresh circuit includes: high-impedance state control circuit, pull-up refresh circuit, drop-down refresh circuit；The input terminal of high-impedance state control circuit is for receiving desired input signals；The output end of high-impedance state control circuit is connect with pull-up refresh circuit；The output end of high-impedance state control circuit is also connect with drop-down refresh circuit；The output end of high-impedance state control circuit also passes through an isolating device and connect with external receiver；Wherein, it remains unchanged in preset duration in the logic state of desired input signals, and the output of high-impedance state control circuit be high-impedance state when, pull-up refresh circuit is pulled up according to output signal of the desired input signals to high-impedance state control circuit, or, drop-down refresh circuit is pulled down according to output signal of the desired input signals to high-impedance state control circuit, to obtain refresh signal.
Description
Technical field
This application involves data isolation transmission fields, in particular to a kind of refresh circuit, method, chip and data
Transmission system.
Background technique
Digital isolator can transmit signal and then the edge to input signal carries out encoding and decoding, the signal after coding
Frequency component with higher is easier across the isolation barrier formed by isolating device, to realize with high voltage
Signal transmitting is carried out between the circuit of difference.
But in traditional transmission process, the receiving end of system is difficult to after obtaining error signal because of emergency case
Restore in time normal.
Summary of the invention
The embodiment of the present application is designed to provide a kind of refresh circuit, method, chip and data transmission system, to change
The receiving end of kind system in the prior art is difficult to restore in time normal problem after obtaining error signal because of emergency case.
In a first aspect, the embodiment of the present application provides a kind of refresh circuit, the refresh circuit include high-impedance state control circuit, on
Draw refresh circuit, drop-down refresh circuit；
The input terminal of the high-impedance state control circuit is for receiving desired input signals, the logic of the desired input signals
State is the first logic or the second logic, and the second logic described in first logical AND is opposite logic state；
The output end of the high-impedance state control circuit is connect with the pull-up refresh circuit；
The output end of the high-impedance state control circuit is also connect with the drop-down refresh circuit；
The output end of the high-impedance state control circuit also passes through an isolating device and connect with external receiver；
Wherein, it remains unchanged in preset duration in the logic state of the desired input signals, and the high-impedance state control
When the output of circuit processed is high-impedance state, the pull-up refresh circuit controls electricity to the high-impedance state according to the desired input signals
The output signal on road is pulled up, or, the drop-down refresh circuit controls the high-impedance state according to the desired input signals
The output signal of circuit is pulled down, to obtain refresh signal.
By above-mentioned refresh circuit, since high-impedance state refresh circuit can be pulled up refreshing in the case where exporting high-impedance state
Circuit is pulled up or is pulled down refresh circuit and pulled down, and can complete the refresh activity under high-impedance state with this.This makes
When the logic state of desired input signals remains unchanged whithin a period of time, refresh circuit can be under high-impedance state to receiver
Refresh signal is sent, so that receiving end can carry out in time data correction according to the refresh signal of refresh circuit, restore.
With reference to first aspect, in a kind of possible design, the high-impedance state control circuit includes the first delayer, refreshes
Controller, high-impedance state control module；
First delayer is believed for generating the first delay by the first delay according to the desired input signals
Number；The refresh controller refreshes enable signal for exporting according to the desired input signals；The high-impedance state controls mould
Block, for exporting high-impedance state according to first time delayed signal and the refreshing enable signal.
By above structure, can obtain refreshing enable signal based on desired input signals, high-impedance state control module can root
According to enable signal and the first time delayed signal output high-impedance state is refreshed, a kind of refresh circuit of exportable high-impedance state is obtained.
With reference to first aspect, in a kind of possible design, the high-impedance state control module includes the first logic circuit, the
Two logic circuits, target phase inverter；
First logic circuit is used to export the first reverse phase according to first time delayed signal, the refreshing enable signal
Control signal；Second logic circuit is used for anti-according to first time delayed signal, refreshing enable signal output second
Phase control signal；The target phase inverter is used for defeated according to first inverted control signal, second inverted control signal
High-impedance state out.
A kind of possible implementation of high-impedance state control circuit is given by above structure, target can be allowed anti-with this
Phase device is based on the first time delayed signal, refreshes both signals of enable signal output high-impedance state.
With reference to first aspect, in a kind of possible design, the target phase inverter includes the first PMOS tube, the first NMOS
Pipe；
The grid of first PMOS tube is connect with first logic circuit, and the source electrode of first PMOS tube connects electricity
The drain electrode in source, first PMOS tube is connect with the drain electrode of first NMOS tube；The grid of first NMOS tube with it is described
The connection of second logic circuit, the source electrode ground connection of first NMOS tube.
Pullup or pulldown is allowed to refresh electricity in the case where high-impedance state control circuit exports high-impedance state by above structure
Road carries out linear-charging or electric discharge to the output node of target phase inverter, obtains refresh signal.
With reference to first aspect, in a kind of possible design, the pull-up refresh circuit includes the first current mirror, pull-up control
Circuit processed；
Two input terminals of the pull-up control circuit, which are respectively used to receive, refreshes enable signal, target input letter
Number；The output end of the pull-up control circuit is connect with first current mirror；First current mirror is used for the high resistant
The output end of state control circuit carries out linear-charging.
By above structure, being switched on or off for the first current mirror can be controlled by pull-up control circuit, in the first electricity
When flowing mirror unlatching, linear-charging is carried out to the output end of high-impedance state control circuit.
With reference to first aspect, in a kind of possible design, the pull-up control circuit includes third logic circuit, pull-up
Switching tube；The control terminal of the pull-up switch pipe is connect with the output end of the third logic circuit, the pull-up switch pipe
Output end is connect with first current mirror；The third logic circuit, for being the second logic in the desired input signals
And the refreshing enable signal be the first logic when, output logic state be the second logic pull-up refresh control signal；It is described
Third logic circuit is also used to, and is patrolled in non-second logic of the desired input signals and/or the refreshing enable signal non-first
When collecting, output logic state is the pull-up refresh control signal of the first logic.
A kind of possible structure for pulling up refresh circuit is provided by above structure, is exported by third logic circuit upper
The on or off for drawing refresh control signal control pull-up switch pipe, in the conducting of pull-up switch pipe, the first current mirror is opened, and is
The output end of high-impedance state control circuit carries out linear-charging, and fast-changing signal edge can be formed after charging.
With reference to first aspect, in a kind of possible design, the drop-down refresh circuit includes the second current mirror, drop-down control
Circuit processed；Two input terminals of the pull-down control circuit, which are respectively used to receive, refreshes enable signal, the desired input signals；
The output end of the pull-down control circuit is connect with second current mirror；Second current mirror is used for the high-impedance state control
The output end of circuit processed carries out linear discharge.
By above structure, drop-down processing can be carried out to high-impedance state control circuit according to the drop-down refresh circuit,
Obtain refresh signal.
With reference to first aspect, in a kind of possible design, the pull-down control circuit includes the 4th logic circuit, drop-down
Switching tube；The control terminal of the pipe that pulls down switch is connect with the output end of the 4th logic circuit, the pipe that pulls down switch
Output end is connect with second current mirror；4th logic circuit, for being the first logic in the desired input signals
And the refreshing enable signal be the first logic when, output logic state be the first logic drop-down refresh control signal；It is described
4th logic circuit is also used to, and is patrolled in non-first logic of the desired input signals and/or the refreshing enable signal non-first
When collecting, output logic state is the drop-down refresh control signal of the second logic.
A kind of possible realization structure of drop-down refresh circuit is provided by above structure.
Second aspect, the embodiment of the present application provide a kind of method for refreshing, are applied to updating system, and the updating system includes
Transmitter, receiver are connected between the transmitter and the receiver by isolating device, and the transmitter includes aforementioned the
Refresh circuit described in one side, the method for refreshing include:
The transmitter receives desired input signals, and the logic state of the desired input signals is the first logic or second
Logic, the second logic described in first logical AND are opposite logic state；
The transmitter is when the logic state of the desired input signals remains unchanged in preset duration, in the brush
Novel circuit is to carry out pullup or pulldown processing according to the desired input signals by the refresh circuit under high-impedance state, is brushed
New signal；
The receiver receives the refresh signal by the isolating device；
The receiver is parsed according to the refresh signal, is confirmed signal.
By the above method, can desired input signals logic state it is constant whithin a period of time or data transfer rate is low
When, the refresh activity under high-impedance state is completed, refresh signal is obtained, so that receiver receives refresh signal by isolating device,
And signal is confirmed based on refresh signal parsing.Even if there is accident or system by dry in the partial circuit of transmitter side
It disturbs, receiver side can also be reacted according to refresh signal, to carry out subsequent data correction, recovery.
In conjunction with second aspect, in a kind of possible design, the refresh circuit includes: high-impedance state control circuit, pull-up
Refresh circuit, drop-down refresh circuit；The high-impedance state control circuit includes for generating the refresh controller for refreshing enable signal；
Pullup or pulldown processing is carried out to the desired input signals by the refresh circuit in the case where the refresh circuit is high-impedance state,
The step of obtaining refresh signal, comprising:
When the refresh circuit is high-impedance state, the pull-up refresh circuit is the second logic in the desired input signals
And the refreshing enable signal obtains refresh signal to carry out pull-up processing when the first logic.
Or, the drop-down refresh circuit is first in the desired input signals when the refresh circuit is high-impedance state
Logic and the refreshing enable signal carry out drop-down processing when being the first logic, obtain refresh signal.
A kind of logic state progress based on desired input signals, refreshing enable signal is provided by above-mentioned implementation
Pull-up processing or drop-down processing, in a manner of obtaining refresh signal.
In conjunction with second aspect, in a kind of possible design, high-impedance state control circuit in the refresh circuit includes the
One delayer, refresh controller, the first logic circuit, the second logic circuit, target phase inverter；
The high-impedance state of the refresh circuit is obtained by following manner:
The refresh controller is according to the desired input signals to first logic circuit and second logic
Circuit, which is sent, refreshes enable signal；First delayer according to the desired input signals to first logic circuit and
Second logic circuit sends the first time delayed signal；First logic circuit is according to the refreshing enable signal, described
One time delayed signal exports the first inverted control signal, and, second logic circuit is according to the refreshing enable signal, described
First time delayed signal exports the second inverted control signal；The target phase inverter receives first inverted control signal and described
Second inverted control signal, and high-impedance state is exported according to first inverted control signal, second inverted control signal；
Wherein, when the refreshing enable signal is the first logic, the first reverse phase that first logic circuit is exported
The logic state for controlling signal is the second logic, the logic shape for the first inverted control signal that second logic circuit is exported
State is the first logic；When the refreshing enable signal is the second logic, first inverted control signal, second reverse phase
The logic state for controlling signal is identical, and the logic state of first inverted control signal, second inverted control signal
It is determined according to the desired input signals.
In such a way that above-mentioned implementation provides a kind of output of realization high-impedance state.
In conjunction with second aspect, in a kind of possible design, patrolling for the refreshing enable signal is determined in the following manner
The state of collecting:
The refresh controller will periodically refresh patrolling for enable signal when the desired input signals remain unchanged
The state of collecting is restored after being converted to the first logic to the second logic.
The time for executing refresh activity is capable of determining that with this.
The third aspect, the embodiment of the present application provide a kind of chip, which includes the electricity of refreshing described in aforementioned first aspect
Road.
Fourth aspect, the embodiment of the present application provide a kind of data transmission system, the data transmission system include transmitter,
Receiver；The transmitter includes refresh circuit described in aforementioned first aspect；Lead between the transmitter and the receiver
Cross isolating device connection.
By above-mentioned data transmission system, transmitter can use refresh circuit and send refresh signal to receiver, receive
Device can be received refresh signal by isolating device and carry out subsequent dissection process.Even if two adjacent edges of input signal are along letter
Number interval time it is long, receiver side also can carry out data validation based on refresh signal, and then in time to some fortuitous events
Caused error in data is corrected, is restored.
In conjunction with fourth aspect, in a kind of possible design, the isolating device is isolation capacitance.
It can use isolation capacitance as the transmission medium between transmitter and receiver using this, receiver can be by isolation
Capacitor identifies refresh signal.
Detailed description of the invention
Technical solution in ord to more clearly illustrate embodiments of the present application will make below to required in the embodiment of the present application
Attached drawing is briefly described, it should be understood that the following drawings illustrates only some embodiments of the application, therefore should not be seen
Work is the restriction to range, for those of ordinary skill in the art, without creative efforts, can be with
Other relevant attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of schematic diagram of refresh circuit provided by the embodiments of the present application.
Fig. 2 is the schematic diagram of another refresh circuit provided by the embodiments of the present application.
Fig. 3 is a kind of schematic diagram for pulling up refresh circuit provided by the embodiments of the present application.
Fig. 4 is a kind of schematic diagram for pulling down refresh circuit provided by the embodiments of the present application.
Fig. 5 is the schematic diagram of the refresh circuit in an example provided by the embodiments of the present application.
Fig. 6 is the waveform diagram that refresh circuit provided by the embodiments of the present application executes refresh activity.
Fig. 7 is the refreshing waveform diagram that the corresponding signal of waveform shown in Fig. 6 obtains after isolating device.
Fig. 8 is a kind of operation principle schematic diagram of refresh circuit provided by the embodiments of the present application.
Fig. 9 is a kind of flow chart of method for refreshing provided by the embodiments of the present application.
Figure 10 is a kind of schematic diagram of updating system provided by the embodiments of the present application.
Icon: 10- data transmission system；100- transmitter；110- high-impedance state control circuit；The first delayer of 111-；
112- refresh controller；113- high-impedance state control module；The first logic circuit of 1131-；The second logic circuit of 1132-；1133- mesh
Mark phase inverter；The first PMOS tube of P1-；The first NMOS tube of N1-；120- pulls up refresh circuit；1201- charge switch；1202- first
Constant current source；The first current mirror of 121-；122- pull-up control circuit；1221- third logic circuit；The second PMOS tube of P2-；
P3- third PMOS tube；P4- pull-up switch pipe；The first current source of U1-；130- pulls down refresh circuit；1301- discharge switch；
The second constant current source of 1302-；The second current mirror of 131-；132- pull-down control circuit；The 4th logic circuit of 1321-；N2- second
NMOS tube；N3- third NMOS tube；N4- pulls down switch pipe；The second current source of U2-；200- isolating device；201- first capacitor；
202- first resistor；300- receiver.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application is described.
Inventor has found that in existing digital isolation applications being carried out by the edge to input signal
Encoding and decoding are to transmit signal.It is simple in the prior art to carry out the mode that encoding and decoding carry out signal transmission by signal edge,
It is easy to appear following two aspects problem:
One, when the data transfer rate of input signal is very low, two adjacent signal edges interval time is very long, and receiver is solving
After code goes out a signal edge, it may be necessary to be lot more time to be resolved to next signal edge, complete to believe input with this
Number decoding.And in practical application scene, if by external interference mistake is occurred for whole system, receiver needs long after
" the next signal edge " of real input signal can just be received and parsed.This makes the data transfer rate in input signal
When very low, receiver side needs long time just to can be carried out data correction.
If two, the partial circuit of transmitter side occurs fortuitous event (such as power-off) in system, receiver side without
Method learns the exception of transmitter side in time, it is difficult to react in time to ensure the safety of whole system.
Therefore, following embodiment is inventors herein proposed to improve drawbacks described above, and the transmitter side of system is existed
Before " the next signal edge " of input signal arrives, the refresh signal for being confirmed, receiver are sent to receiver
Side can be confirmed signal according to refresh signal before " the next signal edge " for receiving real input signal.
Even if something unexpected happened, receiver side also can be corrected or be restored according to refresh signal in time.
Scheme for ease of understanding below will explain some nouns in the application.
High-impedance state: a kind of output state of some node in indication circuit or circuit, neither high level is also not low electricity
It is flat.When carrying out circuit analysis, influence of the high-impedance state to late-class circuit is low, the high-impedance state under extreme case can be regarded as open circuit or
Vacantly.
It should be noted that can be combined with each other and use for reference between following embodiment.
First embodiment
Referring to Fig. 1, Fig. 1 is a kind of schematic diagram of refresh circuit provided by the embodiments of the present application.The refresh circuit can be with
It is arranged at the transmitting terminal (or transmitter 100, transmitter) of data transmission system 10.
As shown in Figure 1, refresh circuit includes high-impedance state control circuit 110, pull-up refresh circuit 120, drop-down refresh circuit
130。
The input terminal of high-impedance state control circuit 110 is for receiving desired input signals a, the logic shape of desired input signals a
State is the first logic or the second logic, and the second logic described in first logical AND is opposite logic state.
The output end of high-impedance state control circuit 110 is connect with pull-up refresh circuit 120.High-impedance state control circuit 110 it is defeated
Outlet is also connect with drop-down refresh circuit 130.
The output end of high-impedance state control circuit 110 also passes through an isolating device 200 and connect with external receiver 300.Isolation
Device 200 can be isolation capacitance.The one end of isolation capacitance far from high-impedance state control circuit 110 can be connect with filtering unit,
Filtering unit includes first capacitor 201 in parallel, first resistor 202.
Wherein, it remains unchanged in preset duration in the logic state of the desired input signals a, and high-impedance state control electricity
When the output on road 110 is high-impedance state, refresh circuit 120 is pulled up according to desired input signals a to the defeated of high-impedance state control circuit 110
Signal is pulled up out, or, drop-down refresh circuit 130 believes the output of high-impedance state control circuit 110 according to desired input signals a
It number is pulled down, to obtain refresh signal.
Preset duration may be related with the internal delay time in high-impedance state control circuit 110, and those skilled in the art can basis
Actual demand sets preset duration.
Illustratively, the first logic can indicate logical zero (or low level), the second logic can indicate logic 1 (or
High level).Wherein, those skilled in the art can realize same function by digital logical operation with opposite logic, because
This, specific logic state selection should not be construed as the limitation to the application.
As a kind of implementation, high-impedance state control circuit 110 can be a kind of spy with delay function, ena-bung function
Different phase inverter.Pull-up refresh circuit 120 or drop-down refresh circuit 130 can control high-impedance state control circuit in refresh process
110 output end waveform slope remains invariable, for example, can be by the first constant current source 1202 in Fig. 1 to high-impedance state
The output end of control circuit 110 charges, or is discharged by the second constant current source 1302 in Fig. 1.Constant current
Source can be adjusted by the reference current source of integrated circuit in the form of current mirror to the size of current realization of setting.Constant current source
Charging process can be controlled by charge switch 1201, the discharge process of constant current source can be controlled by discharge switch 1301.
Pull-up refresh circuit 120, the structure for pulling down refresh circuit 130 are similar, and pullup/pulldown refresh circuit 130 can be right
The output end of high-impedance state control circuit 110 carries out slow charge/discharge, to realize that pullup/pulldown operates, grasps through pullup/pulldown
The signal for making to obtain can be considered as initial refresh signal c.Initial refresh signal c can be exchanged into after isolating device 200 can
The pre- refresh signal d identified by receiver 300, receiver 300 can be decoded the signal edge of pre- refresh signal d to obtain
To confirmation signal.
For ease of description, initial refresh signal c and pre- refresh signal d are referred to as refresh signal, the difference of the two below
The effect for whether passing through isolating device 200 be only that, the waveform of the waveform of initial refresh signal c and pre- refresh signal d are in slope
Upper presentation is positively correlated.
By above-mentioned refresh circuit, high-impedance state refresh circuit can be pulled up refresh circuit in the case where exporting high-impedance state
120, which are pulled up or be pulled down refresh circuit 130, is pulled down, and can complete the refresh activity under high-impedance state with this.This makes
When the logic state of desired input signals a remains unchanged whithin a period of time, refresh circuit can be under high-impedance state to connecing
It receives device 300 and sends refresh signal.Receiver 300 can be on " the next signal side for not receiving real desired input signals a
Refresh signal is received before edge " (before desired input signals a changes), and then is obtained according to the signal edge of refresh signal
To confirmation signal, data validation or correction are realized in advance.
On the one hand, the circuit under high-impedance state can allow influence of the transmitting terminal to receiving end to reduce, even if transmitting terminal side
Partial circuit powered off due to unexpected, it is different that 300 side of receiver also can learn that transmitting terminal occurs according to refresh signal in time
Often.On the other hand, even if the data transfer rate of input signal is low, two adjacent signal edges interval time of input signal is very long,
In the case where system causes interference to receiving end because of external interference, receiving end also according to the refresh signal of refresh circuit and
Shi Jinhang data correction restores.
Optionally, as shown in Figure 1, high-impedance state control circuit 110 may include: the first delayer 111, refresh controller
112, high-impedance state control module 113.
First delayer 111, for generating the first time delayed signal by the first delay D1 according to desired input signals a
a1。
Refresh controller 112 refreshes enable signal b for exporting according to desired input signals a.
High-impedance state control module 113, for exporting high-impedance state according to the first time delayed signal a1 and refreshing enable signal b.
Under normal conditions, the logic circuit inside refresh controller 112 there may be second delay D2, but first delay D1
With the second delay D2 all very littles, the work of system is had no significant effect.
Under some specific application scenes, such as in the working time sufficiently long situation of system, it is possible that brush
The phenomenon that newly process is Chong Die with the effective edge of desired input signals a edge, i.e., when the effective edge of desired input signals a is along appearance
The case where at quarter, system is carrying out refresh operation.It, can be in order to improve refreshing accuracy rate for specific application scene above-mentioned
Be arranged the first logic circuit 1131 receive refresh enable signal b time can earlier than receive the first time delayed signal a1 when
Between.For example, the duration of the first delay D1 can be increased by way of increasing delayer, so that the of refresh controller 112
Two delay D2 are smaller than the duration of the first delay D1.
In other instances, it may not be necessary to which the delay restrictive condition that D1 > D2 is arranged also is able to achieve refreshing.
It can obtain refreshing enable signal b, high resistant based on desired input signals a by above-mentioned high-impedance state control circuit 110
State control module 113 can export high-impedance state according to enable signal b and the first time delayed signal a1 is refreshed, and realize by hardware circuit
Refresh and is better able to suitable for complicated operating condition.
Wherein, the refreshing enable signal b be in addition to that can be sent into high-impedance state control module 113 to export high-impedance state, can be with
It is admitted to pull-up refresh circuit 120 and drop-down refresh circuit 130, so that pull-up refresh circuit 120 can be according to desired input signals a
And refreshes enable signal b and linear slowly charging is carried out to the output node of high-impedance state control circuit 110, or drop-down is made to refresh electricity
Road 130 can carry out line according to output node of the desired input signals a and refreshing enable signal b to high-impedance state control circuit 110
Property is slowly discharged, to realize refreshing, obtains refresh signal.
As an implementation, logic state can be determined in the following manner by refreshing enable signal b:
Refresh controller 112 will periodically refresh enable signal b's when the desired input signals a remains unchanged
Logic state transition is recovery after the first logic to the second logic.
The logic state transition for refreshing enable signal b is the when desired input signals a changes by refresh controller 112
Two logics.
Change principle based on the aforementioned logic state for refreshing enable signal b, no matter the logic state of desired input signals a is
No change, refresh controller 112, which can generate, refreshes enable signal b, and only logic state will be different.
The refreshing enable signal b and desired input signals a exported by aforementioned refresh controller 112, can determine
Execute the time of refresh activity.In an example, " the second logic-the can be occurred into the logic state of refresh control signal
This stage of one the-the second logic of logic " is as the stage for executing refresh activity.
As a kind of implementation, as shown in Fig. 2, high-impedance state control module 113 may include the first logic circuit 1131,
Second logic circuit 1132, target phase inverter 1133.
First logic circuit 1131, for exporting the control of the first reverse phase according to the first time delayed signal a1, refreshing enable signal b
Signal f.
Second logic circuit 1132, for exporting the control of the second reverse phase according to the first time delayed signal a1, refreshing enable signal b
Signal g.
Target phase inverter 1133, for exporting high-impedance state according to the first inverted control signal f, the second inverted control signal g.
Multiple drivers can be set to enhance the response of target phase inverter 1133 in the input terminal of target phase inverter 1133
Speed.
Wherein, for the first logic circuit 1131, the second logic circuit 1132:
When refreshing enable signal b is the first logic, the first inverted control signal f that the first logic circuit 1131 is exported
Logic state be the second logic, the logic state of the first inverted control signal f that the second logic circuit 1132 is exported is the
One logic.
When refreshing enable signal b is the second logic, the logic of the first inverted control signal f, the second inverted control signal g
State is identical, and the logic state of the first inverted control signal f, the second inverted control signal g are according to the desired input signals a
It determines.For example, the first inverted control signal f, the second inverted control signal g are patrolled when refreshing enable signal b is the second logic
The state of collecting can be identical as the logic state of desired input signals a.
Target phase inverter 1133 can be allowed to be based on two kinds of signals with this and export high-impedance state.
In order to realize above-mentioned principle, in an example, the specific structure of high-impedance state control circuit 110 can be such as Fig. 5 institute
Show.As shown in figure 5, the first logic circuit 1131 may include NOT gate or door, refresh enable signal b after NOT gate carries out reverse phase,
It is inputted jointly with desired input signals a or door, to obtain the first inverted control signal f.Second logic circuit 1132 may include one
With door, refreshing enable signal b and desired input signals a is inputted jointly and door, to obtain the second inverted control signal g.
Due to the equivalent replacement mode of digital logic device be it is various, in some instances, those skilled in the art can
To build the first logic circuit 1131, the second logic circuit 1132 using the device of other forms.
As shown in Fig. 2, target phase inverter 1133 may include the first PMOS tube P1 (P-channel type metal-oxide-partly lead
Body field effect transistor, abbreviation PMOS tube), the first NMOS tube N1 (N-channel type Metal-oxide-semicondutor field effect transistor
Pipe, abbreviation NMOS tube).
The grid of first PMOS tube P1 is connect with the first logic circuit 1131, and the source electrode of the first PMOS tube P1 connects power supply, the
The drain electrode of one PMOS tube P1 is connect with the drain electrode of the first NMOS tube N1.
The grid of first NMOS tube N1 is connect with the second logic circuit 1132, the source electrode ground connection of the first NMOS tube N1.
It can be exported according to the first logic circuit 1131, the second logic circuit 1132 by above-mentioned target phase inverter 1133
Signal exports high-impedance state, that is, realizes the first NMOS tube N1 and the first PMOS tube P1 while the state being off.And in target
In the case that phase inverter 1133 exports high-impedance state, allow pullup/pulldown refresh circuit 130 to the output section of target phase inverter 1133
Point (drain electrode and the drain electrode of the first NMOS tube N1 of the first PMOS tube P1) carries out linear slow charge/discharge, obtains refresh signal.
Since output node is in high-impedance state, which cannot obtain effective charge supplement from ground or power supply, so only needing very
Small charging and discharging currents can effectively adjust the voltage of the node, so that the energy consumption of refresh process is very low.
As shown in figure 3, pull-up refresh circuit 120 may include the first current mirror 121, pull-up control circuit 122.
Two input terminals of pull-up control circuit 122, which are respectively used to receive, refreshes enable signal b, desired input signals a.
The output end of pull-up control circuit 122 is connect with the first current mirror 121.
First current mirror 121 carries out linear-charging for the output end to high-impedance state control circuit 110.
Pull-up control circuit 122 can be used as the control switch of the first current mirror 121, and pull-up control circuit 122 can root
It is opened or closed according to enable signal b, desired input signals a the first current mirror 121 of control is refreshed.When first current mirror 121 is opened,
It charges to the output end of high-impedance state control circuit 110.
First current mirror 121 may include the second PMOS tube P2, third PMOS tube P3.
The source electrode of second PMOS tube P2 connects power supply, the drain electrode of the second PMOS tube P2 and the output of high-impedance state control circuit 110
End connection, the grid of the second PMOS tube P2 connect with the grid of third PMOS tube P3, also connect with the first current source U1.Third
The source electrode of PMOS tube P3 connects power supply, and the drain electrode of third PMOS tube P3, grid are connect with the first current source U1.
When the first current mirror 121 is opened, output of the second PMOS tube P2 with constant current to high-impedance state control circuit 110
End is charged, so that the output voltage of high-impedance state control circuit 110 linearly slowly rises.
Optionally, pull-up control circuit 122 may include third logic circuit 1221, pull-up switch pipe P4.
The control terminal of pull-up switch pipe P4 is connect with the output end of third logic circuit 1221, the output of pull-up switch pipe P4
End is connect with the first current mirror 121.
Third logic circuit 1221, for being the second logic in desired input signals a and to refresh enable signal b be first to patrol
When collecting, output logic state is the pull-up refresh control signal e1 of the second logic；
Third logic circuit 1221 is also used to, non-in non-second logic of desired input signals a, and/or refreshing enable signal b
When the first logic, output logic state is the pull-up refresh control signal e1 of the first logic.
There are many specific implementations of third logic circuit 1221.In one implementation, third logic circuit
1221 may include NOT gate and door.Refresh enable signal b to input jointly with desired input signals a and door behind the door by non-, obtain
Pull up refresh control signal e1.In other implementations, NOT gate can be combined with door by other fundamental digital logical devices
It obtains.
Pull-up switch pipe P4 can be the 4th PMOS tube, the switch as the first current mirror 121.The source electrode of 4th PMOS tube
Power supply is connect, drain electrode is connect with the first current source U1, and grid is connect with the output end of third logic circuit 1221.
Wherein, when the logic state for pulling up refresh control signal e1 is the second logic, the first current mirror 121 is opened, right
The output end of high-impedance state control circuit 110 carries out linear slowly charging.When the logic state of pull-up refresh control signal e1 is the
When one logic, the shutdown of the first current mirror 121, the no longer voltage of the output end of control high-impedance state control circuit 110.Pass through above-mentioned reality
Existing process, the pull-up refresh control signal e1 exported by third logic circuit 1221 control conducting or the pass of pull-up switch pipe P4
Disconnected, in pull-up switch pipe P4 conducting, the first current mirror 121 is opened, and is that the output end progress of high-impedance state control circuit 110 is linear
Charging, can form fast-changing signal edge after charging.
In an example, refresh to realize, and if only if desired input signals a be logic 1 and refreshing enable signal b is
When logical zero, pull-up refresh control signal e1 is logic 1, that is, is met: pull-up refresh control signal e1=(NOT b) AND a.
Optionally, as shown in figure 4, drop-down refresh circuit 130 can be similar with pull-up 120 structure of refresh circuit.Drop-down brush
Novel circuit 130 may include the second current mirror 131, pull-down control circuit 132.
Two input terminals of pull-down control circuit 132, which are respectively used to receive, refreshes enable signal b, desired input signals a.Under
The output end of control circuit 132 is drawn to connect with the second current mirror 131.
Second current mirror 131 is used to carry out linear discharge to the output end of high-impedance state control circuit 110.
Pull-down control circuit 132 can be used as the control switch of the second current mirror 131, and pull-down control circuit 132 can root
It is opened or closed according to enable signal b, desired input signals a the second current mirror 131 of control is refreshed.When second current mirror 131 is opened,
It discharges the output end of high-impedance state control circuit 110.
Second current mirror 131 may include the second NMOS tube N2, third NMOS tube N3.
The source electrode of second NMOS tube N2 is grounded, the drain electrode of the second NMOS tube N2 and the output end of high-impedance state control circuit 110
Connection, the grid of the second NMOS tube N2 connect with the grid of third NMOS tube N3, also connect with the second current source U2.3rd NMOS
The source electrode of pipe N3 is grounded, and the drain electrode of third NMOS tube N3, grid are connect with the second current source U2.
When the second current mirror 131 is opened, output of the second NMOS tube N2 with constant current to high-impedance state control circuit 110
End is discharged, so that the output voltage of high-impedance state control circuit 110 linearly slowly declines.
Optionally, pull-down control circuit 132 may include the 4th logic circuit 1321, pull down switch pipe N4.It pulls down switch
The control terminal of pipe N4 is connect with the output end of the 4th logic circuit 1321, the output end and the second current mirror of the pipe N4 that pulls down switch
131 connections.
4th logic circuit 1321, for being the first logic in desired input signals a and to refresh enable signal b be first to patrol
When collecting, output logic state is the drop-down refresh control signal e2 of the first logic.
4th logic circuit 1321 is also used to, non-in non-first logic of desired input signals a, and/or refreshing enable signal b
When the first logic, output logic state is the drop-down refresh control signal e2 of the second logic.
As a kind of way of realization of the 4th logic circuit 1321, the 4th logic circuit 1321 can be one or.Brush
New enable signal b and desired input signals a inputs this or door jointly, obtains drop-down refresh control signal e2.In other realization sides
In formula or door can be combined to obtain by other fundamental digital logical devices, such as can be according to the combination of NAND gate to realize
Or the function of door.
The pipe N4 that pulls down switch can be the 4th NMOS tube, the switch as the second current mirror 131.The source electrode of 4th NMOS tube
Ground connection, drain electrode are connect with the second current source U2, and grid is connect with the output end of the 4th logic circuit 1321.
Wherein, when the logic state for pulling down refresh control signal e2 is the first logic, the second current mirror 131 is opened, right
The output end of high-impedance state control circuit 110 carries out linear slowly electric discharge.When the logic state of drop-down refresh control signal e2 is the
When two logics, the shutdown of the second current mirror 131, the no longer voltage of the output end of control high-impedance state control circuit 110.
In an example, refresh to realize, and if only if desired input signals a be logical zero and refreshing enable signal b is
When logical zero, drop-down refresh control signal e2 is logical zero, that is, is met: drop-down refresh control signal e2=a OR b.
It is introduced below in conjunction with working principle of the Fig. 5 to aforementioned refresh circuit.
In refresh circuit shown in Fig. 5, high-impedance state control circuit 110 may include for receiving desired input signals a
Input port, and the output port for sending initial refresh signal c to isolating device 200 further includes one for connecing
Receive the enable port for refreshing enable signal b.
When the refreshing enable signal b that enable port receives is the first logic, the grid voltage of the first PMOS tube P1 is
The corresponding voltage of logic 1 (such as can be supply voltage), the grid voltage of the first NMOS tube N1 are the corresponding voltage of logical zero
(such as the corresponding voltage of earth signal).When the refreshing enable signal b that enable port receives is the second logic, the first PMOS tube
The grid voltage logic state having the same of the grid voltage of P1 and the first NMOS tube N1, for example, with desired input signals a's
Logic state is identical.Pass through the first logic circuit 1131, the second logic circuit 1132, the first PMOS tube P1, the first NMOS tube N1
Mating connection relationship, can allow the first PMOS tube P1, the first NMOS tube N1 formed target phase inverter 1133 export high-impedance state.
In the case where exporting high-impedance state, for the above pulling process is refreshed, the detailed process of pulling operation be can refer to
The description of pull-up process.The third logic circuit 1221 pulled up in refresh circuit 120 is inputted according to refreshing enable signal b, target
Signal a sends pull-up refresh control signal e1 to the second PMOS tube P2.When pulling up refresh control signal e1 is logic 1, first
Current mirror 121 is opened, to carry out linear slowly charging to the output node of target phase inverter 1133.In charging process, high-impedance state
The signal waveform slope of 110 output end of control circuit is constant, such as the waveform " 1. " in Fig. 6.It, can be with after the completion of refresh activity
Obtain initial refresh signal c, in corresponding waveform such as Fig. 6 1. (linear) and 4. (rapid decrease edge).Initial refresh signal c is sent
After entering isolating device 200, in the available pre- refresh signal d in the one end of isolating device 200 far from high-impedance state control circuit 110,
The waveform of pre- refresh signal d is as shown in Figure 7.
In practical application scene, the output end voltage of high-impedance state control circuit 110 rises to this mistake of logic 1 from logical zero
Journey, which changes over time, may correspond to three kinds of waveforms, as in Fig. 6 1., 2., 3..Wherein, the convex waveform in Fig. 6 2., recessed wave
3. shape may be linear-charging effect difference or not using caused by linear-charging.For convex waveform 2., recessed waveform 3.,
In waveform shown in Fig. 7 available after isolating device 200.Wherein, " 511 ", " 512 " corresponding dotted line indicate receiver
Signal threshold value set by comparator in 300.If convex waveform 2., the extreme value of recessed waveform 3. reach the letter in comparator
Number threshold value, it is possible that false triggering, allows receiver more than 300 to be resolved to a signal edge to influence to refresh accuracy rate.Cause
This refreshes accuracy rate to improve, and those skilled in the art can be modified the signal threshold value in comparator, or select as far as possible
Selecting linear-charging effect, good pull-up refresh circuit 120 carries out pulling process, so that the output end of high-impedance state control circuit 110
Signal waveform slope during the charging process is as constant as possible.
The waveform to be remained unchanged substantially by slope 1. with rapid decrease along waveform 4., receiver 300 can be allowed according to wave
1., 4. shape is resolved to rapid decrease along 4. corresponding negative pulse coding.
In the refresh process of refresh circuit, the work wave of each signal is as shown in Figure 8.
When the logic state of desired input signals a changes, 300 side of receiver be can recognize to a signal side
Edge can parse to obtain corresponding data such as " 600 " in Fig. 8 according to the signal edge.
Within the T1 period that desired input signals a remains unchanged (before 604 this signal edge arrive), refresh enabled
Signal b occurs once being converted to the phenomenon that logical zero restores again to logic 1 from logic 1, " 605 " waveform in corresponding diagram 8.?
The corresponding time period t 1 of 605 waveform pulls up the pull-up refresh control that the third logic circuit 1221 in refresh circuit 120 exports
Signal e1 is first changed into logic 1, then restores to logical zero, pull-up switch pipe P4 conducting, and the first current mirror 121 is opened, the 2nd PMOS
Pipe P2 is charged with output end of the constant current I to high-impedance state control circuit 110, so that high-impedance state control circuit 110 is defeated
Available 601 waveforms as in Fig. 8 of outlet so that the receiver 300 for being located at 200 one end of isolating device can recognize as
603 signal edges in Fig. 8,603 logic state can be determined according to 601 logic state.Hereby it is achieved that defeated in target
Enter the process that refresh activity is completed before the 604 of signal a this signal edge arrive, receiver 300 can detect signal side
603 signal edges are obtained before 604, to realize confirmation, the correction to 600 this signal edge.
Similarly, within other duty cycles for refreshing enable signal b, it may be possible to pull down the work of refresh circuit 130 to carry out
Drop-down handles (electric discharge), so that the output end in high-impedance state control circuit 110 obtains initial refresh signal c, waveform is similar to Fig. 8
In 602, enable 300 side of receiver to obtain corresponding signal edge to be parsed, be confirmed.
Under normal conditions, in principle shown in Fig. 8, refresh the logic state of enable signal b desired input signals a's
Logic state just reverts to logic 1 before changing, therefore can ignore the time delay condition between D1, D2.And if target inputs
The signal edge 605 that the logic state of signal a generates when changing just falls in the refresh work time t1 of a refreshing enable signal b
Interior, i.e., 604 this signal edge were in this period of t1, then needed to meet this time delay condition of D1 > D2, to avoid brush
New mistake refreshes failure, improves and refreshes accuracy rate.
In other embodiments, isolating device 200 can be incorporated in refresh circuit with lifting system stability.
Second embodiment
Based on the same inventive concept, method for refreshing is also provided in the embodiment of the present application, which can be applied to brush
New system.Updating system may include transmitter 100, receiver 300, pass through isolating device between transmitter 100 and receiver 300
200 connections.Wherein, isolating device 200 can be isolation capacitance.
It may include the refresh circuit that aforementioned first embodiment provides in transmitter 100.About the specific thin of refresh circuit
Section please refers to the associated description in aforementioned first embodiment, and details are not described herein.
As shown in figure 9, the method for refreshing in the present embodiment includes S21-S24.
S21: transmitter 100 receives desired input signals a, and the logic state of desired input signals a is the first logic or the
Two logics, first the second logic of logical AND are opposite logic state.
S22: transmitter 100 is refreshing electricity when the logic state of desired input signals a remains unchanged in preset duration
Road is to carry out pullup or pulldown processing according to desired input signals a by refresh circuit under high-impedance state, obtains refresh signal.
Wherein, the high-impedance state output of high-impedance state control circuit 110 can indicate that refresh circuit is under high-impedance state, that is, brush
Novel circuit is high-impedance state.
Those skilled in the art can according to actual needs set preset duration, for example, can be according to aforementioned reality
The durations such as t1, D2 in example are applied to set preset duration.
S23: receiver 300 receives refresh signal by isolating device 200.
S24: receiver 300 is parsed according to refresh signal, is confirmed signal.
Wherein it is possible to generate initial refresh signal c by refresh circuit and be sent to isolating device 200, by isolating device 200
Initial refresh signal c is converted into pre- refresh signal d, receiver 300 is enabled to receive and identify out pre- refresh signal d.It connects
Signal can be confirmed according to the parsing of the signal edge of pre- refresh signal d by receiving device 300.
By above-mentioned method for refreshing, can desired input signals a logic state is constant whithin a period of time or data
When rate is low, refresh circuit completes the refresh activity under high-impedance state according to desired input signals a, obtains refresh signal, for receiving
Device 300 receives refresh signal by isolating device 200, and is confirmed signal based on refresh signal parsing.Even if transmitter
There is accident in the partial circuit of 100 sides or system is interfered, and 300 side of receiver can also carry out anti-according to refresh signal
It answers, to carry out subsequent data correction, recovery.
Optionally, refresh circuit can include: high-impedance state control circuit 110, pull-up refresh circuit 120, drop-down refresh circuit
130.High-impedance state control circuit 110 includes for generating the refresh controller 112 for refreshing enable signal b.
Wherein, pull-up refresh circuit 120 can desired input signals a and refresh enable signal b collective effect under, according to
Desired input signals a and refreshing enable signal b carries out pull-up processing to the node being under high-impedance state in refresh circuit, is brushed
New signal.Pulling down refresh circuit 130 can also be in desired input signals a and under refreshing the collective effect of enable signal b, according to target
Input signal a and refreshing enable signal b carries out drop-down processing to the node being under high-impedance state in refresh circuit, obtains refreshing letter
Number.
In one embodiment, above-mentioned S22 may include:
When refresh circuit is high-impedance state, pull-up refresh circuit 120 is the second logic in desired input signals a and refreshing makes
Energy signal b carries out pull-up processing when being the first logic, obtains refresh signal.
Or, drop-down refresh circuit 130 is the first logic and brush in desired input signals a when refresh circuit is high-impedance state
New enable signal b carries out drop-down processing when being the first logic, obtains refresh signal.
Wherein it is possible to using the multiple combinations of fundamental digital logical device to realize above-mentioned logic control process.
With this can combining target input signal a, refresh the two signals of enable signal b logic state determine whether into
Row refresh activity determines refreshing opportunity.
Optionally, the high-impedance state control circuit 110 in refresh circuit may include the first delayer 111, refresh controller
112, the first logic circuit 1131, the second logic circuit 1132, target phase inverter 1133.
It for the high-impedance state of refresh circuit, can be obtained by following manner, including S31-S34.
S31: refresh controller 112 is according to desired input signals a to the first logic circuit 1131 and the second logic circuit
1132 send refreshing enable signal b.
S32: the first delayer 111 is according to desired input signals a to the first logic circuit 1131 and the second logic circuit
1132 send the first time delayed signal a1.
S33: the first logic circuit 1131 exports the control of the first reverse phase according to enable signal b, the first time delayed signal a1 is refreshed
Signal f, and, the second logic circuit 1132 exports the second reverse phase control letter according to enable signal b, the first time delayed signal a1 is refreshed
Number g.
S34: target phase inverter 1133 receives the first inverted control signal f and the second inverted control signal g, and according to first
Inverted control signal f, the second inverted control signal g export high-impedance state.
Wherein, when refreshing enable signal b is the first logic, the first reverse phase that the first logic circuit 1131 is exported is controlled
The logic state of signal f is the second logic, the logic state for the first inverted control signal f that the second logic circuit 1132 is exported
For the first logic；When refreshing enable signal b is the second logic, the first inverted control signal f, the second inverted control signal g
Logic state is identical, and the logic state of the first inverted control signal f, the second inverted control signal g are inputted according to the target
Signal a is determined.
With this refresh process can be completed based on a kind of refresh circuit of exportable high-impedance state.
Due to that can be related to during obtaining high-impedance state and during determining specifically pull-up or drop-down processing
Refresh enable signal b, and subsequent refresh activity is carried out based on the logic state for refreshing enable signal b.Therefore, method for refreshing may be used also
To include:
Before carrying out pullup or pulldown processing, the logic state for refreshing enable signal b is determined.
As an implementation, the logic state for refreshing enable signal b can be determined in the following manner:
Refresh controller 112 will periodically refresh the logic of enable signal b when desired input signals a remains unchanged
State is restored after being converted to the first logic to the second logic.
Refresh controller 112 will refresh the logic state transition of enable signal b to the when desired input signals a changes
Two logics.
The logic state of refreshing enable signal b can be determined with this, and based on refreshing enable signal b and target input
The logic state of signal a is refreshed.
3rd embodiment
The present embodiment provides a kind of chip, which includes the refresh circuit that aforementioned first embodiment provides.
The chip can be digital isolating chip, for example, it may be capacitor digital isolator.
The detail of the refresh circuit involved in the present embodiment, please further refer in aforementioned first embodiment
Associated description, details are not described herein.
By said chip, improve data transfer accuracy rate when data are transmitted, lifting system robust can be used in chip
Property.Even if accident occurs for system, receiver 300 also can carry out data validation according to the refresh signal of chip output in time, correct.
Fourth embodiment
The present embodiment provides a kind of data transmission systems 10, and as shown in Figure 10, which includes transmitter
100, receiver 300.It is connected between transmitter 100 and receiver 300 by an isolating device 200.
Transmitter 100 includes the refresh circuit that aforementioned first embodiment provides, and with this data transmission system 10 is had
Refresh Data function.
By above-mentioned data transmission system 10, transmitter 100, which can use refresh circuit and send to receiver 300, refreshes letter
Number, receiver 300 can be received refresh signal by isolating device 200 and carry out subsequent dissection process, and signal is confirmed.I.e.
Keep the interval time of two adjacent edge signals of input signal long, 300 side of receiver can also be counted based on refresh signal
According to confirmation, and then error in data caused by some fortuitous events is corrected in time, is restored.
In embodiment provided herein, it should be understood that embodiments described above is only schematical,
For example, the division to module, unit in circuit, only a kind of logical function partition, can there is other draw in actual implementation
The mode of dividing, in another example, multiple units or components can be combined or can be integrated into another system or some features can neglect
Slightly, it or does not execute.In addition, unit may or may not be physically separated as illustrated by the separation member.Furthermore
Each functional module in each embodiment of the application can integrate one independent part of formation together, be also possible to each
Module individualism can also be integrated to form an independent part with two or more modules.
Herein, relational terms such as first and second and the like be used merely to by an entity or operation with it is another
One entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this reality
Relationship or sequence.
The above description is only an example of the present application, the protection scope being not intended to limit this application, for ability
For the technical staff in domain, various changes and changes are possible in this application.Within the spirit and principles of this application, made
Any modification, equivalent substitution, improvement and etc. should be included within the scope of protection of this application.
Claims (15)
1. a kind of refresh circuit, which is characterized in that the refresh circuit include: high-impedance state control circuit, pull-up refresh circuit, under
Draw refresh circuit；
The input terminal of the high-impedance state control circuit is for receiving desired input signals, the logic state of the desired input signals
For the first logic or the second logic, the second logic described in first logical AND is opposite logic state；
The output end of the high-impedance state control circuit is connect with the pull-up refresh circuit；
The output end of the high-impedance state control circuit is also connect with the drop-down refresh circuit；
The output end of the high-impedance state control circuit also passes through an isolating device and connect with external receiver；
Wherein, it remains unchanged in preset duration in the logic state of the desired input signals, and high-impedance state control electricity
When the output on road is high-impedance state, the pull-up refresh circuit is according to the desired input signals to the high-impedance state control circuit
Output signal is pulled up, or, the drop-down refresh circuit is according to the desired input signals to the high-impedance state control circuit
Output signal pulled down, to obtain refresh signal.
2. refresh circuit according to claim 1, which is characterized in that the high-impedance state control circuit includes the first delay
Device, refresh controller, high-impedance state control module；
First delayer, for generating the first time delayed signal by the first delay according to the desired input signals；
The refresh controller refreshes enable signal for exporting according to the desired input signals；
The high-impedance state control module, for exporting high resistant according to first time delayed signal and the refreshing enable signal
State.
3. refresh circuit according to claim 2, which is characterized in that the high-impedance state control module includes the first logic electricity
Road, the second logic circuit, target phase inverter；
First logic circuit, for exporting the first reverse phase control according to first time delayed signal, the refreshing enable signal
Signal processed；
Second logic circuit, for exporting the second reverse phase control according to first time delayed signal, the refreshing enable signal
Signal processed；
The target phase inverter, for exporting high resistant according to first inverted control signal, second inverted control signal
State.
4. refresh circuit according to claim 3, which is characterized in that the target phase inverter includes the first PMOS tube, the
One NMOS tube；
The grid of first PMOS tube is connect with first logic circuit, and the source electrode of first PMOS tube connects power supply, institute
The drain electrode for stating the first PMOS tube is connect with the drain electrode of first NMOS tube；
The grid of first NMOS tube is connect with second logic circuit, the source electrode ground connection of first NMOS tube.
5. refresh circuit according to claim 1, which is characterized in that the pull-up refresh circuit include the first current mirror,
Pull-up control circuit；
Two input terminals of the pull-up control circuit, which are respectively used to receive, refreshes enable signal, the desired input signals；
The output end of the pull-up control circuit is connect with first current mirror；
First current mirror is used to carry out linear-charging to the output end of the high-impedance state control circuit.
6. refresh circuit according to claim 5, which is characterized in that the pull-up control circuit includes third logic electricity
Road, pull-up switch pipe；
The control terminal of the pull-up switch pipe is connect with the output end of the third logic circuit, the output of the pull-up switch pipe
End is connect with first current mirror；
The third logic circuit, for being the second logic in the desired input signals and the refreshing enable signal is first
When logic, output logic state is the pull-up refresh control signal of the second logic；
The third logic circuit is also used to, in non-second logic of the desired input signals and/or the refreshing enable signal
When non-first logic, output logic state is the pull-up refresh control signal of the first logic.
7. refresh circuit according to claim 1, which is characterized in that
The drop-down refresh circuit includes the second current mirror, pull-down control circuit；
Two input terminals of the pull-down control circuit, which are respectively used to receive, refreshes enable signal, the desired input signals；
The output end of the pull-down control circuit is connect with second current mirror；
Second current mirror is used to carry out linear discharge to the output end of the high-impedance state control circuit.
8. refresh circuit according to claim 7, which is characterized in that
The pull-down control circuit includes the 4th logic circuit, pull down switch pipe；
The control terminal of the pipe that pulls down switch is connect with the output end of the 4th logic circuit, the output of the pipe that pulls down switch
End is connect with second current mirror；
4th logic circuit, for being the first logic in the desired input signals and the refreshing enable signal is first
When logic, output logic state is the drop-down refresh control signal of the first logic；
4th logic circuit is also used to, in non-first logic of the desired input signals and/or the refreshing enable signal
When non-first logic, output logic state is the drop-down refresh control signal of the second logic.
9. a kind of method for refreshing, which is characterized in that be applied to updating system, the updating system includes transmitter, receiver, institute
It states and is connected between transmitter and the receiver by isolating device, the transmitter includes described in claim any one of 1-8
Refresh circuit, which comprises
The transmitter receives desired input signals, and the logic state of the desired input signals is that the first logic or second are patrolled
Volume, the second logic described in first logical AND is opposite logic state；
The transmitter is when the logic state of the desired input signals remains unchanged in preset duration, in the refreshing electricity
Road is to carry out pullup or pulldown processing according to the desired input signals by the refresh circuit under high-impedance state, obtains refreshing letter
Number；
The receiver receives the refresh signal by the isolating device；
The receiver is parsed according to the refresh signal, is confirmed signal.
10. method for refreshing according to claim 9, which is characterized in that the refresh circuit includes: high-impedance state control electricity
Road, pull-up refresh circuit, drop-down refresh circuit；The high-impedance state control circuit includes for generating the refreshing for refreshing enable signal
Controller；
Pullup or pulldown is carried out to the desired input signals by the refresh circuit in the case where the refresh circuit is high-impedance state
The step of handling, obtaining refresh signal, comprising:
When the refresh circuit is high-impedance state, the pull-up refresh circuit is the second logic and institute in the desired input signals
It states to refresh when enable signal is the first logic and carries out pull-up processing, obtain refresh signal；
Or, the drop-down refresh circuit is the first logic in the desired input signals when the refresh circuit is high-impedance state
And the refreshing enable signal obtains refresh signal to carry out drop-down processing when the first logic.
11. method for refreshing according to claim 9, which is characterized in that the high-impedance state control circuit in the refresh circuit
Including the first delayer, refresh controller, the first logic circuit, the second logic circuit, target phase inverter；
The high-impedance state of the refresh circuit is obtained by following manner:
The refresh controller is according to the desired input signals to first logic circuit and second logic circuit
It sends and refreshes enable signal；
First delayer is according to the desired input signals to first logic circuit and second logic circuit
Send the first time delayed signal；
First logic circuit exports the first reverse phase control letter according to the refreshing enable signal, first time delayed signal
Number, and, second logic circuit exports the second reverse phase and controls according to the refreshing enable signal, first time delayed signal
Signal；
The target phase inverter receives first inverted control signal and second inverted control signal, and according to described the
One inverted control signal, second inverted control signal export high-impedance state；
Wherein, when the refreshing enable signal is the first logic, the first reverse phase that first logic circuit is exported is controlled
The logic state of signal is the second logic, and the logic state for the first inverted control signal that second logic circuit is exported is
First logic；
When the refreshing enable signal is the second logic, first inverted control signal, second inverted control signal
Logic state it is identical, and the logic state of first inverted control signal, second inverted control signal is according to
Desired input signals determine.
12. method for refreshing according to claim 11, which is characterized in that determine that described refresh enables letter in the following manner
Number logic state:
The refresh controller will periodically refresh the logic shape of enable signal when the desired input signals remain unchanged
State is restored after being converted to the first logic to the second logic.
13. a kind of chip, which is characterized in that including the described in any item refresh circuits of claim 1-8.
14. a kind of data transmission system, which is characterized in that the system comprises transmitters, receiver；
The transmitter includes the described in any item refresh circuits of claim 1-8；
It is connected between the transmitter and the receiver by an isolating device.
15. data transmission system according to claim 14, which is characterized in that the isolating device is isolation capacitance.
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