CN102819282A - Clock recovery circuit device and corresponding method - Google Patents
Clock recovery circuit device and corresponding method Download PDFInfo
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- CN102819282A CN102819282A CN2012102626222A CN201210262622A CN102819282A CN 102819282 A CN102819282 A CN 102819282A CN 2012102626222 A CN2012102626222 A CN 2012102626222A CN 201210262622 A CN201210262622 A CN 201210262622A CN 102819282 A CN102819282 A CN 102819282A
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Abstract
The invention discloses a clock recovery circuit device and a corresponding method. The device comprises a data preprocessing circuit, a clock recovery circuit and a control circuit. Through the data preprocessing circuit, received data flow signals are transformed into standard digital signals and output to the clock recovery circuit. The clock recovery circuit generates clock signals through an oscillator and obtains frequency information from the standard digital signals. Control signals are obtained through the differences of the obtained actual frequency and the target frequency. According to the control signals, the clock signals are corrected to the accuracy range meeting the requirements. The control circuit turns on and turns off the correcting process of the clock recovery circuit and configures corresponding parameters of the clock recovery. According to the clock recovery circuit device and the corresponding method, the frequency and the accuracy of a local clock can meet the accuracy requirements on the decoding of data flow.
Description
Technical field
The present invention relates to the clock circuit device in the computer system, relate in particular to the clock recovery circuitry device and the corresponding method of system.
Background technology
Clock has vital role in the data transmission procedure of computer system.Receiving equipment needs the clock signal reception data of sampling; Transmitting apparatus need send data with certain speed.Therefore the clock signal that produces meet the demands frequency and precision has also just become the key in the data transmission.Such as, USB (Universal Serial Bus) 2.0 standards of generally having used have just proposed corresponding requirement to the clock of using in the data transmission, and it has stipulated the data pattern of quick data transfering stream signal.According to this USB2.0 standard, USB device can be divided into three kinds according to the height of traffic rate: low-speed mode, full speed pattern and fast mode.Simultaneously, for the work clock under the different rates comparatively strict regulation is arranged, low-speed mode is 1.5MHZ down, and precision is ± 1.5%; Be 12MHZ under the pattern at full speed, precision is ± 0.25%; Fast mode is 480MHZ down, and precision is ± 0.05%.
Traditional clock generator is based on that the clock source of the chip exterior of using clock realizes, crystal oscillator is elected in this clock source usually as, such as quartz crystal oscillator circuits or piezoelectric oscillator circuit.Chip is adjusted the reference clock that crystal oscillator produces, and makes it satisfy required frequency of decoded data stream and accuracy requirement.Yet,,, thereby be not suitable for area, power consumption etc. are required relatively harsher embedded device so this outer oscillator increased the cost of design for the chip that needs the sheet internal oscillator because crystal oscillator can't be integrated on the silicon circle crystalline substance usually.And, because crystal oscillator is easy to receive the destruction of physical impact, thereby be not suitable for portable equipment.Traditional providing by external clock reference in the computer system of reference clock; Delay lock loop (DLL commonly used; Delay Lock Loop) or phase place phaselocked loop (PLL; Phase Lock Loop) circuit locks onto the frequency and the precision of regulation with reference clock, to satisfy the rate requirement that receives signal.This also can increase the cost of equipment.
At present, clock generator generally is to utilize that oscillator produces local clock on the sheet.
What patent documentation 1 (US7093151) was described is a kind of device according to oscillator generation local clock on the sheet, and its structure is as shown in Figure 3, comprises detecting device, counter, controller, programmable oscillator; Its course of work is: detecting device detects the time signal that comprises in the data stream, and counter is counted clock signal clk between adjacent time signal, obtains count value CNT; Controller is according to count value CNT query counts value-Configuration Values record sheet, and generation Configuration Values CN; Programmable oscillator is adjusted to frequency within the accuracy rating of regulation according to this CN Configuration Values.The frequency that the mode that this patent documentation 1 utilization is tabled look-up is come oscillator on the trim tab, this needs bigger internal memory come data in the storage list, and can increase area of chip.And the method requires the curve of oscillator frequency and parameter to have strict linear corresponding relation, and this has just proposed the very requirement of strictness to the technology of oscillator.Be difficult to reach this requirement in the bigger occasion of range of temperature.
The implementation that patent documentation 2 (US7120813) is described is: use the oscillator of a high speed to produce the clock signal of a plurality of outs of phase, high many of the frequency ratio assigned frequency of these clock signals; The synthetic clock signal that satisfies accuracy requirement of temporal information that comprises according to data stream then.The method of this patent documentation 2 will be used an oscillator that frequency is very high, can increase the cost of design, needs a bigger internal memory simultaneously, and this also can increase area of chip.
In present computer system, the USB2.0 regulation and stipulation a kind of between main process equipment and USB device the form of quick data transfering.As shown in Figure 1, traffic rate is under the full speed pattern, and the transmission of data is unit with the frame, and each frame data all is to begin with start frame (SOF, Start Of Frame) packet, finishes with end frame (EOF, End Of Frame) sign.Main process equipment periodically sends the SOF packet, and Frame receives strict time and accuracy limitations: the time span of each Frame in usb data stream is 1ms ± 500ns, that is to say that the SOF packet can transmit on data line with the time interval of 1ms.
According to the regulation of USB2.0 agreement, main frame and USB device are realized the mutual of data through the differential signal that transmits a pair of data-signal.For anti-interference that strengthens data and the activity of keeping bus, data had been carried out bit filling (Bit-Stuff) and reverse non-return-to-zero (NRZI, Non Return To Zero Inverted) coding before sending to bus.Bit is filled and to be meant after having occurred continuous 61 on the data bus, will introduce 1 redundant digit 0 by force.The nrzi encoding mode is that " 0 " in the index certificate adopts the logic level saltus step at data starting point place to represent that " 1 " in the data then adopts no level saltus step to represent.As shown in Figure 2 is the structural information and the nrzi encoding information of SOF packet.The usb data bag all is with synchronizing sequence (Sync; Be fixing 80H) beginning; Then being the sign (PID, Packet Identifier) of this packet and the check field (PIDB) of PID, then is the CRC (CRC of the concrete data message of this packet and this data message again; Cyclic Redundancy Check), be the end sign EOP of this packet at last.Different data are surrounded by different PID, and fixing coding is all arranged; The data message of SOF packet is the frame number of this Frame, and the scope of frame number is 0～1023, and reaching makes zero after the maximal value restarts counting.Sync/PID/PIDB/EOP (2SE0+J) is fixing signal, and the detection of SOF packet can be realized through the detection to synchronizing sequence and PID sequence.
Can design a kind of like this clock recovery circuitry device, when receiving the SOF packet, use its timing information that carries to recover local clock through USB full speed equipment.And it does not need look-up table, and can in the timing information interval, obtain a plurality of reference signals.
Summary of the invention
Technical matters to be solved by this invention provides a kind of clock recovery circuitry device and corresponding method, can make the frequency accuracy of local clock reach needed requirement.
In order to solve the problems of the technologies described above, the invention provides a kind of clock recovery circuitry device, comprise the data pre-process circuit, clock recovery circuitry and the control circuit that connect successively, wherein:
The data pre-process circuit is used for converting the traffic spike that receives into standard digital signals, and exports to clock recovery circuitry;
Clock recovery circuitry; Be used for through the oscillator clocking; From said standard digital signals, obtain frequency information, obtain control signal, clock signal is calibrated in the accuracy rating that meets the demands according to this control signal by the difference of actual frequency that obtains and target frequency;
Control circuit is used for the calibration process of opening and closing clock recovery circuitry, and configurable clock generator recovers relevant parameters.
Further, clock recovery circuitry comprises testing circuit, calibration pulse generative circuit, counter circuit, calibration circuit and the parameter tunable oscillator circuit that connects successively, wherein:
Testing circuit connects the parameter tunable oscillator circuit, is used for according to detected time information generating detection signal, and exports to the calibration pulse generative circuit;
The calibration pulse generative circuit is used for producing a plurality of calibration pulse signals according to detection signal, with the opening and closing of timesharing control counter circuit;
Counter circuit is used under the timesharing control of two calibration pulse signals, clock signal being counted, and count value is exported to calibration circuit;
Calibration circuit is used under the control of control circuit the difference according to the parameter value of count value and local maintenance, is the control signal of M position to parameter tunable oscillator circuit output data width, and M is a positive integer;
The parameter tunable oscillator circuit is used for also exporting to testing circuit sum counter circuit respectively through the oscillator clocking, calibrates the frequency of clock signal by turn according to the control signal of M position;
The parameter of control circuit configuration comprises the reference value of counter circuit and the figure place that control signal is participated in calibration.
Further, testing circuit also is connected with counter circuit, wherein:
Testing circuit utilizes synchronization signal detection behind last bit of PID Packet Identifier, to produce detection signal, when exporting to the calibration pulse generative circuit, also exports to counter circuit;
Counter circuit is counted clock signal under the control of two detection signals in course of normal operation; And count value exported to calibration circuit, whether clock signal is calibrated according to the difference decision of the parameter value of this count value and local maintenance by this calibration circuit.
Further, testing circuit comprises data recovery circuit and detection signal statement circuit, wherein:
The data pre-process circuit is connected with data recovery circuit, converts the differential signal of a pair of usb data that receives into standard reverse non-return-to-zero signal, and exports to data recovery circuit;
Data recovery circuit is connected with the parameter tunable oscillator circuit, is used for according to clock signal the reverse non-return-to-zero signal of standard being decoded, and sends the numeric string that produces to detection signal statement circuit;
Detection signal statement circuit produces circuit with said calibration pulse and is connected, and is used for the detection signal of each generation according to the digital signal of data recovery circuit transmission, and exports to calibration pulse generation circuit or counter circuit;
Counter circuit is opened after receiving first calibration pulse signal or first detection signal clock signal is counted; After receiving next calibration pulse signal or next detection signal, close the counting to clock signal, the count value of exporting between adjacent calibration pulse signal or adjacent detection signal is given calibration circuit;
It is L that calibration circuit is set control signal adjustment figure place through control circuit, L≤M, and the L position with control signal is changed to 0 entirely earlier; According to the L position of control signal relatively count value and reference value one by one,, then successively the corresponding positions of the control signal of L position is adjusted into 1 if count value is greater than said reference value; If count value is less than or equal to reference value, then successively the corresponding positions of the control signal of L position is adjusted into 0; Lowest order until the L position has been adjusted, and produces look-at-me and gives control circuit, simultaneously the control signal of M position is exported to the parameter tunable oscillator circuit;
The parameter tunable oscillator is according to the control signal of said M the position frequency of alignment oscillator clock signal, that is: f by turn
CLOCK=k
0* f+k
1* f+......+k
M* f, this f is the frequency signal of oscillator benchmark, this k
M=0 or 1.
Further, also comprise the functional circuit of utilization parameter tunable oscillator circuit, be used to use clock signal to realize the application corresponding function through calibration through the clock signal of calibration.
In order to solve the problems of the technologies described above, the invention provides a kind of clock recovery method, relate to foregoing clock recovery circuitry device, this method comprises:
Clock recovery circuitry is through the internal oscillator clocking; Obtain frequency information in the standard digital signals according to reception of data pre-process circuit and conversion; Difference by actual frequency that obtains and target frequency is obtained control signal, according to this control signal clock signal is calibrated in the accuracy rating that meets the demands.
Further,, this method also comprises before carrying out:
Behind clock recovery circuitry device electrification reset, control circuit is opened clock recovery circuitry, disposes relevant parameters simultaneously.
Further; Obtain frequency information in the standard digital signals that clock recovery circuitry receives and changes according to the data pre-process circuit; Difference by actual frequency that obtains and target frequency is obtained control signal; According to this control signal clock signal is calibrated in the accuracy rating that meets the demands, specifically comprises:
The data pre-process circuit converts differential signal the reverse non-return-to-zero signal with usb data numerical coding form of standard into, and exports to clock recovery circuitry after receiving the differential signal of two-way usb data;
Clock recovery circuitry passes through testing circuit according to detected time information generating detection signal; Produce a plurality of calibration pulse signals through the calibration pulse generative circuit according to said detection signal; Through counter circuit in calibration process under the timesharing of two calibration pulse signals control, clock signal is counted; Through the difference of calibration circuit according to the reference value of the count value of counter circuit and local maintenance, the output data width is the control signal of M position, and M is a positive integer; Calibrate the frequency of clock signal by turn according to the control signal of M position through the parameter tunable oscillator circuit.
Further, testing circuit specifically comprises according to detected time information generating detection signal:
Testing circuit utilizes synchronization signal detection behind last bit of PID Packet Identifier, to produce detection signal, as the sign output that detects the start frame packet.
Further, this method also comprises:
Counter circuit is counted clock signal under the timesharing control of two detection signals in course of normal operation; And count value exported to said calibration circuit; By the difference of this calibration circuit according to the reference value of this count value and local maintenance, whether decision gets into the calibration process to clock signal.
Further, counter circuit is counted clock signal under the timesharing control of two calibration pulse signals or two detection signals, specifically comprises:
Counter circuit is opened the counting to clock signal after receiving first calibration pulse signal or first detection signal; After receiving next calibration pulse signal or next detection signal, close counting, and export the count value between adjacent calibration pulse signal or the adjacent detection signal clock signal.
Further, calibration circuit is according to the difference of the reference value of the count value of counter circuit and local maintenance, and the output data width is the control signal of M position, specifically comprises:
It is L that calibration circuit is set control signal adjustment figure place through control circuit, L≤M, and the L position with control signal is changed to 0 entirely earlier; According to the L position of control signal relatively count value and reference value one by one,, then successively the corresponding positions of the control signal of L position is adjusted into 1 if count value is greater than reference value; If count value is less than or equal to reference value, then successively the corresponding positions of the control signal of L position is adjusted into 0; Lowest order until the L position has been adjusted, and produces look-at-me and gives control circuit, simultaneously the control signal of M position is exported to the parameter tunable oscillator circuit.
Further, the parameter tunable oscillator circuit is calibrated the frequency of clock signal by turn according to the control signal of M position, specifically comprises:
The parameter tunable oscillator is according to the control signal of M the position frequency of alignment oscillator clock signal, that is: f by turn
CLOCK=k
0* f+k
1* f+......+k
M* f, this f is the frequency signal of oscillator benchmark, this k
M=0 or 1.
The present invention produces the lower clock signal of initial precision through using a simple sheet internal oscillator; Adjust the parameter of oscillator by control circuit by turn according to the temporal information that data stream comprises, thereby make the frequency of local clock and precision reach the needed accuracy requirement of decoded data stream.
Description of drawings
Fig. 1 is the stream data transmission pattern diagram of prior USB regulation and stipulation;
Fig. 2 is a SOF bit mode information and coding synoptic diagram in the prior USB data stream;
Fig. 3 is existing device and the structural representation thereof that produces local clock according to oscillator on the sheet;
Fig. 4 is the structured flowchart of clock recovery circuitry device embodiment of the present invention;
Fig. 5 is a calibration circuit working process flow diagram among the clock recovery circuitry device embodiment shown in Figure 4;
Fig. 6 is a clock recovery circuitry device course of work process flow diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment technical scheme of the present invention is done explanation further.Should be appreciated that following listed examples only is used for explanation and explains the present invention, and does not constitute the restriction to technical scheme of the present invention.
As shown in Figure 4, represented the structure of clock recovery circuitry device embodiment of the present invention, comprise the data pre-process circuit, clock recovery circuitry (in the empty frame of Fig. 4) and the control circuit that connect successively, wherein:
The data pre-process circuit is used for converting the traffic spike that receives (DATA) into standard digital signals (NRZI signal), and exports to clock recovery circuitry;
Clock recovery circuitry; Be used for through the oscillator clocking; From the standard digital signals of input, obtain frequency information, obtain control signal, clock signal is calibrated in the accuracy rating that meets the demands according to this control signal by the difference of actual frequency that obtains and target frequency;
Control circuit is used for the calibration process of opening and closing clock recovery circuitry, and configurable clock generator recovers relevant parameters.
In said apparatus embodiment, clock recovery circuitry comprises testing circuit, calibration pulse generative circuit, counter circuit, calibration circuit and the parameter tunable oscillator circuit that connects successively, wherein:
Testing circuit connects the parameter tunable oscillator circuit, is used for testing circuit according to detected time information generating detection signal (DET), and the DET signal is exported to the calibration pulse generative circuit;
The calibration pulse generative circuit is used for producing a plurality of calibration pulse signals (TDs) according to the detection signal of input, with the opening and closing of timesharing control counter circuit;
Counter circuit is used under the timesharing control of calibration process at two calibration pulse signals (TDs), clock signal (CLOCK) being counted, and count value is exported to calibration circuit;
The USB2.0 regulation and stipulation, the time interval between the adjacent SOF packet is 1ms, precision is ± 0.05%.The calibration pulse generative circuit produces N calibration pulse signal in 1ms, wherein N is a positive integer.
Calibration circuit; Being used under the control of control circuit the difference according to the parameter value (representative target frequency) of the count value (representative actual frequency) of input and local maintenance, is M (M is a positive integer) control signal CON to parameter tunable oscillator circuit output data width;
The parameter tunable oscillator circuit is used for calibrating the frequency of clock signal by turn according to the control signal of M position with also exporting to testing circuit sum counter circuit respectively through oscillator clocking (CLOCK);
The parameter of control circuit configuration comprises the reference value of counter circuit and the figure place that control signal is participated in calibration.
In said apparatus embodiment, testing circuit also is connected with counter circuit, wherein:
The detection signal (DET) that testing circuit produces is also exported to counter circuit;
Counter circuit is counted clock signal (CLOCK) under the control of two detection signals (DET) in course of normal operation; And count value exported to calibration circuit; By the difference of this calibration circuit according to the parameter value of this count value and local maintenance, whether decision calibrates clock signal.
In said apparatus embodiment, testing circuit comprises data recovery circuit and detection signal statement circuit, wherein:
The differential signal of a pair of usb data that the data pre-process circuit will receive (the usb data stream that usb host or router send) converts standard NRZI signal into, and this NRZI signal is exported to data recovery circuit such as the numerical coding form that is usb data;
Data recovery circuit; Be connected with the parameter tunable oscillator circuit with the data pre-process circuit respectively; Be used for the standard NRZI signal of input being decoded, and send the numeric string (0 or 1) that produces to detection signal statement circuit according to the clock signal of parameter tunable oscillator circuit output;
Detection signal statement circuit produces circuit with calibration pulse and is connected, and is used for each the generation detection signal (DET) according to the digital signal (0 or 1) of data recovery circuit transmission, exports to calibration pulse and produces circuit or counter circuit;
Counter circuit is opened the clock signal counting to input after receiving first TD signal or first detection signal; After receiving next TD signal or next detection signal, close clock signal counting, export between adjacent TD signal or detection signal count value thus and give calibration circuit clock signal;
It is that (L≤M), the L position with CON is changed to 0 to L entirely earlier that calibration circuit is set control signal CON adjustment figure place through control circuit; Compare count value and reference value (promptly comparing actual frequency and target frequency) from high to low one by one according to the L position of CON; If this comparative result is a count value greater than reference value (the expression actual frequency is higher than target frequency), then successively the corresponding positions of the CON of L position is adjusted into 1; If count value is less than or equal to reference value (expression actual frequency be lower than target frequency), then successively the corresponding positions of the CON of L position is adjusted into 0; Lowest order until the L position has been adjusted, and produces look-at-me (INT) and gives control circuit, and the CON with the M position exports to the parameter tunable oscillator circuit simultaneously;
The parameter tunable oscillator circuit is according to the control signal of M position (or reverse order) frequency of alignment oscillator clock signal, that is: f by turn from high to low
CLOCK=k
0* f+k
1* f+......+k
M* (f is the frequency signal of oscillator benchmark to f, k
M=0,1; M is the integer more than or equal to zero).
Through the adjustment by turn of control signal CON being realized the calibration of oscillator clock frequency.Since adjacent two SOF packets be spaced apart 1ms, precision is ± 0.05%, the precision of oscillator can be calibrated to ± 0.25% in.
In general, the requirement that the initial precision of the oscillator of formation local clock does not reach decoded data stream, after adjustment, the precision of local clock can satisfy application requirements.Such as, in certain Application and implementation, the frequency of clock is 12MHZ, initial precision is below 5%; After clock recovery circuitry calibration of the present invention, its precision can reach more than 0.25%, can satisfy the requirement of decoded data stream fully.
Said apparatus embodiment also comprises the USB functional circuit, is used for the clock signal realization USB transfer function of operation parameter tunable oscillator circuit through calibration.
Certainly, parameter tunable oscillator circuit of the present invention also can be used for other function through the clock signal of calibration, such as the signal transfer functions of smart card, the inscription of CD or read functions etc.
In said apparatus embodiment, control circuit is made up of CPU, and is as shown in Figure 4.
The present invention is directed to said apparatus embodiment, clock recovery method embodiment correspondingly also is provided, relate to clock recovery circuitry device of the present invention, this method comprises the steps:
The data pre-process circuit converts the traffic spike that receives into standard digital signals, and exports to clock recovery circuitry;
Clock recovery circuitry is through the oscillator clocking; From standard digital signals, obtain frequency information; Difference by actual frequency that obtains and target frequency is obtained control signal, according to this control signal clock signal is calibrated in the accuracy rating that meets the demands.
Said method embodiment also comprises:
Behind clock recovery circuitry device electrification reset, control circuit is opened clock recovery circuitry, disposes relevant parameters simultaneously.
In said method embodiment, the data pre-process circuit converts the traffic spike that receives into standard digital signals, specifically comprises:
The data pre-process circuit converts the differential signal of the two-way usb data that receives into the NRZI signal with usb data numerical coding form of standard.
In said method embodiment; Clock recovery circuitry is through the oscillator clocking; From the standard digital signals of input, obtain frequency information; Difference by actual frequency that obtains and target frequency is obtained control signal, according to this control signal clock signal is calibrated in the accuracy rating that meets the demands, and specifically comprises:
Testing circuit is according to detected time information generating detection signal, and exports to the calibration pulse generative circuit;
The calibration pulse generative circuit produces a plurality of calibration pulse signals (TDs) according to the detection signal of input, with the opening and closing of timesharing control counter circuit;
Counter circuit under the timesharing control of two calibration pulse signals, is counted the clock signal of parameter tunable oscillator circuit output in calibration process;
Calibration circuit according to the difference of the reference value of the count value of counter circuit and local maintenance, is the control signal CON of M (M is a positive integer) position to parameter tunable oscillator circuit output data width under the control of control circuit;
The parameter tunable oscillator circuit is calibrated the frequency of clock signal by turn according to the control signal of M position.
In said method embodiment, testing circuit is according to detected time information generating detection signal, and exports to the calibration pulse generative circuit, specifically comprises:
Testing circuit utilizes synchronization signal detection behind last bit of PID Packet Identifier (PID), to produce detection signal, exports to the calibration pulse generative circuit as the sign that detects the SOF packet.
The USB2.0 regulation and stipulation, the time interval between the adjacent SOF packet is 1ms, precision is ± 0.05%.The full sized pules generative circuit produces N calibration pulse signal in 1ms, wherein N is a positive integer.
In said method embodiment, also comprise:
Counter circuit is counted clock signal under the timesharing control of two detection signals in course of normal operation; And count value exported to calibration circuit; By the difference of this calibration circuit according to the reference value of this count value and local maintenance, whether decision gets into the calibration process to clock signal.
In said method embodiment, counter circuit under the timesharing control of two calibration pulse signals or two detection signals, is counted the clock signal of parameter tunable oscillator circuit output in calibration process, specifically comprises:
Counter circuit is opened the counting to clock signal after receiving first calibration pulse signal TD or first detection signal DET; After receiving next TD signal or next DET signal, close counting, and export adjacent TD signal or the count value between the DET signal clock signal.
Fig. 5 has represented calibration circuit working flow process among the clock recovery circuitry device embodiment, comprises the steps:
50: control signal CON most significant digit is made as 1, and all the other positions are made as 0;
51: judging whether count value＞reference value, is then to represent actual frequency greater than target frequency, and the CON most significant digit is remained 1; Otherwise the expression actual frequency is less than or equal to target frequency, and the CON most significant digit is made as 0;
52: a CON high position is made as 1, and all the other positions remain unchanged;
53: judging whether count value＞reference value, is then a CON high position to be made as 1; Otherwise a CON high position is made as 0;
……
57: until the CON lowest order is made as 1, all the other positions remain unchanged;
58: judging whether count value＞reference value, is then the CON lowest order to be made as 1; Otherwise the CON lowest order is made as 0;
59: calibration finishes to produce look-at-me INT and gives control circuit.
Fig. 6 has represented clock recovery circuitry device course of work flow process of the present invention, comprises the steps:
60: carry out calibration process after device powers on, meet accuracy requirement until clock signal is calibrated to;
According to the regulation of USB2.0 agreement, main process equipment after detecting new USB device and inserting, this USB device that at first resets, the address 0 that this moment, this USB device had acquiescence.USB full speed equipment can receive the SOF packet of main frame or router transmission.The present invention can obtain to satisfy the clock signal of application requirements through several SOF packets before using, and this is called the calibration process that powers on.
Above-mentioned steps is exactly the calibration operation that powers on of one whole.
61,62: once and again monitor the clock signal process in real time, do not meet accuracy requirement until monitoring clock signal;
Oscillator has obtained to satisfy the local clock signal of accuracy requirement behind the calibration process that powers on.
But continuous work along with oscillator; The variation of surrounding environment can cause the original oscillation frequency of the frequency departure of oscillator; Thereby cause the frequency of oscillator to produce bigger error; In order to prevent that oscillator frequency from departing from the needed accuracy rating of decoded data stream signal for a long time, the present invention has increased the process that oscillator frequency is monitored in real time.
Monitoring in the process of oscillator frequency in real time, counter is worked under the control of detection signal DET.Counter is counting clock pulse between adjacent SOF packet, and the reference value of preserving with this locality relatively; If relatively difference has exceeded the scope of regulation, then produce look-at-me, control circuit (CPU) starts the clock alignment in the course of work according to this look-at-me.
63: calibrate in the course of work, meet accuracy requirement until clock signal is calibrated to.
64: after course of work calibration finishes, continue clock signal is monitored.
Calibration and last electric calibration are similar in the course of work, also are through calibration process mentioned above.Its adjustment figure place can be set, and opening and closing are controlled by CPU equally.
The present invention produces the lower clock signal of initial ratio of precision through using a simple sheet internal oscillator; Control circuit is adjusted the parameter of oscillator by turn according to the temporal information that data stream comprises, thereby makes the frequency of local clock and precision reach the needed accuracy requirement of decoded data stream.
The present invention detects accurate timing information from traffic spike, and in the time interval that timing information is confirmed, repeatedly adjusts, thus the Rapid Realization calibration.
The present invention is applicable to USB pattern at full speed.SOF packet in the usb data stream carries timing information, and the time interval between two adjacent SOF packets is defined as 1ms ± 500ns by strictness, precision promptly ± 0.05%.According to the design, counter is (such as 1/Nms) counting local clock pulse within a certain period of time, and compares with corresponding reference value, thereby realizes the calibration of local clock signal.The precision of oscillator clock signal can be calibrated to ± 0.25% in.
Though the embodiment that the present invention disclosed as above, the embodiment that described content just adopts for the ease of understanding the present invention is not in order to limit the present invention.Technician under any the present invention in the technical field; Under the prerequisite of spirit that does not break away from the present invention and disclosed and scope; Can do any modification and variation what implement in form and on the details; But scope of patent protection of the present invention still must be as the criterion with the scope that appending claims was defined.
Claims (13)
1. a clock recovery circuitry device comprises the data pre-process circuit, clock recovery circuitry and the control circuit that connect successively, it is characterized in that:
The data pre-process circuit is used for converting the traffic spike that receives into standard digital signals, and exports to clock recovery circuitry;
Clock recovery circuitry; Be used for through the oscillator clocking; From said standard digital signals, obtain frequency information, obtain control signal, clock signal is calibrated in the accuracy rating that meets the demands according to this control signal by the difference of actual frequency that obtains and target frequency;
Control circuit is used for the calibration process of opening and closing clock recovery circuitry, and configurable clock generator recovers relevant parameters.
2. according to the described device of claim 1, it is characterized in that said clock recovery circuitry comprises testing circuit, calibration pulse generative circuit, counter circuit, calibration circuit and the parameter tunable oscillator circuit that connects successively, wherein:
Testing circuit connects the parameter tunable oscillator circuit, is used for according to detected time information generating detection signal, and exports to the calibration pulse generative circuit;
The calibration pulse generative circuit is used for producing a plurality of calibration pulse signals according to said detection signal, with the opening and closing of timesharing control counter circuit;
Counter circuit is used under the timesharing control of two calibration pulse signals, said clock signal being counted, and count value is exported to calibration circuit;
Calibration circuit is used under the control of said control circuit the difference according to the parameter value of said count value and local maintenance, is the control signal of M position to parameter tunable oscillator circuit output data width, and said M is a positive integer;
The parameter tunable oscillator circuit is used for producing said clock signal and exporting to testing circuit sum counter circuit respectively through oscillator, calibrates the frequency of clock signal by turn according to the control signal of said M position;
The parameter of said control circuit configuration comprises the reference value of counter circuit and the figure place that control signal is participated in calibration.
3. according to the described device of claim 2, it is characterized in that said testing circuit also is connected with said counter circuit, wherein:
The synchronization signal detection of utilizing said testing circuit produces said detection signal after arriving last bit of PID Packet Identifier, when exporting to said calibration pulse generative circuit, also exports to said counter circuit;
Said counter circuit is counted said clock signal under the control of two detection signals in course of normal operation; And count value exported to calibration circuit, whether clock signal is calibrated according to the difference decision of the parameter value of this count value and local maintenance by this calibration circuit.
4. according to the described device of claim 3, it is characterized in that said testing circuit comprises data recovery circuit and detection signal statement circuit, wherein:
Said data pre-process circuit is connected with data recovery circuit, converts the differential signal of a pair of usb data that receives into standard reverse non-return-to-zero signal, and exports to data recovery circuit;
Data recovery circuit is connected with said parameter tunable oscillator circuit, is used for according to said clock signal the reverse non-return-to-zero signal of said standard being decoded, and sends the numeric string that produces to detection signal statement circuit;
Detection signal statement circuit produces circuit with said calibration pulse and is connected, and is used for the detection signal of each generation according to the digital signal of said data recovery circuit transmission, and exports to said calibration pulse generation circuit or said counter circuit;
Said counter circuit is opened after receiving first calibration pulse signal or first detection signal said clock signal counting; After receiving next calibration pulse signal or next detection signal, close the counting to said clock signal, the count value of exporting between adjacent calibration pulse signal or adjacent detection signal is given said calibration circuit;
It is L that calibration circuit is set control signal adjustment figure place through said control circuit, said L≤M, and the L position with said control signal is changed to 0 entirely earlier; According to more said one by one count value in the L position of said control signal and said reference value,, then successively the corresponding positions of the control signal of L position is adjusted into 1 if said count value is greater than said reference value; If said count value is less than or equal to said reference value, then successively the corresponding positions of the control signal of said L position is adjusted into 0; Lowest order until said L position has been adjusted, and produces look-at-me and gives said control circuit, simultaneously the control signal of M position is exported to said parameter tunable oscillator circuit;
Said parameter tunable oscillator is according to the control signal of said M the position frequency of alignment oscillator clock signal, that is: f by turn
CLOCK=k
0* f+k
1* f+......+k
M* f, said f is the frequency signal of oscillator benchmark, said k
M=0 or 1.
5. according to each described device of claim 1 to 4, it is characterized in that, also comprise the functional circuit of the said parameter tunable oscillator circuit of utilization, be used to use said clock signal to realize the application corresponding function through calibration through the clock signal of calibration.
6. a clock recovery method relates to clock recovery circuitry device as claimed in claim 1, and this method comprises:
Clock recovery circuitry is through the internal oscillator clocking; Obtain frequency information in the standard digital signals according to reception of data pre-process circuit and conversion; Difference by actual frequency that obtains and target frequency is obtained control signal, according to this control signal said clock signal is calibrated in the accuracy rating that meets the demands.
7. according to the described method of claim 6, it is characterized in that, before said method is carried out, also comprise:
Behind clock recovery circuitry device electrification reset, said control circuit is opened said clock recovery circuitry, disposes relevant parameters simultaneously.
8. according to the described method of claim 7; It is characterized in that; Obtain frequency information in the standard digital signals that said clock recovery circuitry receives and changes according to the data pre-process circuit; Difference by actual frequency that obtains and target frequency is obtained control signal, according to this control signal clock signal is calibrated in the accuracy rating that meets the demands, and specifically comprises:
Said data pre-process circuit converts said differential signal the reverse non-return-to-zero signal with usb data numerical coding form of standard into, and exports to said clock recovery circuitry after receiving the differential signal of two-way usb data;
Said clock recovery circuitry passes through testing circuit according to detected time information generating detection signal; Produce a plurality of calibration pulse signals through the calibration pulse generative circuit according to said detection signal; Through counter circuit in calibration process under the timesharing of two calibration pulse signals control, said clock signal is counted; Through the difference of calibration circuit according to the reference value of the count value of counter circuit and local maintenance, the output data width is the control signal of M position, and said M is a positive integer; Calibrate the frequency of clock signal by turn according to the control signal of said M position through the parameter tunable oscillator circuit.
9. according to the described method of claim 8, it is characterized in that said testing circuit specifically comprises according to detected time information generating detection signal:
Said testing circuit utilizes synchronization signal detection behind last bit of PID Packet Identifier, to produce detection signal, as the sign output that detects the start frame packet.
10. according to claim 8 or 9 described methods, it is characterized in that, also comprise:
Counter circuit is counted said clock signal under the timesharing control of two detection signals in course of normal operation; And count value exported to said calibration circuit; By the difference of this calibration circuit according to the reference value of this count value and local maintenance, whether decision gets into the calibration process to clock signal.
11., it is characterized in that said counter circuit is counted said clock signal, specifically comprises according to the described method of claim 10 under the timesharing control of two calibration pulse signals or two detection signals:
Said counter circuit is opened the counting to said clock signal after receiving first calibration pulse signal or first detection signal; After receiving next calibration pulse signal or next detection signal, close counting, and export the count value between adjacent calibration pulse signal or the adjacent detection signal said clock signal.
12., it is characterized in that said calibration circuit is according to the difference of the reference value of the count value of counter circuit and local maintenance according to the described method of claim 11, the output data width is the control signal of M position, specifically comprises:
It is L that said calibration circuit is set control signal adjustment figure place through said control circuit, said L≤M, and the L position with said control signal is changed to 0 entirely earlier; According to more said one by one count value in the L position of said control signal and said reference value,, then successively the corresponding positions of the control signal of L position is adjusted into 1 if said count value is greater than said reference value; If said count value is less than or equal to said reference value, then successively the corresponding positions of the control signal of said L position is adjusted into 0; Lowest order until said L position has been adjusted, and produces look-at-me and gives said control circuit, simultaneously the control signal of M position is exported to said parameter tunable oscillator circuit.
13., it is characterized in that said parameter tunable oscillator circuit is calibrated the frequency of clock signal by turn according to the control signal of said M position, specifically comprises according to the described method of claim 12:
Said parameter tunable oscillator is according to the control signal of said M the position frequency of alignment oscillator clock signal, that is: f by turn
CLOCK=k
0* f+k
1* f+......+k
M* f, said f is the frequency signal of oscillator benchmark, said k
M=0 or 1.
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| CN111819787B (en) * | 2020-01-03 | 2023-12-15 | 深圳市汇顶科技股份有限公司 | Crystal calibration method, chip and Bluetooth headset |
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| CN113552920B (en) * | 2021-08-03 | 2023-05-09 | 中科芯集成电路有限公司 | Clock recovery system circuit |
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