CN101986613A

CN101986613A - All-purpose asynchronous serial communication controller

Info

Publication number: CN101986613A
Application number: CN 201010263970
Authority: CN
Inventors: 刘泽响; 翟雯艳; 吉伟
Original assignee: 771 Research Institute of 9th Academy of CASC
Current assignee: 771 Research Institute of 9th Academy of CASC
Priority date: 2010-08-26
Filing date: 2010-08-26
Publication date: 2011-03-16
Anticipated expiration: 2030-08-26
Also published as: CN101986613B

Abstract

The invention discloses an all-purpose asynchronous serial communication controller. The controller comprises a bidirectional IO processing module, a PCI secondary controller, an interior bus interface, interrupt management, and 1 to 8 channels UART control module, wherein the bidirectional IO processing module is used for connecting an exterior bus signal with a signal of the PCI secondary controller and merging the corresponding input output signals of the PCI secondary controller into a bidirectional signal of the PCI bus. The application coverage of the invention is wider than the controller of four channels. The depth for transceiving FIFO of each UART channel is 512 bytes and the processor access frequency is at least reduced by 4 times of the industrial controller. The controller supports sharing the 485 bus communication and receiving the enable control and is flexible to use. The processor interface is PCI bus, the integrated level is high which is beneficial to integrate a system, and the data throughput rate is high, and the highest data throughput rate reaches to 132MB/s.

Description

A kind of universal asynchronous serial communication controller

Technical field:

The invention belongs to universal asynchronous serial data communication field, relate to a kind of universal asynchronous serial communication controller, especially a kind of universal asynchronous serial communication controller that comprises pci interface and multichannel UART control module.

Background technology:

The widely used universal asynchronous serial communication controller major part of industry is a chip inlet, ST16C554, ST16C654, XR16C854 and XR16C864 etc. as EXAR company, this type of chip faces following problem in actual use: the one, and port number mostly is 4 most, the port number that needs when system is greater than 4, and monolithic can't meet the demands; The 2nd, the transmitting-receiving FIFO degree of depth is 128 bytes to the maximum, and processor access is frequent relatively; The 3rd, receive the FIFO filp-flop stage and be fixed as 4 grades, flexibility is relatively poor relatively; The 4th, processor interface is an asynchronous bus, and data throughput is not high, and when using in the CPCI system, needs extra pci controller, and integrated level is low.

High-throughput UART interface (United States Patent (USP) 7191262) is expanded 1 tunnel auxiliary transceiver channel on industrial standard 16550 bases, increased and subsystem between throughput, but the performance of UART passage does not promote; A kind of asynchronous serial communication control device (Chinese patent CN101122894A) can be realized multi-channel data communication, finishes the function of serial data route switching, but can not use as general purpose controller; Asynchronous communication controller (Chinese patent CN201349219Y) provides 485 data communication frame address identification and the automatic controlled function of transmit-receive position automatically, but the controller versatility is poor, and performance is limited; Asynchronous serial data line information transceiving method and asynchronous serial transceiver (Chinese patent CN101383819A) propose the method and corresponding asynchronous serial transceiver of the non-character information of a kind of quantitative transmitting-receiving, and function is special-purpose relatively, can not use as general purpose controller.

Universal asynchronous serial communication controller of industry and relevant patent achievement can not satisfy high-performance, miniaturized system application demand.

Summary of the invention:

The present invention is directed to requirement in practical systems, and the deficiency of existing controller and achievement, propose a kind of multichannel, big metadata cache, use universal asynchronous serial communication controller flexible, high-throughput.

The objective of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of universal asynchronous serial communication controller is provided, and this controller is made of two-way IO processing module, PCI slave controller, internal bus interface, interrupt management, a passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and eight passage UART control modules; Described two-way IO processing module is used to realize the interface of external pci bus signal and inner PCI slave controller signal, the corresponding input/output signal of PCI slave controller is merged into the two-way signaling of pci bus; Described PCI slave controller module is used to realize the agreement control of pci bus, converts the pci bus operation to local bus operation, finishes the exchanges data with pci bus; Described internal bus interface module is used for the bus on chip operation of standard that the operation of PCI slave controller local bus is converted to, and the interrupt management module, a passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and the eight passage UART control modules that are connected on the bus on chip are carried out the addressing visit; Described interrupt management module is used for 8 tunnel of a passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and the output of eight passage UART control modules is interrupted managing, and interruption exported to the PCI slave controller, with the break in service of application pci bus; A described passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and eight passage UART control modules are respectively applied for the agreement control that each UART channel data is communicated by letter.

A described passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules are identical with the structure of eight passage UART control modules, all be by internal bus interface, control/status register, send control, receive control, baud rate clock generating, Modem control, interruption controls, transmission FIFO, send shift register, receive FIFO, reception shift register and 485 control modules constitute; Described internal bus interface module is used for realizing and the external data exchange; Described control/status register module is used to be provided with functions of modules, and returns operating state; Described transmission control module is added start bit, check bit sum position of rest according to the data format setting to byte data, forms to send character, and is provided with according to the data baud rate, and control sends character data and exported by transmit port; Described reception control module is used to monitor receiving-end state, when sampling effective start bit, begins to receive data, and finishes the storage of verification and valid data, if when detecting verification mistake, frame mistake or Break condition, and preservation state; Described baud rate clock generating module is carried out frequency division according to the frequency division setting to system clock, produces the baud rate clock, is used for data and sends and receive; Described Modem control module is used for the generation and the status monitoring of Modem control signal; Described interruption controls module is finished the generation and the removing of interruption according to interruption masking setting and module operating state; Described transmission FIFO is the transmission data buffering of 512 bytes; Described transmission shift register is used for current transmission byte data serial shift output; Described reception FIFO is the reception data buffering of 512 bytes, and provides 3 error flag for each unit; Described reception shift register is used for the input of the data shift on the serial ports is realized string and conversion; Described 485 control modules are exported effective direction control signal according to controller state when sending data, when being used for shared bus communication, and the control of external transceiver output triple gate, and reception enables control.

Universal asynchronous serial communication controller of the present invention, its function specifically comprises: 33M/32 position pci bus interface, eight passage high-performance UART data communication and internal interrupt management etc. are provided.

Inner each the UART passage of controller is separate, but function is identical, specifically comprises: 512 bytes send FIFO; 512 bytes receive FIFO (each unit also has 3 bit-errors signs); Support transmission/reception FIFO to reset; Receive the FIFO filp-flop stage and have fixing and self-defined two kinds of configuration modes; Independently send and receive control; Serial data format (data bit can be set to 5,6,7 or 8 bit wides, and position of rest can be set to 1,1.5 or 2 bit wides) able to programme; Data check (no parity check, odd, even parity check or four kinds of forms of adhesion verification) able to programme; The data baud rate is able to programme; Support Modem signal controlling and detection; Support multiple error condition report (receive that FIFO overflows, verification mistake and frame mistake); Support the Break condition to produce and detection; Support inner self-looped testing; Support 5 types of interruptions (receive line states, receive data effective, overtime, send buffering sky and Modem state); Simple interruption masking and management function are provided; Support the control of 485 half-duplex data communication and direction; Provide 485 receptions to enable control etc.

In order to realize above-mentioned functions, controller mainly is made up of 12 modules, specifically comprises: two-way IO processing, PCI slave controller, internal bus interface, interrupt management, UART control module 1-8.Two-way IO processing module is mainly used in the interface of realizing external pci bus signal and inner PCI slave controller signal, the corresponding input/output signal of PCI slave controller is merged into the two-way signaling of pci bus; PCI slave controller module is mainly used in the agreement control that realizes pci bus, converts the pci bus operation to local bus operation, finishes the exchanges data with pci bus; The internal bus interface module is mainly used in the bus on chip operation of standard that the operation of PCI slave controller local bus is converted to, and interrupt management module and the UART control module 1-8 that is connected on the bus on chip carried out the addressing visit; The interrupt management module is mainly used in interrupts managing to 8 tunnel of UART control module 1-8 output, and the PCI slave controller is exported in interruption, with the break in service of application pci bus; UART control module 1-8 mainly is respectively applied for the agreement control of each UART channel data communication.

The UART control module is as the core that realizes universal asynchronous serial communication, mainly form, specifically comprise: internal bus interface, control/status register, transmission control, reception control, baud rate clock generating, Modem control, interruption controls, transmission FIFO, transmission shift register, reception FIFO, reception shift register, 485 controls by 12 submodules.The internal bus interface module is mainly used in and realizes and the external data exchange; Control/status register module is mainly used in functions of modules is set, and returns operating state; Send control module mainly according to the data format setting, add start bit, check bit sum position of rest to byte data, form the transmission character, and be provided with according to the data baud rate, control sends character data and is exported by transmit port; Receive control module and be mainly used in the monitoring receiving-end state, when sampling effective start bit, begin to receive data, and finish verification and valid data storage, if when detecting verification mistake, frame mistake or Break condition, preservation state; Baud rate clock generating module is carried out frequency division mainly according to the frequency division setting to system clock, produces the baud rate clock, is used for data and sends and receive; The Modem control module is mainly used in the generation and the status monitoring of Modem control signal; The interruption controls module is finished the generation and the removing of interruption mainly according to interruption masking setting and module operating state; Sending FIFO is the transmission data buffering of 512 bytes; Sending shift register is used for current transmission byte data serial shift output; Receiving FIFO is the reception data buffering of 512 bytes, and provides 3 error flag for each unit; Receiving shift register is used for the input of the data shift on the serial ports is realized string and conversion; 485 control modules are exported effective direction control signal mainly according to controller state when sending data, when being used for shared bus communication, and the control of external transceiver output triple gate, and reception enables control etc.

The effect that the present invention can reach specifically comprises:

(1) the UART port number is 8 among the present invention, and it is wider than the controller of four-way to use coverage rate;

(2) the transmitting-receiving FIFO degree of depth of each UART passage is 512 bytes among the present invention, and processor access frequency ratio industry controller reduces by 4 times at least;

(3) receiving the FIFO filp-flop stage among the present invention and can be fixed as 4 grades, can be 0-511 by User Defined also, and supports shared 485 bus communications and reception to enable control, uses flexibly;

(4) processor interface is a pci bus among the present invention, the integrated level height, is easy to the system integration, and the data throughput height, is up to 132MB/s.

Description of drawings:

Fig. 1 is the structured flowchart of middle controller of the present invention;

Fig. 2 is the structured flowchart of UART module in the controller of the present invention.

Embodiment:

Below in conjunction with accompanying drawing the present invention is done and to describe in further detail:

Referring to Fig. 1,2,, design detailed implementation according to content of the present invention.

Controller architecture as shown in Figure 1,1 is two-way IO processing module, 2 is PCI slave controller module, 3 is the internal bus interface module, 4 is the interrupt management module, 5 is a passage UART control module, 6 is two passage UART control modules, 7 is triple channel UART control module, 8 is four-way UART control module, 9 is five-way road UART control module, 10 is six passage UART control modules, 11 is seven passage UART control modules, 12 is eight passage UART control modules, 13 is the pci bus signal, 14 is the internal bus signal, 15 is a passage UART interface signal, 16 is two passage UART interface signals, 17 is triple channel UART interface signal, 18 is four-way UART interface signal, 19 is five-way road UART interface signal, 20 is six passage UART interface signals, 21 is seven passage UART interface signals, 22 is eight passage UART interface signals.

Controller is mutual by pci bus signal 13 and exterior PC I main equipment; The part signal of 1 pair of PCI slave controller of two-way IO processing module module 2 carries out two-way processing, and is connected with outside by pci bus signal 13; The local bus of PCI slave controller module 2 and the bridge joint of internal bus signal 14 are then realized by internal bus interface module 3; 12 of interrupt management module 4, a passage UART control module 5, two passage UART control modules 6, triple channel UART control module 7, four-way UART control module 8, five-way road UART control module 9, six passage UART control modules 10, seven passage UART control modules 11 and eight passage UART control modules are connected with internal bus interface module 3 by internal bus signal 14; One passage UART control module 5, two passage UART control modules 6, triple channel UART control module 7, four-way UART control module 8, five-way road UART control module 9, six passage UART control modules 10, seven passage

UART control modules

11 and 12 outputs of eight passage UART control modules are interrupted by 4 unified managements of interrupt management module, and export to PCI slave controller module 2; UART passage 1-8 is respectively by a passage UART control module 5, two passage UART control modules 6, triple channel UART control module 7, four-way UART control module 8, five-way road UART control module 9, six passage UART control modules 10, seven passage UART control modules 11 and eight passage UART control modules 12 are by a passage UART interface signal 15, two passage UART interface signals 16, triple channel UART interface signal 17, four-way UART interface signal 18, five-way road UART interface signal 19, six passage UART interface signals 20, seven passage UART interface signals 21, eight passage UART interface signals 22 are connected with outside transmission circuit.

The main effect of two-way IO processing module 1, PCI slave controller module 2 and internal bus interface module 3 is to convert the pci bus operation to the internal bus operation, and this part logic designs according to PCI V2.1 and Wishbone VB.3 standard criterion; Interrupt management module 4 is eight passage interrupt managements, adopts compatible A8259 design.

One passage UART control module 5, two passage UART control modules 6, triple channel UART control module 7, four-way UART control module 8, five-way road UART control module 9, six passage UART control modules 10, seven passage UART control modules 11 are identical with the structure of eight passage UART control modules 12, as shown in Figure 2,23 is the internal bus interface module, 24 for sending control module, 25 is the transmission FIFO of 512 bytes, 26 for sending shift register, 27 is baud rate clock generating module, 28 is the reception FIFO of 512 bytes, 29 for receiving shift register, 30 for receiving control module, 31 are control/status register module, 32 is the interruption controls module, 33 is the Modem control module, 34 is 485 control modules, 35 is the serial ports transmitting terminal, 36 are the output of baud rate clock, 37 is the serial ports receiving terminal, 38 are Modem transmission request signal, 39 is Modem DTR signal, 40 are Modem permission transmission signal, 41 are ready to signal for the Modem data set, 42 is Modem jingle bell id signal, 43 is Modem data medium detection signal, 44 is 485 output enable signals.

27 the settings of baud rate clock generating module according to control/status register module 31, clock in the inner bus signals 14 is carried out frequency division, produce the baud rate clock that needs, by baud rate clock output 36 outputs, and offer to receive control module 30 and send control module 24 and be used for the serial data transmitting-receiving; Data to be sent deposit the transmission FIFO 25 of 512 bytes in by internal bus signal 14, internal bus interface module 23, send the relative set of control module 24 according to control/status register module 31, the transmission FIFO 25 top layer data of 512 bytes are got in the transmission shift register 26, add corresponding start bit, check bit sum position of rest, by sending shift register 26 serial shifts by 35 outputs of serial ports transmitting terminal; Receive the relevant setting of control module 30 according to control/status register module 31, by receiving shift register 29 serial ports receiving terminal 37 input signals are detected, and valid data are deposited in the reception FIFO 28 of 512 bytes, the various states that DRP data reception process produces deposit relevant register in control/status register module 31 in, and the valid data among the reception FIFO 28 of 512 bytes are read by internal bus signal 14 and internal bus interface module 23; The outside can conduct interviews by internal bus signal 14 and 23 pairs of control/status register module 31 internal registers of internal bus interface module; Interruption controls module 32 is according to register-bit state in the control/status register module 31, by internal bus interface module 23 and internal bus signal 14 output interrupt requests; Modem control module 33 is according to corresponding registers position state in the control/status register module 31, output Modem sends request signal 38 and Modem DTR signal 39, and detection Modem allows to send signal 40, the Modem data set is ready to signal 41, Modem jingle bell id signal 42 and Modem data medium detection signal 43 states, deposits relevant register in control/status register module 31 in; 485 control modules 34 are provided with and transmit status according to control/status register module 31, by 485 output enable signals, 44 controls, 485 output enables.

According to such scheme, be described with of the logical design of Verilog HDL language, and completion logic is comprehensive and placement-and-routing to controller; Simultaneously, design a CPCI witness plate, design of Controller is mapped in the programmable logic device realizes, and the function of controller is tested.Test result shows that the present invention has good exploitativeness, and performance satisfies expection.

Above content is to further describing that the present invention did in conjunction with concrete preferred implementation; can not assert that the specific embodiment of the present invention only limits to this; for the general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by claims of being submitted to.

Claims

1. universal asynchronous serial communication controller, it is characterized in that: this controller is made of two-way IO processing module, PCI slave controller, internal bus interface, interrupt management, a passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and eight passage UART control modules; Described two-way IO processing module is used to realize the interface of external pci bus signal and inner PCI slave controller signal, the corresponding input/output signal of PCI slave controller is merged into the two-way signaling of pci bus; Described PCI slave controller module is used to realize the agreement control of pci bus, converts the pci bus operation to local bus operation, finishes the exchanges data with pci bus; Described internal bus interface module is used for the bus on chip operation of standard that the operation of PCI slave controller local bus is converted to, and the interrupt management module, a passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and the eight passage UART control modules that are connected on the bus on chip are carried out the addressing visit; Described interrupt management module is used for 8 tunnel of a passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and the output of eight passage UART control modules is interrupted managing, and interruption exported to the PCI slave controller, with the break in service of application pci bus; A described passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules and eight passage UART control modules are respectively applied for the agreement control that each UART channel data is communicated by letter.

2. a kind of according to claim 1 universal asynchronous serial communication controller, it is characterized in that: a described passage UART control module, two passage UART control modules, triple channel UART control module, four-way UART control module, five-way road UART control module, six passage UART control modules, seven passage UART control modules are identical with the structure of eight passage UART control modules, all are by internal bus interface, control/status register, send control, receive control, the baud rate clock generating, Modem control, interruption controls, send FIFO, send shift register, receive FIFO, receiving shift register and 485 control modules constitutes; Described internal bus interface module is used for realizing and the external data exchange; Described control/status register module is used to be provided with functions of modules, and returns operating state; Described transmission control module is added start bit, check bit sum position of rest according to the data format setting to byte data, forms to send character, and is provided with according to the data baud rate, and control sends character data and exported by transmit port; Described reception control module is used to monitor receiving-end state, when sampling effective start bit, begins to receive data, and finishes the storage of verification and valid data, if when detecting verification mistake, frame mistake or Break condition, and preservation state; Described baud rate clock generating module is carried out frequency division according to the frequency division setting to system clock, produces the baud rate clock, is used for data and sends and receive; Described Modem control module is used for the generation and the status monitoring of Modem control signal; Described interruption controls module is finished the generation and the removing of interruption according to interruption masking setting and module operating state; Described transmission FIFO is the transmission data buffering of 512 bytes; Described transmission shift register is used for current transmission byte data serial shift output; Described reception FIFO is the reception data buffering of 512 bytes, and provides 3 error flag for each unit; Described reception shift register is used for the input of the data shift on the serial ports is realized string and conversion; Described 485 control modules are exported effective direction control signal according to controller state when sending data, when being used for shared bus communication, and the control of external transceiver output triple gate, and reception enables control.