CN101937412B - System on chip and access method thereof - Google Patents
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Abstract
The invention provides a system on chip and an access method thereof. The system on chip comprises an OSB (Oriented Shaving Board) as well as a master device and a slave device which are connected on the OSB, wherein the master device is used for sending an access request for requesting accessing the slave device to the OSB; the OSB is used for sending the access request from the master device to the slave device and sending the results of relevant operations performed by the slave device according to the access request to the master device; and the slave device is used for performing relevant operations according to the access request and sending the results of the relevant operations to the OSB. The simultaneous working of sufficient different bus control modules is supported on same bus system by reducing the access efficiency of each bus control module, no conflict occurs, and no instantaneous bus efficiency reduction is produced; thus, the problems of complex bus structure and difficult realization existing in relevant technologies are solved.
Description
Technical Field
The invention relates to the field of communication and chip design, in particular to a universal system on a chip and implementation of a bus structure in the universal system on a chip.
Background
With the continuous improvement of integrated circuit technology, SOC (system on chip) becomes possible. In a typical system on chip, a control module (CPU) and a functional module (a coprocessor or a dedicated functional module) exist on the same chip, which needs to solve the problems of interconnection and data transfer of the control module and the functional module in the system on chip, i.e. the design of an on-chip bus. This problem is similar to the control and data transfer in computers via PCI bus. In the bus technology, different systems on chip or embedded CPUs have different bus structures, which depends on the data structure of the CPU, the data transmission throughput to be realized, and the requirement for real-time performance. For example, in order to ensure the operation of the bus under different system architectures and application conditions, the bus architecture and communication method designed by the ARM corporation are very complex and difficult to be compatible with other bus systems, although they have strong versatility. Meanwhile, the complex ASIC chip also has the requirement on a bus structure, but the bus structure is not well applied.
ASIC chips generally have one or more complex functional modules, while control modules are generally off-chip, which also have the need for control and data transfer between the different modules of the SOC chip. Therefore, the ASIC chip can have the advantages of modular design, analysis and realization as the SOC chip by introducing the bus system, the development cycle of the ASIC chip is shortened finally, the chip can realize modular design and verification, and the reusability of the module is enhanced.
In addition, even in the SOC chip, most of the bus applications are low-efficiency control layer applications, and a complex bus system does not play a real role, but makes development difficulty increase and consumes more hardware resources.
In summary, in the process of implementing the present invention, the inventors found that at least the following problems exist in the prior art:
1. the bus structure is complex and is not easy to realize;
2. the method is only suitable for an SOC chip, is difficult to realize in an ASIC chip and can generate the waste of hardware resources;
3. the structure and the generalization are not strong, a plurality of modules can be separately designed and verified, and the independent design and verification are difficult due to the limitation of a bus structure;
4. because the bus system designed for the SOC chip has complex requirements on the number of the main control modules and arbitration after competition, the bus system is not beneficial to the design of general chips;
5. collisions between the master control modules may cause a reduction in access efficiency and may cause erroneous operations.
Disclosure of Invention
The invention aims to provide a system on a chip and an access method thereof, which can solve the problems of complex bus structure and difficult realization in the related technology.
According to an aspect of the present invention, there is provided a system on a chip, including: OSB, and master device and slave device connected to the OSB, wherein: the master device is used for sending an access request for requesting to access the slave device to the OSB; the OSB is used for sending an access request from the master equipment to the slave equipment and sending a result of corresponding operation performed by the slave equipment according to the access request to the master equipment; and the slave equipment is used for carrying out corresponding operation according to the access request and sending the result of the corresponding operation to the OSB.
Further, in the above system on chip, the master and the slave are in a peer-to-peer relationship.
Further, in the above system on chip, the method further includes: and a bridge unit connected between the host device and the OSB, for converting a protocol of an access request from the host device into an OSB protocol, and transmitting the access request converted into the OSB protocol to the OSB.
Further, in the above system on chip, there are a plurality of master devices and a plurality of slave devices, respectively.
Further, in the above system on chip, the method further includes: the arbiter is used for receiving the access request sent by the master device through the OSB and analyzing the access request to obtain the number of the slave device to be accessed, wherein the number is carried in the access request; and establishing a data channel between the master device and the slave device to be accessed indicated by the number.
Further, in the above system on chip, the arbiter comprises: the queue arbitration module is used for queuing the access requests from the plurality of main devices, and analyzing each access request in the queue in sequence to obtain the number of the slave device to be accessed, which is carried in each access request; and the channel distribution module is used for sending an instruction to the slave equipment to be accessed according to the number analyzed by the queue arbitration module so as to activate the slave equipment and perform corresponding operation, and establishing a data channel between the master equipment and the slave equipment to be accessed.
Further, in the above system on chip, the master device communicates with the OSB through the master device and the OSB interface, and the slave device communicates with the OSB through the slave device and the OSB interface; wherein, the master device and the OSB interface comprise at least one of the following: the address port is used for indicating the number of the slave device and the access space of the slave device; an operation result receiving port for indicating that a result of the corresponding operation returned from the device is success or failure; the access port is used for enabling the access request and indicating that the access is a read operation and/or a write operation; a first output operation data port for outputting operation data to the slave device; and a second input operation data port for receiving operation data transmitted from the device;
the slave device interfacing with the OSB includes at least one of: an enable port for indicating a slave device to be enabled; the access space port is used for indicating the access space of the slave equipment to be accessed, and the access space is matched with the access space in the address port; a read/write operation port for enabling read/write operations of the slave device; the operation result return port is used for returning the result of the corresponding operation to the main equipment as success or failure; a second output operation data port for outputting operation data to the master device; and the second input operation data port is used for receiving the operation data sent by the master equipment.
According to another aspect of the present invention, there is also provided a bus access method of a system on a chip, including the steps of: the master device sends an access request for requesting access to the slave device to the open shared bus OSB; the OSB sends an access request to the slave equipment; and the slave equipment performs corresponding operation according to the access request, and sends the result of the corresponding operation to the master equipment through the OSB.
Further, the master device sending an access request for accessing the slave device to the open shared bus OSB includes: the master device sends an access request to the bridge unit; the bridge unit converts the protocol of the access request to the OSB protocol and sends the access request converted to the OSB protocol to the OSB.
Further, the OSB sending the access request to the slave device includes: the OSB sends the access request to the arbiter; the arbiter analyzes the access request to obtain the serial number of the slave equipment to be accessed, wherein the serial number is carried in the access request; the arbiter establishes a data channel between the master device and the slave device to be accessed as indicated by the number according to the number.
In the invention, because the different points and the same points of the SOC and the ASIC chip are fully considered, the structure of the chip is greatly improved through the optimization design of the bus, so that a bus system becomes an important link for improving the efficiency. The low-efficiency general bus structure has enough capacity of controlling data transmission, can support enough different bus control modules to work simultaneously on the same bus system by reducing the access efficiency of each bus control module, does not conflict and does not generate instantaneous bus efficiency reduction, thereby solving the problems of complex bus structure and difficult realization existing in the related technology.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 shows a schematic architectural diagram of a system on chip according to one embodiment of the invention;
FIG. 2 is a block diagram of a system on chip having an arbiter according to another embodiment of the present invention;
FIG. 3 shows a bit-mapped representation of an Osbm _ op _ addr port according to an embodiment of the invention;
FIG. 4 illustrates a timing diagram of a master read operation according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating a master write operation according to an embodiment of the present invention;
FIG. 6 illustrates a timing diagram for a slave device write operation according to an embodiment of the present invention;
FIG. 7 illustrates a timing diagram for a read operation from a device according to an embodiment of the invention;
FIG. 8 is a flowchart illustrating a bus access method of a system on chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
FIG. 1 shows a schematic architectural diagram of a system-on-chip having a bus structure according to one embodiment of the present invention, including: an OSB (Open-Shared-Bus) 10, and a master device 20 and a slave device 30 connected to the OSB 10, wherein: a master device 20 for transmitting an access request requesting access to the slave device 30 to the OSB 10; the OSB 10 is configured to send the access request from the master device 20 to the slave device 30, and send a result of a corresponding operation performed by the slave device 30 according to the access request to the master device 20; the slave device 30 is configured to perform the corresponding operation according to the access request, and send a result of the corresponding operation to the OSB 10.
In the embodiment, different points and the same points of the SOC and the ASIC chip are fully considered, and the structure of the chip is greatly improved through the optimization design of the bus, so that a bus system becomes an important link for improving the efficiency. The low-efficiency general bus structure has enough capacity of controlling data transmission, can support enough different bus control modules to work simultaneously on the same bus system by reducing the access efficiency of each bus control module, does not conflict and does not generate instantaneous bus efficiency reduction, thereby solving the problems of complex bus structure and difficult realization existing in the related technology.
In the system on chip of the above embodiment, the master device 20 and the slave device 30 are in a peer-to-peer relationship. That is, only the accessed device is defined as the master device and the accessed device is defined as the slave device, and therefore, it is obvious that the roles of the master device and the slave device of one device can be switched at any time, or both roles can be provided. Here, it is worth noting here that the master and slave devices may be any type of device.
Because the master device and the slave device are in a peer-to-peer relationship, any small module is separately and independently designed during module design, so that the problems that the structuralization and the generalization are not strong, a plurality of modules can be separately designed and verified, and the independent design and verification are difficult due to the limitation of a bus structure in the related technology are solved, and the generalization of the bus of the system on chip is further enhanced. In addition, the master device and the slave device are in a peer-to-peer relationship, and the problem of master control does not exist, so that the bus system in the related technology has complex requirements on the number of the master control modules and arbitration after competition is generated, and the problem that the design of a common chip is not facilitated is solved.
In practical implementation, as shown in fig. 1, the system on chip may further include a bridge unit 40 connected between the host device 20 and the OSB 10 (one host device corresponds to one bridge unit), and configured to convert the protocol of the access request from the host device 20 into the OSB protocol and send the access request converted into the OSB protocol to the OSB 10. Since the host device may be a device supporting various protocols, a bridge device is required for protocol conversion in order to be able to communicate with the OSB normally.
It is apparent that a plurality of masters 20 and a plurality of slaves 30 may be included in the above-described system-on-chip, as shown in fig. 1. Thus, when multiple master devices 20 and multiple slave devices 30 are connected to the OSB 10, how the OSB 10 can operate properly and efficiently becomes a problem to be solved. Therefore, in order to solve the problem, an arbiter 50 (the connection relationship between the master device, the bridge unit, the arbiter and the slave device is shown in fig. 2) may be provided between the master devices and the slave devices in the system on chip, where the arbiter 50 is configured to receive the access request sent by the master device 20 through the OSB 10, and analyze the access request to obtain the number of the slave device to be accessed, which is carried in the access request; and establishing a data channel between the master device sending the access request and the slave device to be accessed indicated by the obtained number.
Since the arbiter may receive multiple access requests from multiple masters, the arbiter 50 may use round robin as its arbitration mechanism. As shown in fig. 2, the arbiter 50 may specifically include a queue arbitration module 502 and a channel allocation module 504, where the queue arbitration module 502 is configured to queue access requests from a plurality of master devices 20, and sequentially analyze each access request in the queue to obtain a number of a slave device to be accessed, which is carried in each access request; a channel allocation module 504, configured to send an instruction to the slave device to be accessed according to the number analyzed by the queue arbitration module 502, so that the slave device is activated and performs a corresponding operation, and establish a data channel between the master device and the slave device to be accessed (i.e., allocate a bus resource for the access request).
In fig. 2, I2C _ slave (I2C slave), AUX-CH, and MCU are all masters. Firstly, the access request of the master device is converted into OSB protocol by the bridge unit, then arbitrated by the arbitrator, and finally sent to the corresponding slave device.
In the system on chip of the above embodiment, the master device 20 needs to wait for a response (i.e., the result of the above-described corresponding operation) until an indication signal of success or failure is returned. That is, the slave device 30 must return an indication of success or failure to the master device 20. That is, the OSB protocol is a non-destructive protocol. OSB does not support structures that exist exceptionally (i.e. does not support cases other than returning a success or failure indication). Therefore, the slave device needs to have a dedicated function to return a failure indication signal if it is busy. Therefore, the access conflict between the modules does not occur in the system on chip of the embodiment, thereby solving the problems that the conflict between the main control modules in the related art causes the reduction of the access efficiency and may cause the erroneous operation.
In order to implement the system on chip having the above bus structure, a communication interface between the master device and the OSB and a communication interface between the slave device and the OSB need to be defined, that is, the master device 20 and the OSB 10 communicate with each other through the master device and the OSB interface, and the slave device 30 and the OSB 10 communicate with each other through the slave device and the OSB interface; wherein,
as shown in table 1, the master device and OSB interface includes various ports, such as: the address port is used for indicating the number of the slave device and the access space of the slave device; an operation result receiving port for indicating that a result of the corresponding operation returned from the device is success or failure; the access port is used for enabling the access request and indicating that the access is a read operation and/or a write operation; a first output operation data port for outputting operation data to the slave device; and a second input operation data port for receiving operation data transmitted from the device.
TABLE 1
Table 1 shows the ports of the host device bridge interface including the arbiter. The width of the Osbm _ op _ addr port is 32 bits, as shown in fig. 3, wherein the upper 8 bits indicate the number of the slave device, and the last 24 bits indicate the specific address of the space to be accessed.
As shown in table 2, the slave device and OSB interface includes at least one of: an enable port for indicating a slave device to be enabled; the access space port is used for indicating the access space of the slave equipment to be accessed, and the access space is matched with the access space in the address port; a read/write operation port for enabling read/write operations of the slave device; the operation result return port is used for returning the result of the corresponding operation to the main equipment as success or failure; a second output operation data port for outputting operation data to the master device; and the second input operation data port is used for receiving the operation data sent by the master equipment.
TABLE 2
Table 2 shows the ports of the OSB slave device bridge interface with the arbiter. The operating address port op _ addr on the slave side has a bit width of 24 bits and is used for matching the access address of the master. Since the number bit width of the slave device is 8 bits, the OSB can support up to 256 slave devices. When a read operation starts, the port Osbs _ op _ ok _ n and the port Osbs _ n _ rd _ data should be set to valid bits simultaneously.
If the data Bit width of the control register is only 8 bits, the LSB (Least Significant Bit) needs to be used to match the read/write data bus, and other bits should be reserved or left blank in the IP.
Here, it is worth noting that: the bit width occupied by each port in table 1 and table 2 can be adjusted according to actual requirements in practical applications.
In one embodiment of the invention, three slaves are defined in the DP RX IP. Two of which are the initial I2C access registers and one is the DPCD register.
FIG. 4 is a timing diagram illustrating a read operation of a master device according to an embodiment of the present invention, and FIG. 5 is a timing diagram illustrating a write operation of a master device according to an embodiment of the present invention. When the master sends a request, the write/read operation will complete in two cycles if the slave is idle. If the slave is busy, the arbiter is unable to send requests to the slave until the slave is idle. In this case, the request needs to wait a long time until the slave is idle.
FIG. 6 shows a timing diagram of a write operation of a slave device according to an embodiment of the present invention, and FIG. 7 shows a timing diagram of a read operation of a slave device according to an embodiment of the present invention. All request signals (i.e. access requests) including the osbs _ slave _ sel must arrive at the slave device at the same time.
In conjunction with the system on chip shown in fig. 1, the bus access method of the system on chip is shown in fig. 8, and includes the following steps:
step S802, the master device sends an access request for requesting access to the slave device to an OSB (Open-Shared-Bus);
step S804, the OSB sends the access request to the slave device;
in step S806, the slave device performs a corresponding operation according to the access request, and sends the operation result to the master device through the OSB.
Preferably, in the above method, the sending, by the master device, the access request to the OSB includes: the master device sends an access request to the bridge unit; the bridge unit converts the protocol of the access request to the OSB protocol and sends the access request converted to the OSB protocol to the OSB.
Preferably, in the above method, the OSB sending the access request to the slave device includes: the OSB sends the access request to an arbiter; the arbiter analyzes the access request to obtain the serial number of the slave device to be accessed, which is carried in the access request; and establishing a data channel between the master equipment and the slave equipment to be sent indicated by the number according to the obtained number.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
the different points and the same points of the SOC and the ASIC chip are fully considered, the structure of the chip is greatly improved through the optimization design of the bus, and the bus system becomes an important link for improving the efficiency. The low-efficiency general bus structure has enough capacity of controlling data transmission, can support enough different bus control modules to work simultaneously on the same bus system by reducing the access efficiency of each bus control module, does not conflict and does not generate instantaneous bus efficiency reduction, thereby solving the problems of complex bus structure and difficult realization existing in the related technology.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, or they may be separately fabricated into various integrated circuit modules, or multiple modules or steps thereof may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A system on a chip, comprising: an open shared bus OSB, and a master device and a slave device connected to the OSB, wherein:
the master device is used for sending an access request for requesting to access the slave device to the OSB;
the OSB is used for sending the access request from the master device to the slave device and sending a result of corresponding operation performed by the slave device according to the access request to the master device;
the slave device is configured to perform the corresponding operation according to the access request, and send a result of the corresponding operation to the OSB;
the master device and the OSB communicate with each other through a master device and an OSB interface, and the slave device and the OSB communicate with each other through a slave device and an OSB interface; wherein,
the master device and OSB interface includes at least one of: an address port for indicating a number of the slave device and an access space of the slave device; an operation result receiving port, configured to indicate that a result of the corresponding operation returned by the slave device is success or failure; the access port is used for enabling the access request and indicating that the access is read operation and/or write operation; a first output operational data port for outputting operational data to the slave device; the second input operation data port is used for receiving the operation data sent by the slave equipment;
the slave device interfacing with the OSB includes at least one of: an enable port for indicating a slave device to be enabled; an access space port for indicating an access space of the slave device to be accessed, which matches the access space in the address port; a read/write operation port for enabling read/write operations of the slave device; an operation result return port for returning the result of the corresponding operation to the master device as success or failure; a second output operation data port for outputting operation data to the master device; and the second input operation data port is used for receiving the operation data sent by the main equipment.
2. The system on a chip of claim 1, wherein the master device and the slave device are in a peer-to-peer relationship.
3. The system on a chip of claim 1, further comprising:
and the network bridge unit is connected between the main equipment and the OSB and used for converting the protocol of the access request from the main equipment into an OSB protocol and sending the access request converted into the OSB protocol to the OSB.
4. The system on chip of claim 1, wherein the master device and the slave device are respectively plural.
5. The system on a chip of claim 4, further comprising:
the arbiter is used for receiving the access request sent by the master device through the OSB and analyzing the access request to obtain the number of the slave device to be accessed, wherein the number is carried in the access request; and establishing a data channel between the master device and the slave device to be accessed indicated by the number.
6. The system on a chip of claim 5, wherein the arbiter comprises:
the queue arbitration module is used for queuing the access requests from the plurality of main devices, and analyzing each access request in the queue in sequence to obtain the number of the slave device to be accessed, which is carried in each access request;
and the channel distribution module is used for sending an instruction to the slave equipment to be accessed according to the serial number analyzed by the queue arbitration module so as to enable the slave equipment to be activated and carry out the corresponding operation, and establishing a data channel between the master equipment and the slave equipment to be accessed.
7. A method for bus access in a system on a chip, comprising the steps of:
the master device sends an access request for requesting access to the slave device to the open shared bus OSB;
the OSB sends the access request to the slave device; and
the slave device performs corresponding operation according to the access request, and sends the result of the corresponding operation to the master device through the OSB, wherein,
the master device and the OSB communicate with each other through a master device and an OSB interface, and the slave device and the OSB communicate with each other through a slave device and an OSB interface;
the master device and OSB interface includes at least one of: an address port for indicating a number of the slave device and an access space of the slave device; an operation result receiving port, configured to indicate that a result of the corresponding operation returned by the slave device is success or failure; the access port is used for enabling the access request and indicating that the access is read operation and/or write operation; a first output operational data port for outputting operational data to the slave device; the second input operation data port is used for receiving the operation data sent by the slave equipment;
the slave device interfacing with the OSB includes at least one of: an enable port for indicating a slave device to be enabled; an access space port for indicating an access space of the slave device to be accessed, which matches the access space in the address port; a read/write operation port for enabling read/write operations of the slave device; an operation result return port for returning the result of the corresponding operation to the master device as success or failure; a second output operation data port for outputting operation data to the master device; and the second input operation data port is used for receiving the operation data sent by the main equipment.
8. The method of claim 7, wherein sending, by the master device, an access request for accessing the slave device to the Open Shared Bus (OSB) comprises:
the master device sends the access request to a bridge unit;
the bridge element converts the protocol of the access request to OSB protocol,
and sending the access request converted into the OSB protocol to the OSB.
9. The method of claim 7, wherein the OSB sending the access request to the slave device comprises:
the OSB sends the access request to an arbiter;
the arbiter analyzes the access request to obtain the number of the slave device to be accessed, wherein the number is carried in the access request;
and the arbiter establishes a data channel between the master device and the slave device to be accessed, which is indicated by the number, according to the number.
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN103218337B (en) * | 2013-03-13 | 2015-10-07 | 北京安拓思科技有限责任公司 | Based on wishbone bus realize main and master and slave with from the SOC (system on a chip) communicated and method |
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| CN106610906A (en) * | 2015-10-27 | 2017-05-03 | 深圳市中兴微电子技术有限公司 | Data access method and bus |
| CN107517167B (en) * | 2016-06-15 | 2020-04-14 | 华为技术有限公司 | Data transmission control method and device and SoC chip |
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| CN112949247B (en) * | 2021-02-01 | 2022-05-20 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
| CN114422290A (en) * | 2022-01-21 | 2022-04-29 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission device and communication system |
| CN115357926B (en) * | 2022-10-19 | 2023-03-24 | 南京芯驰半导体科技有限公司 | AXI bus protocol access authority control method and device based on SoC chip |
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