CN101127023A - Universal asynchronous serial extended chip of multi-bus interface - Google Patents
Universal asynchronous serial extended chip of multi-bus interface Download PDFInfo
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- CN101127023A CN101127023A CNA2006100216073A CN200610021607A CN101127023A CN 101127023 A CN101127023 A CN 101127023A CN A2006100216073 A CNA2006100216073 A CN A2006100216073A CN 200610021607 A CN200610021607 A CN 200610021607A CN 101127023 A CN101127023 A CN 101127023A
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Abstract
The utility model discloses a multi-bus interface extended chip with general asynchronous serial ports, comprising a host interface, a subchannel processing module, a MODEM control logic module, an interrupt control logic module and a clock generator. The utility model is characterized in that the host interface comprises a 8-bit parallel bus interface, a serial peripheral interface SPI bus interface, a UART bus interface, an internal integrated circuit bus I2C bus interface, a protocol processor, a global register and a mode selection control logic module, wherein the four bus interfaces are all connected with the CPU/DSP host and the bus type corresponding the host is selected through the bus processing logic, in addition, the data and the conversion of data format are processed through the bus processing logic. The working state of the host interface of the chip is setup by the global register and the mode selection, the mode selection control logic module selects the host interface and the signal line through mode. The utility model supports 8-bit parallel bus, SPI bus, I2C, UART and other host bus interfaces, realizes a plurality of extended serial ports for buses, besides, the utility model has compact and perfect configuration register structure and enables multi-working modes set of the sub serial ports independently, and supports high-speed communication, and each channel has independent and controllable data broadcasting and receiving function, and all UARTs support IRDA infrared communication.
Description
Technical field
The present invention relates to a kind of UART universal asynchronous serial expansion integrated circuit (IC) chip, particularly a kind of multibus host interface, subchannel can independently be provided with, built-in multibus protocol processor and the universal asynchronous serial extended chip of simplifying register architecture.
Background technology
Universal asynchronous serial transmitting-receiving interface UART (Universal Asynchronous Receiver/Transmitter) was born in for the 1970's, was widely used in computing machine at present, communication, Industry Control, household electrical appliance, every field such as consumer electronics.UART is first large scale integrated circuit, UART occurs several years ago just having produced at chip microprocessor, present UART with 30 years before compare, structure is similar substantially.
As a kind of general serial data bus, UART is mainly used in asynchronous communication.This bus two-way communication can realize full duplex transmission and reception.In embedded design, UART is used for communicating with PC, comprises and monitoring debugger and other device, communicates by letter as EEPROM.
UART has simple to operate, reliable operation, anti-interference strong, long transmission distance (forming 485 networks can transmit more than 1200 meters), the designer generally believes that UART is from central processor CPU or the microcontroller best mode to other parts transmission data of system, so they are applied in industry, communication, embedded and field of household appliances in large quantities.Because UART is easy to use, but and the facilitating chip design, the demand of UART is very vigorous always separately.
Up to now, there are 40 kinds of UART devices of surpassing to select in the global range, but inside sequential and the collaborative work that relates to more complicated handled because a plurality of UART work simultaneously, so present UART up to today its versatility, pin, register still seldom change, can really realize the very few of Full Featured UART expansion.Most of UART devices are application foundation with computer bus conversion UART, the ubiquity complicated operation, and pin is many, weakness such as cost height.
In Embedded Application, microprocessor controller MCU and peripheral communication substantially all adopt serial ports, and most of microprocessor controller MCU only are with a serial ports, and traditional serial ports expansion IC generally need take the IO of a large amount of MCU, is not suitable for being applied in the embedded system.Take the MCU resource and adopt more software simulation serial mode to exist now, shortcoming such as communication speed is slow, and it is unreliable to communicate by letter.
Summary of the invention
The objective of the invention is the development trend at UART in the embedded system, a kind of multibus host interface is provided, subchannel can independently be provided with, built-in multibus protocol processor and the asynchronous serial extended chip of simplifying register architecture.
Technical scheme of the present invention is as follows:
A kind of universal asynchronous serial extended chip of multi-bus interface, comprise host interface, subchannel processing module, MODEM control logic module, interrupt control logic module and clock generator, it is characterized in that: described host interface comprises 8 bit parallel bus interface, serial peripheral interface spi bus interface, UART bus interface, internal integrate circuit bus I
2C bus interface, protocol processor, global register and model selection control logic module; Described four kinds of bus interface all are connected with the CPU/DSP main frame, select the bus type of main frame correspondence by the bus processing logic, and pass through bus processing logic treatment S PI, UART, I
2The unified conversion of the data of C and 8 bit parallel buses and data layout; Described global register is provided with the host interface duty of chip; Described model selection control logic module is by mode select signal line options host interface.
Described CPU/DSP main frame is central processing unit/digital signal processing main frame.
The reception and the transmission of described subchannel processing module logical process data, comprise sending first-in first-out buffer FIFO, reception first-in first-out buffer FIFO, Baud rate generator, transmission shift register, reception shift register, flow control logic and substring mouth register, described word passage processing module also comprises IR scrambler and IR demoder.
Described subchannel processing module also comprises TX serial output signal line.
Described global register comprises RSV, overall control register GCR, overall main serial ports control register GMUCR, global interrupt register GIR, overall XOFF character register GXOFFH and overall XON character register GXON, and wherein RSV is for keeping register; Described global register is 6 bit address numberings by address number, and the address of global register is XX0000-XX0101, and wherein XX is any one value in 00,01,10,11, and wherein high 2 is channel number, and low 4 are the register address numbering.
Described subchannel processing module is provided with 10 substring mouth registers that each subchannel is provided with, and is respectively substring mouth control register SCTLR, substring mouth configuration register SCONR, substring mouth flow control register SFWCR, substring mouth FIFO control register SFOCR, the automatic identification address register of substring mouth SADR, substring mouth OIER SIER, substring mouth interrupt flag register SIFR, substring mouth status register SSR, substring mouth fifo status register SFSR and substring mouth fifo data register SFDR.
The status signal that the monitoring of described MODEM control logic module and control are connected with MODEM.MODEM refers to modulator-demodular unit.
Described interrupt control logic module produces and controls various internal interrupt, comprise that substring mouth and MODEM interrupt and global interrupt, the interrupt control logic module reads the type that global interrupt register GIR obtains to interrupt by the IRQ pin, read corresponding interrupt status register then, determine interrupt source at last.Described interrupt status register comprises the part that relates to interruption status in global register and the substring mouth register.
Wherein each substring mouth all has independently interrupt system simultaneously, comprising: the data fifo mistake is interrupted, and receiver address interrupts (RS485 pattern), and XOFF sends interruption, and RTS interrupts, and CTS interrupts, and sends the FIFO trigger point and interrupts, and receives the FIFO trigger point and interrupts.After any one interruption enables, satisfy interrupt condition and will produce corresponding interruption.
Described clock generator provides clock for chip, and this clock generator can be selected to obtain clock from crystal oscillator or external clock reference with clock selecting signal wire CLKSEL lead-in wire.
Groundwork flow process of the present invention is as follows:
The processing procedure that data send: host interface, i.e. 8 bit parallel bus interface, spi bus interface, UART bus interface, I
2The C bus interface is sent to corresponding subchannel FIFO after the data of sending are handled, data in the FIFO are through behind the flow control logic, under the effect of Baud rate generator, data are sent on the TX serial output signal line successively by sending shift register.
The Data Receiving processing procedure: after the substring mouth receives data, be stored in and receive among the FIFO, receive the host interface reading command after, protocol processor processes data into corresponding host bus data layout and is transferred to main frame.
In the subchannel processing module, substring mouth control register is used for each subchannel is provided with, and the IR codec is used for infrared signal is carried out encoding and decoding; The subchannel flow controller comprises the transmitted traffic controller and receives flow controller, the automatic flow control when being used for subchannel transmission data.
Advantage of the present invention is as follows:
One, supports 8 bit parallel buses, spi bus, I
2C, multiple host bus interface such as UART, built-in multiple bus protocol processor can be realized multiple bus expansion serial ports.
8 bit parallel bus interface products can be 8 by parallel bus, and 16,32 MCU carry out the UART serial ports expansion.8 bit parallel bus interface UART products have adopted simplifies the control register design, and has reduced chip pin by pin multiplexing, and the software design of simplification and PCB design all are more suitable for the embedded system demand.
SPI interface bus series of products are that the DSP, the MCU that have the SPI interface realize bridge joint and the expansion of synchronous SPI serial ports to asynchronous UART serial ports.The spi bus interface product can realize the asynchronous serial communication of DSP and peripheral hardware easily with a SPI synchronous serial interface bridge joint/be expanded into 1～4 universal asynchronous serial.
The realization of UART interface product innovation a standard 3 line asynchronous serial ports (UART) are expanded into 2～4 enhancement function serial ports (UART).The UART Extended Protocol processing logic of built-in chip type need not other address signal, the full duplex serial ports expansion that control signal wire just can be realized a plurality of separate configurations, and the embedded system of expanding serial ports for needs provides a solution the most succinct.
I
2The C bus interface is supported the quick I2C bus of 400Kbps, provide 2 can configuration address pin, can realize 4 similar devices on the same bus at most, for the field of a large amount of serial ports expansion of needs provides a feasible scheme.
Two, simplify perfect configuration register structure, the substring mouth can independently be provided with multiple mode of operation, supports high-speed communication.
Each substring mouth can independently be provided with baud rate and data layout by register, and substring mouth highest communication speed can reach 920K bps (5V operating voltage).The spi bus maximum transmission rate of host interface support is 4M bits/s, and the maximum transmission rate of main frame 8 bit parallel buses is 10M bit/s.
Perfect FIFO function, each passage independently 16 grades receive and send FIFO, each FIFO has 4 programmable trip point settings.The data buffering that perfect FIFO function can send/receive reduces the operation of DSP/CPU to data transmission, improves efficient and the reliability of data transmission of CPU/DSP.
Substring mouth passage can be configured to software or the control of hardware automatic flow, satisfies the needs of flow control in the high speed data transfer.
The substring mouth possesses the automatic control function of programmable hardware RS-485 and automatic 9 network address recognition functions, reduces the burden of processor greatly, is particularly useful for industrial RS-485 networking.
Three, each passage possesses independent controlled data broadcasting receiving function, can use and needs in the embedded system of datacast transmissions and control.
Four, all UART (comprising UART main interface and subchannel UART) support the IRDA infrared communication.
Description of drawings
Fig. 1 is a principle of work synoptic diagram of the present invention
Fig. 2 is an interrupt structure synoptic diagram of the present invention
Fig. 3 is the syndeton synoptic diagram of the present invention and RS485
Fig. 4 is SPI interface of the present invention and main frame syndeton synoptic diagram
Fig. 5 is a SPI time sequential routine synoptic diagram of the present invention
Fig. 6 is UART interface of the present invention and main frame syndeton synoptic diagram
Fig. 7 is a UART main interface write operation sequential synoptic diagram of the present invention
Fig. 8 is a UART main interface read operation sequential synoptic diagram of the present invention
Fig. 9 is parallel 8 the bus master interface connection diagrams of the present invention
Figure 10 is parallel 8 the total line write transactions sequential synoptic diagram of the present invention
Figure 11 is parallel 8 the bus read operation sequential synoptic diagram of the present invention
Embodiment
As shown in Figure 1, a kind of universal asynchronous serial extended chip of multi-bus interface, comprise host interface, subchannel processing module, MODEM control logic module, interrupt control logic module and clock generator, described host interface comprises 8 bit parallel bus interface, serial peripheral interface spi bus interface, UART bus interface, internal integrate circuit bus I
2C bus interface, protocol processor, global register and model selection control logic module; Described four kinds of bus interface all are connected with the CPU/DSP main frame, select the bus type of main frame correspondence by the bus processing logic, and pass through bus processing logic treatment S PI, UART, I
2The unified conversion of the data of C and 8 bit parallel buses and data layout; Described global register setting is provided with chip host interface duty; Described model selection control logic module is by mode select signal line options host interface, and M1 shown in Figure 1, M0 are for selecting signal wire.
Described CPU/DSP main frame is central processing unit/digital signal processing main frame.
The reception and the transmission of described subchannel processing module logical process data, comprise sending FIFO, reception FIFO, Baud rate generator, transmission shift register, reception shift register, flow control logic and substring mouth register, described word passage processing module also comprises IR scrambler and IR demoder.
The status signal that the monitoring of described MODEM control logic module and control are connected with MODEM.
Described interrupt control logic module produces and controls various internal interrupt, comprise that substring mouth and MODEM interrupt and global interrupt, the interrupt control logic module reads the type that global interrupt register GIR obtains to interrupt by the IRQ pin, read corresponding interrupt status register then, determine interrupt source at last, interrupt structure as shown in Figure 2.Described interrupt status register comprises the part that relates to interruption status in global register and the substring mouth register.
Simultaneously, wherein each substring mouth all has independently interrupt system, comprising: the data fifo mistake is interrupted, and receiver address interrupts (RS485 pattern), and XOFF sends interruption, and RTS interrupts, and CTS interrupts, and sends the FIFO trigger point and interrupts, and receives the FIFO trigger point and interrupts.After any one interruption enables, satisfy interrupt condition and will produce corresponding interruption.
Each substring mouth all has independently interrupt system, comprising: the data fifo mistake is interrupted, and receiver address interrupts (RS485 pattern), and XOFF sends interruption, and RTS interrupts, and CTS interrupts, and sends the FIFO trigger point and interrupts, and receives the FIFO trigger point and interrupts.After any one interruption enables, satisfy interrupt condition and will produce corresponding interruption.
Described clock generator provides clock for chip, obtains clock by selecting a kind of mode in external oscillator input and output XTAL1, XTAL2 and three kinds of modes of clock selection signal line CLKSEL.This clock generator can be selected to obtain clock from crystal oscillator or external clock reference with the CLKSEL lead-in wire.
Groundwork flow process of the present invention is as follows:
The processing procedure that data send: host interface, i.e. 8 bit parallel bus interface, spi bus interface, UART bus interface, I
2The C bus interface, be sent to corresponding subchannel FIFO after the data of sending are handled, data in the FIFO, send to data on the TX serial output signal line by sending shift register under the effect of Baud rate generator successively through behind the flow control logic.
The Data Receiving processing procedure: after the substring mouth receives data, be stored in and receive among the FIFO, receive the host interface reading command after, protocol processor processes data into corresponding host bus data layout and is transferred to main frame.
In the subchannel processing module, substring mouth control register is used for each subchannel is provided with, and the IR codec is used for infrared signal is carried out encoding and decoding; The subchannel flow controller comprises the transmitted traffic controller and receives flow controller, the automatic flow control when being used for subchannel transmission data.
A kind of universal asynchronous serial extended chip of multi-bus interface, this chip adopt simplifies register architecture, and register is 6 bit address numberings by address number, and the address is 000000～111111.
The host interface of this chip comprises RSV, overall control register GCR, overall main serial ports control register GMUCR, global interrupt register GIR, overall XOFF character register GXOFFH and overall XON character register GXON 6 global registers altogether.
The address of described global register is XX0000-XX0101, and wherein XX is any one value in 00,01,10,11, and wherein high 2 is channel number, and low 4 are the register address numbering, and concrete arrangement of its low 4 bit address seen the following form:
Global register is listed as follows:
| Register address [3:0] | The register title | Type | Register functions is described |
| (XX)0000 | RSV | Do not have | Keep |
| (XX)0001 | GCR | R/W | Overall situation control register |
| (XX)0010 | GMUCR | R/W | The main serial ports control register of the overall situation |
| (XX)0011 | GIR | R/W | The global interrupt register |
| (XX)0100 | GXOFF | R/W | Overall situation XOFF character register |
| (XX)0101 | GXON | R/W | Overall situation XON character register |
Be the specific descriptions of each global register below:
GCR overall situation control register: (0001)
| The position | Reset values | Functional | Type |
| Bit7 | |||
| 0 | GBDEN overall situation broadcasting enable bit | W/R |
| 0: forbidden data broadcasting 1: enable | |||
| Bit6 | |||
| 0 | IDEL software I DEL enable bit 0: wake operate as normal 1 up: enter the IDEL pattern | W/ | |
| Bit5 | |||
| 0 | DCDF carrier wave zone bit DCD pin | R | |
| Bit4 | |||
| 0 | DSRF data equipment ready flag position DSR pin | R | |
| Bit3 | |||
| 0 | DTRC data terminal ready control bit DTR pin control bit | W/ | |
| Bit2 | |||
| 0 | RIF ring indicating status position RI pin | R | |
| Bit1 | |||
| 0 | MINT MODEM interruption indication signal position 0: no MODEM interrupt identification 1:MODEM interrupt identification (under the situation that EMINT enables, DCD, DSR, the state of RI changes will produce this interruption) | | |
| Bit0 | |||
| 0 | ENMINT MINT interrupts enabling control bit 0: forbid that MINT interrupts 1: enable MINT and interrupt | W/R |
The main serial ports control register of the overall situation: (0010)
| The position | Reset values | Functional description | Type |
| Bit7---4 | 0011 | Main serial ports baud rate is provided with, and specifically the value of setting is referring to table 8.9.1 (the corresponding B3-B0 of Bit7-4) | W/R |
| Bit3 | 0 | (data length is provided with the position) 0:8 bit data (no tape verifying position) 1:9 bit data (being with the 9th bit check position) is set in PAEN master UART verification | W/ |
| Bit2 | |||
| 0 | STPL position of rest length is provided with position of rest 1:2 position, a 0:1 position position of rest | W/R | |
| Bit1--0 | 00 | PAM1-0 parity checking model selection 00: |
W/R |
GIR global interrupt register: (0011)
| The position | Reset values | Functional description | Class |
| | |||
| Bit7 | |||
| 0 | U4IEN substring mouth 4 interrupts enabling control bit 0: forbid that substring mouth 4 interrupts 1: enable substring mouth 4 and interrupt | W/ | |
| Bit6 | |||
| 0 | U3IEN substring mouth 3 interrupts enabling control bit 0: forbid that substring mouth 3 interrupts 1: enable substring mouth 3 and interrupt | W/ | |
| Bit5 | |||
| 0 | |
W/ | |
| Bit4 | |||
| 0 | |
W/ | |
| Bit3 | |||
| 0 | U4IF substring mouth 4 interrupt flag bits 0: substring mouth 4 does not have interruption 1: substring mouth 4 has | R | |
| Bit2 | |||
| 0 | U3IF substring mouth 3 interrupt flag bits 0: substring mouth 3 does not have interruption 1: substring mouth 3 has | R | |
| Bit1 | |||
| 0 | | R | |
| Bit0 | |||
| 0 | |
R |
GXOFF overall situation XOFF character register: (0100)
| The position | Reset values | Functional description | Type |
| Bit7---0 | 00000000 | XOFF special character register | W/R |
GXON overall situation XON character register:
| The position | Reset values | Functional description | Type |
| Bit7---0 | 00000000 | XON special character register | W/R |
Described subchannel processing module is provided with 10 substring mouth registers that each subchannel is provided with, and is respectively substring mouth control register SCTLR, substring mouth configuration register SCONR, substring mouth flow control register SFWCR, substring mouth FIFO control register SFOCR, the automatic identification address register of substring mouth SADR, substring mouth OIER SIER, substring mouth interrupt flag register SIFR, substring mouth status register SSR, substring mouth fifo status register SFSR and substring mouth fifo data register SFDR.
The tabulation of substring mouth register is as follows:
| Register address [3:0] | The register title | Type | Register functions is described |
| (C1，C0)0110 | SCTLR | R/W | Substring mouth control register |
| (C1，C0)0111 | SCONR | R/W | Substring mouth configuration register |
| (C1，C0)1000 | SFWCR | R/W | Substring mouth flow control register |
| (C1，C0)1001 | SFOCR | R/W | Substring mouth FIFO control register |
| (C1，C0)1010 | SADR | R/W | The automatic identification address register of substring mouth |
| (C1，C0)1011 | SIER | R/W | Substring mouth OIER |
| (C1，C0)1100 | SIFR | R | Substring mouth interrupt flag register |
| (C1，C0)1101 | SSR | R | Substring mouth status register |
| (C1，C0)1110 | SFSR | RW | Substring mouth fifo status register |
| (C1，C0)1111 | SFDR | RW | Substring mouth fifo data register |
Annotate: (00～11 respectively corresponding substring mouth 1 is to substring mouth 4 for C1, C0) expression subchannel number.SCTLR substring mouth control register: (0110)
It is arranged as C1C0REG[3:0 substring mouth register], high two is substring mouth channel number, low 4 is register address.
| The position | Reset values | Functional description | Type |
| Bit7---4 | 0011 | Substring mouth baud rate is provided with, and specifically the value of setting is referring to table 8.9.1 (the corresponding B3-B0 of Bit7-4) | W/ |
| Bit3 | |||
| 0 | UTEN substring mouth enables control bit 0: do not enable, this moment, this substring mouth passage can not carry out data transmit-receive | W/R |
| 1: enable, this substring mouth can carry out normal data transmit-receive after enabling | |||
| |
0 | MDSEL 485 and the automatic transceiver mode of 232 model selection control bit 0:RS232 transceiver mode 1:RS485, under this pattern, RTS is as receiving and dispatching control signal automatically | W/ |
| Bit1 | |||
| 0 | RBDEN allows to receive broadcast data control bit 1: allow the substring mouth to receive broadcast data 0: forbid that the substring mouth receives broadcast data | W/ | |
| Bit0 | |||
| 0 | The IREN infrared mode is selected position 0: standard serial port pattern 1: infrared data pattern | W/R |
SCONR substring mouth configuration register: (0111)
| The position | Reset values | Functional | Type |
| Bit7 | |||
| 0 | Position of rest 1:2 position, SSTPL substring mouth position of rest length control bit 0:1 position position of rest | W/ | |
| Bit6 | |||
| 0 | The verification of SPAEN substring mouth enables (data length control) position 0: no parity check position (8 bit data) 1: check bit (9 bit data) is arranged | W/ | |
| Bit5 | |||
| 0 | SFPAEN substring mouth forces verification to enable control bit 0: do not use the substring mouth to force verification 1: enable the substring mouth and force verification | W/R | |
| Bit4-3 | 00 | PAM1-0 parity checking model selection: when SFPAEN=1 substring mouth forces verification to enable: 00: |
W/ |
| Bit2 | |||
| 1 | AOD substring port address/data pattern is selected position (when being operated in the RS485 pattern) | W/R |
| 0: allow to receive all data bytes 1: only allow the receiver | |||
| Bit1 | |||
| 0 | Automatic identification control position, the AREN network address 0: forbid |
W/ | |
| Bit0 | |||
| 0 | The |
W/R |
SFWCR substring mouth flow control register: (1000)
| The position | Reset values | Functional description | Type |
| Bit7-6 | 00 | HRTL1-0 suspends transmission trigger point control (effective under the RS232 pattern): 00=3bytes 01=7bytes 10=11bytes 11=15bytes is under the condition that flow control enables, in receiving FIFO data be increased to this trigger point the time, start corresponding software/hardware flow control, the equipment that control channel is connected suspends data and sends. | W/R |
| Bit5-4 | 00 | PRTL1-0 continues to send trigger point control (effective under the RS23 pattern): 00=1bytes 01=4bytes 10=8bytes 11=12bytes is under the condition that flow control enables, when the data in receiving FIFO are reduced to this trigger point, by the software/hardware flow control mechanism, the equipment that control is connected with this passage continues to send data. | W/ |
| Bit3 | |||
| 0 | The FWCEN flow control enables control bit (effective under the RS232 pattern) 0: forbid substring mouth automatic flow control 1: allow the control of substring mouth automatic flow | W/ | |
| Bit2 | |||
| 0 | FWCM flow control mode (effective when flow control enables) 0: substring mouth automatic software flow control 1: the automatic hardware flow control of substring mouth | W/R | |
| Bit1 | 0 | (effective when the hardware flow control enables) selected in the flow control of AOMH hardware | W/R |
| 0: | |||
| Bit0 | |||
| 0 | As seen XVEN XON/XOFF is provided with the invisible 1:XON/XOFF character of 0:XON/XOFF character and writes FIFO, at the visible XOFF of host side | W/R |
SFOCR substring mouth FIFO control register: (1001)
| The position | Reset values | Functional description | Type |
| Bit7-6 | 00 | TFTL1-0 sends the control of FIFO contact: when 00=0bytes 01=4bytes 10=8bytes 11=12bytes reduced to this trigger point when the data that receive FIFO, the prompting main frame can continue to write data to sending FIFO. | W/R |
| Bit5---4 | 00 | RFTL1-0 receives the control of FIFO contact: 00=1bytes 01=4bytes 10=8bytes 11=14bytes when the data that receive FIFO are increased to this trigger point is prompting host interface reading of data from receive FIFO. | W/ |
| Bit3 | |||
| 0 | TFEN sends FIFO and enables control bit 0: forbid sending FIFO, data to be sent do not write and send FIFO, directly enter and send shift register 1: enable to send FIFO, data to be sent write and send FIFO, send by FIFO | W/ | |
| Bit2 | |||
| 0 | RFEN receives FIFO and enables 0: forbid receiving FIFO, the data that receive do not write and receive FIFO 1: enable to receive FIFO, the data that receive write and receive FIFO | W/ | |
| Bit1 | |||
| 0 | TFCL clear to send FIFO 0: do not remove TX FIFO 1: all data among the clear to send TX FIFO | W/ | |
| Bit0 | |||
| 0 | RFCL removes and receives FIFO 0: do not remove and receive |
W/R |
The automatic identification address register of SADR substring mouth: (1010)
| The position | Reset values | Functional description | Type |
| Bit7---0 | 00000000 | The automatic recognition network address register of substring mouth.(effective under the RS485 pattern) | W/R |
SIER substring mouth OIER: (1011)
| The position | Reset values | Functional | Type |
| Bit7 | |||
| 0 | RXBY RX_BUSY mode bit 0: this passage RX free time 1: this passage RX is receiving | R | |
| Bit6 | |||
| 0 | FOEIEN data fifo mistake interrupt enable bit: 0: forbid that the data fifo mistake produces interruption 1: enable the data fifo mistake and produce interruption | W/ | |
| Bit5 | |||
| 0 | RAIEN receiver address interrupt enable bit: 0: forbid that substring mouth receiver address produces interruption 1: enable substring mouth receiver address and produce interruption | W/ | |
| Bit4 | |||
| 0 | XFIEN XOFF interrupt enable bit: 0: forbid that XOFF interrupts 1: enable XOFF and interrupt, produce when the group serial ports receives the XOFF special character and interrupt | W/ | |
| Bit3 | |||
| 0 | RSTIEN RTS interrupt enable bit 0: forbid that RTS interrupts 1: enable RTS and interrupt | W/ | |
| Bit2 | |||
| 0 | CTSIEN CTS interrupt enable bit 0: forbid that CTS interrupts 1: enable CTS and interrupt | W/ | |
| Bit1 | |||
| 0 | TRIEN sends FIFO contact interrupt enable bit 0: forbid sending the FIFO contact and interrupt 1: enable to send the FIFO contact and interrupt | W/ | |
| Bit0 | |||
| 0 | RFIEN enables to receive the FIFO contact and interrupts | W/R |
| 0: forbid receiving the FIFO contact and interrupt 1: enable to receive the FIFO contact and interrupt |
SIFR substring mouth interrupt flag register: (1100)
| The position | Reset values | Functional | Type |
| Bit7 | |||
| 0 | The value of the mode bit current C TS pin of CTSR indication | R | |
| Bit6 | |||
| 0 | FOEINT substring mouth data fifo mistake interrupt flag bit 0: no data fifo mistake is interrupted 1:FIFO error in data (producing this interruption when data are made mistakes among the FIFO) | R/ | |
| Bit5 | |||
| 0 | RAINT substring mouth automatic address identification interrupt bit 0: zero-address is discerned automatically and interrupted 1: (when the data that receive are address byte and produce interruption when mate with SDAR) interrupted in automatic address identification | R/ | |
| Bit4 | |||
| 0 | XFINT XOFF interrupt flag bit 0: no XOFF interrupts 1: have XOFF to interrupt | R/ | |
| Bit3 | |||
| 0 | RSTINT RTS interrupt flag bit 0: no RTS interrupts 1: have RTS to interrupt | R/ | |
| Bit2 | |||
| 0 | CTSINT CTS interrupt flag bit 0: read automatic clear 1 behind this register: have CTS to interrupt | R/ | |
| Bit1 | |||
| 0 | TFINT substring mouth sends FIFO contact interrupt flag bit 0: no TFINT interrupts 1: have TFINT to interrupt | R/ | |
| Bit0 | |||
| 0 | RFINT substring mouth receives FIFO contact interrupt flag bit 0: no RFINT interrupts 1: have RFINT to interrupt | R/ W |
SSR substring mouth status register: (1101)
| The position | Reset values | Functional description | Type |
| Bit7 | X | OE substring mouth receives the overflow error zone bit of current data (writing the earliest) among the FIFO: 0: no OE mistake 1: the OE mistake is arranged | R |
| Bit6 | X | FE substring mouth receives the frame error flag position of current data (writing the earliest) among the FIFO: 0: no FE mistake 1: the FE mistake is arranged | R |
| Bit5 | X | PE substring mouth receives the check errors zone bit 0 of current data (writing the earliest) among the FIFO: no PE mistake 1: the PE mistake is arranged | R |
| Bit4 | X | RX8 substring mouth receives the 9th (Bit8) data value of current data (writing the earliest) among the FIFO | R |
| Bit3 | 0 | TFFL substring mouth sends FIFO full scale will 0: the substring mouth sends FIFO less than 1: it is full that the substring mouth sends FIFO | R |
| Bit2 | 1 | TFEM substring mouth sends the empty sign 0 of FIFO: the substring mouth sends FIFO position sky 1: the substring mouth sends the FIFO sky | R |
| Bit1 | 0 | TXBY substring mouth sends the busy sign 0 of TX: the substring mouth sends TX sky 1: it is busy that the substring mouth sends TX | R |
| Bit0 | 1 | RFEM substring mouth receives the empty sign 0 of FIFO: the substring mouth receives not sky 1 of FIFO: the substring mouth receives the FIFO sky | R |
SFSR substring mouth fifo status register: (1110)
| The position | Reset values | Functional description | Type |
| Bit7-4 | 0000 | TCNT3-0 substring mouth sends the data number among the FIFO | R |
| Bit3--0 | 0000 | RCNT3-0 substring mouth receives the data number among the FIFO | R |
SFDR substring mouth fifo data register: (1111)
| The position | Reset values | Functional description | Type |
| Bit7--0 | xxxxxxxx | During write operation: the substring mouth that writes sends the data reading operation ten of FIFO: the substring mouth of reading receives the data of FIFO | W/R |
Embodiment 3
But the chip among the present invention is supported the data broadcast mode of substring mouth passage separate configurations.By the GBDEN position among the global register GCR is set, main mouthful overall situation broadcasting is set to enable, and the RDBEN position of the SCTLR of the corresponding substring mouth passage that needs the reception broadcast data is set then, makes this passage can receive data broadcasting.After the main interface steering logic detects broadcasting and is provided with, main mouthful data are sent to all substring mouths, broadcast data can be set to receive the substring mouth that broadcasting enables and receive, and will not ignore these data and the substring mouth that receives data broadcasting is set.Thereby realized can separate configurations the data broadcasting function.
Embodiment 4
This chip is also supported dormancy and automatic awakening mode, writes 1 to the IDLE position of GCR, after steering logic detects this value, after finishing existing operation, will cut off all internal clockings, and chip enters park mode to reduce power consumption.
Under park mode, can be waken up automatically by main mouthful and substring mouth: in case SCS, CS, main mouthful MRX, substring mouth RX have the data change, after the steering logic of chip detects variation, will be in several clock period the automatic start up system clock, enter normal transmitting-receiving.
The operating voltage of considering DSP/FPGA novel in the present built-in field mostly is 2.5V greatly, and the MCU of a large amount of industrial control fields still need work under 5V voltage, and the operating voltage range of the UART design that this chip relates to is 2.5V～5.5V.Simultaneously, this family chip can be in dormancy and is worked under the awakening mode automatically, effectively reduces power consumption.
Embodiment 5
The design allows independent enable or forbids each substring mouth passage.Have one to enable control bit in substring mouth control register, have only when it is set to enable, substring mouth steering logic is just opened the transmission-receiving function of substring mouth.Can forbid that obsolete substring mouth passage is to reduce power consumption.Substring mouth passage only is in enabled state could receive and send data.
Embodiment 6
The design possesses the automatic recognition function of the automatic transmitting-receiving control and the network address under the RS-485 pattern.
By substring mouth register is set is the RS-485 pattern, and substring mouth steering logic will make this serial ports be operated under the RS-485 pattern.At this moment, flow control will be under an embargo.The RTS signal is used to control the automatic transmitting-receiving control of RS485 transceiver.
Only when sending data, RTS just is high, and under other situation, it is low that RTS keeps.
Being connected of chip and 485 transceiver as Fig. 3.
The network address and automatic address identification principle of work:
Under the RS485 pattern, each UART has a unique network address, and this chip provides an eight bit register to carry out the RS485 network settings.When automatic network Address Recognition function enabled, chip was discerned automatically to the data that receive.
If the data that receive be data byte or with SADR in during the unmatched address byte of address byte, ignore these data.If the data that this substring mouth receives are address byte, and with SADR in Data Matching, then this chip enters accepting state, the data byte behind this address byte is write receive among the FIFO.When this substring mouth under data receiving state, receive an address byte, and this byte and SADR be not when matching, reception will be by automatic forbidden energy.
Automatic and manual Address Recognition principle of work:
Under the RS485 pattern, the AOD position in the SCONR substring mouth configuration register is that data address is selected the position.Its default value is 1, shows that this substring mouth receives only address byte and ignores data byte.
Under RS485 automatic address pattern, when the address that receives is consistent with the address of SADR, AOD will become 0 automatically, and this moment, this substring mouth can continue to receive data.When next address byte that the group serial ports receives and the address of SARD are inconsistent, the AOD position will put 1 automatically, no longer receive data byte thereafter.
Under the recognition mode of the manual address of RS485, RS485 is judged by upper layer software (applications) the address that the AOD position needs manually to be provided with.AOD is set to show all data that can receive thereafter at 0 o'clock, when AOD is set to 1, shows all data that will ignore except the address.When receiving address byte, chip will produce interruption, and notice MCU judges the address byte of receiving whether AOD is set to receive data thereafter with decision.
As seen the network address is provided with workflow:
When the group serial port setting was manual address recognition mode, the RS485 network address always as seen.
When substring mouth society is set to the automatic address recognition mode, the AVEN position in the SCONR substring mouth configuration register can be set, change network address visual attribute.When being made as the address when visible, the network address that receives enters and receives FIFO, otherwise will be left in the basket.
A kind of universal asynchronous serial extended chip of multi-bus interface, described host interface comprise 8 bit parallel bus interface, serial peripheral interface spi bus interface, UART bus interface, I
2C bus interface, global register and model selection control logic module; The principle of work and the flow process of described four kinds of bus interface are as described below.
1, SPI interface modes operation
SPI is connected with main frame, as shown in Figure 4.
Shown in the SPI interface comprise following four signals:
The input of SDIN:SPI data.
The output of SDOUT:SPI data.
The SCLK:SPI serial clock.
SCS:SPI sheet choosing (subordinate selection).
The time sequential routine of SPI interface is:
This chip operation is supported SPI pattern 0 standard under the slave mode of SPI synchronous serial communication.For realizing communicating by letter of main frame and this chip, in host side CPOL=0 (the SPI clock polarity is selected the position) need be set, CPHA=0 (the SPI clock phase is selected the position).
The time sequential routine of SPI interface as shown in Figure 5.
For realizing spi bus expansion operation of serial-port, following agreement is adopted in the spi bus communication of this chip:
SPI writes register
| SPI | Control byte GMD | Data | ||||||||||||||
| BIT | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| |
1 | C1 | C0 | A3 | A2 | A1 | A0 | D8t | D7t | D6t | D5t | D4t | D3t | D2t | D1t | D0t |
| DOUT | INT1 | INT2 | INT3 | INT4 | OE | FE | PE | RX8 | TC3 | TC2 | TC1 | TC0 | RC3 | RC2 | RC1 | RC0 |
The SPI read register
| Classification | Control byte CMD | Data | |||||||||||||||
| BIT | |||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| |
0 | C1 | C0 | A3 | | A1 | A0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| DOUT | INT1 | INT2 | INT3 | INT4 | TXF | TXE | TXB | RXB | D7r | D6r | D5r | D4r | D3r | D2r | D1r | D0r | |
Illustrate:
C1C0: substring mouth channel number 00～11 respectively corresponding substring mouth 1 is to substring mouth 4
A3-A0: substring mouth register address
The 9th data when D8t:9 bit data length sends
INT1-INT4: the interrupt identification of passage 1 to 4
Overflow error sign during OE:=1
FE:=1 time frame error flag
Check errors sign during PE:=1
RX8: the 9th bit data of reception
TC3-TC0: the number that sends data fifo
RC3-RC0: the number that receives data fifo
It is full to send FIFO during TXF:=1
Send the FIFO sky during TXE:=1
Send FIFO Busy during TXB:=1
Receive the FIFO sky during RXE:=1
2, being connected of UART interface and main frame, as shown in Figure 6.
When the main interface of this chip is UART, only need RX, TX connects main frame.The UART agreement of employing standard communicates.After powering on, main frame with determined baud rate of reset values and data layout can realize the serial ports expansion function easily after this chip is carried out initialization and is provided with.
During write operation, write a command byte (Command Byte) to the RX of this chip earlier, write corresponding data byte subsequently, its time sequential routine (no parity check is forbidden escape and infrared mode) as shown in Figure 7.
During read operation, earlier to the RX of this chip write command byte, corresponding data byte reads from TX, and its time sequential routine (no parity check is forbidden escape and infrared mode) as shown in Figure 8.
Main UART communication transport protocols is described below shown in the table:
Write register:
| Classification | |
1 data byte DB (descending) | ||||||||||||||
| |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| |
1 | 0 | C1 | C0 | A3 | A2 | A1 | A0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| RX | ||||||||||||||||
Writing the FIFO:(multibyte writes)
| Classification | Control byte CMD | [N3 N2 N1 N0] individual data byte DB (descending) | ||||||||||||||
| |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| |
1 | 1 | C1 | C0 | N3 | N2 | N1 | N0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| RX | ||||||||||||||||
Read register:
| Classification | |
1 data byte DB (up) | ||||||||||||||
| |
7 | 6 | D | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| |
0 | 0 | C1 | C0 | N3 | N2 | N1 | N0 | ||||||||
| RX | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | ||||||||
Reading the FIFO:(multibyte reads)
| Classification | Control byte CMD | [N3 N2 N1 N0] individual data byte DB (up) | ||||||||||||||
| |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| |
0 | 1 | C1 | C0 | N3 | N2 | N1 | N0 | ||||||||
| RX | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | ||||||||
Illustrate:
C1, C0: substring mouth channel number, 00～11 respectively corresponding substring mouth 1 is to substring mouth 4.
A3, A2, A1, A0: substring mouth register address;
N3, N2, N1, N0: the data byte number that writes/read FIFO; When it is 0000, connect 1 data byte after showing; When it is 1111, connect 16 data bytes after showing.
To substring mouth read/write data two kinds of methods are arranged:
A. read/write register mode, antithetical phrase serial ports fifo register SFDR (1111) carries out read/write operation, once can only byte of read/write;
B. read/write FIFO mode is directly carried out read/write operation to reception/transmission FIFO, once can read and write 16 continuous datas at most.
The infrared operator scheme of main UART interface:
When main serial ports IR pin connect high level, chip master UART was operated under the infrared mode, and main UART defers to infrared communication protocol with communicating by letter of main frame, and its time sequential routine is the infrared mode operation.
When main serial ports IR pin connect low level, chip operation was under general mode.
3, being connected of parallel 8 buses and main frame:
Chip of the present invention supports 8 bit parallel buses to be connected with main frame, and under 8 mode bus, chip only needs to take two address spaces, and one is used for operation-address register, and one is used for the service data register.When adopting inquiry mode work, IRQ can not connect, and it connects as shown in Figure 9.
The time sequential routine of parallel 8 bus interface:
The time sequential routine of 8 MCU (as 8051) of the complete compatible main flow of 8 bit parallel bus interface of this chip, the write operation sequential as shown in figure 10, the read operation sequential is as shown in figure 11.
Parallel 8 bus transfer protocol descriptions:
Write register:
| Classification | Control byte CMD (A0=0) | 1 data byte DB (descending) (A0=1) | ||||||||||||||
| |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | C1 | C0 | A3 | A2 | A1 | A0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
Read data:
| Classification | Control byte CMD (A0=0) | 1 data byte DB (up) (A0=1) | ||||||||||||||
| |
7 0 | 6 0 | 5 C1 | 4 C0 | 3 |
2 |
1 |
0 |
7 D7 | 6 D6 | 5 D5 | 4 D4 | 3 |
2 |
1 |
0 D0 |
Illustrate:
C1, C0: substring mouth channel number, 00～11 respectively corresponding substring mouth 1 is to substring mouth 4.
A3, A2, A1, A0: substring mouth register address
This chip characteristics compared with similar products:
1. multi-bus interface: main interface has SPI, serial ports, and 8 bit parallels, the I2C bus can be selected, and each substring mouth data layout and baud rate independently are provided with.
2. simplify register architecture, built-in structure is simplified, the overall situation of perfect in shape and function and substring mouth register project organization.
3. built-in serial ports expansion agreement, under the serial ports expansion serial ports pattern, main serial ports only needs the three-way serial ports of a standard, RXD, TXD, GND need not the outer address signal line of occupying volume.
4. adopt dormancy and wake design automatically up, waking up automatically of US level do not influence the reception and the transmission of start byte.
5. wide operating voltage: 2.5V--5.5V.
6. substring mouth and main serial ports are all supported infrared mode.
7. perfect FIFO function: each passage is 16 grades of RX and TX FIFO independently.
8. perfect flow control: the hardware and software flow control, automatic and manual flow control can be selected.
9.RS485 transmitting-receiving and automatic network Address Recognition are particularly suitable for industrial networking automatically
10. Du Chuan separate configurations data broadcasting merit.
4, I
2The protocol operation of C bus is consistent with the protocol operation of UART bus.
Claims (9)
1. the universal asynchronous serial extended chip of a multi-bus interface, comprise host interface, subchannel processing module, MODEM control logic module, interrupt control logic module and clock generator, it is characterized in that: described host interface comprises 8 bit parallel bus interface, serial peripheral interface spi bus interface, UART bus interface, internal integrate circuit bus I
2C bus interface, protocol processor, global register and model selection control logic module; Described four kinds of bus interface all are connected with the CPU/DSP main frame, select the bus type of main frame correspondence by the bus processing logic, and pass through bus processing logic treatment S PI, UART, I
2The unified conversion of the data of C and 8 bit parallel buses and data layout; Described global register is provided with the host interface duty of chip; Described model selection control logic module is by mode select signal line options host interface.
2. the universal asynchronous serial extended chip of a kind of multi-bus interface according to claim 1, it is characterized in that: described CPU/DSP main frame is central processing unit/digital signal processing main frame.
3. the universal asynchronous serial extended chip of a kind of multi-bus interface according to claim 1 and 2, it is characterized in that: the reception and the transmission of described subchannel processing module logical process data, comprise sending first-in first-out buffer FIFO, reception first-in first-out buffer FIFO, Baud rate generator, transmission shift register, reception shift register, flow control logic and substring mouth register, described word passage processing module also comprises IR scrambler and IR demoder.
4. according to the universal asynchronous serial extended chip of claim 1 or 3 described a kind of multi-bus interfaces, it is characterized in that: described subchannel processing module also comprises TX serial output signal line.
5. the universal asynchronous serial extended chip of a kind of multi-bus interface according to claim 1, it is characterized in that: described global register comprises RSV, overall control register GCR, overall main serial ports control register GMUCR, global interrupt register GIR, overall XOFF character register GXOFFH and overall XON character register GXON, and wherein RSV is for keeping register; Described global register is 6 bit address numberings by address number, and the address of global register is XX0000-XX0101, and wherein high 2 is channel number, and low 4 are the register address numbering, and XX is any one value in 00,01,10,11.
6. the universal asynchronous serial extended chip of a kind of multi-bus interface according to claim 1, it is characterized in that: described subchannel processing module is provided with 10 substring mouth registers that each subchannel is provided with, and is respectively substring mouth control register SCTLR, substring mouth configuration register SCONR, substring mouth flow control register SFWCR, substring mouth FIFO control register SFOCR, the automatic identification address register of substring mouth SADR, substring mouth OIER SIER, substring mouth interrupt flag register SIFR, substring mouth status register SSR, substring mouth fifo status register SFSR and substring mouth fifo data register SFDR.
7.。The universal asynchronous serial extended chip of a kind of multi-bus interface according to claim 1 is characterized in that: the status signal that the monitoring of described MODEM control logic module and control are connected with MODEM.
8. the universal asynchronous serial extended chip of a kind of multi-bus interface according to claim 1, it is characterized in that: described interrupt control logic module produces and controls various internal interrupt, comprise that substring mouth and MODEM interrupt and global interrupt, the interrupt control logic module reads the type that global interrupt register GIR obtains to interrupt by the IRQ pin, read corresponding interrupt status register then, determine interrupt source at last.
9. the universal asynchronous serial extended chip of a kind of multi-bus interface according to claim 1, it is characterized in that: described clock generator provides clock for chip.
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| CN116028403A (en) * | 2023-03-27 | 2023-04-28 | 江苏润石科技有限公司 | I2C bus circuit based on asynchronous circuit |
| CN116627885A (en) * | 2023-07-26 | 2023-08-22 | 苏州萨沙迈半导体有限公司 | Flexible application serial peripheral interface host circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2671026Y (en) * | 2003-09-23 | 2005-01-12 | 南京师范大学 | Embedded observer and control system developing platform |
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