CN101136754A - Data transmission control system of ethernet chip - Google Patents
Data transmission control system of ethernet chip Download PDFInfo
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- CN101136754A CN101136754A CNA2006101522767A CN200610152276A CN101136754A CN 101136754 A CN101136754 A CN 101136754A CN A2006101522767 A CNA2006101522767 A CN A2006101522767A CN 200610152276 A CN200610152276 A CN 200610152276A CN 101136754 A CN101136754 A CN 101136754A
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Abstract
The data transmission control system includes CPU, memory module, piece of PCI bridge, hardware logic unit (HLU), multiple Ethernet chip, and E1/T1 chip. The system also includes direct accessible common storage area (CSA) by HLU. CSA is in use for saving data received from and transmitted to by Ethernet chip and E1/T1 chip. HLU includes following parts: Ethernet control module in use for controlling data transmission of Ethernet chip; E1/T1 control module in use for configuring address of data received from and transmitted to by E1/T1, and in use for staring data interchange between Ethernet chip and E1/T1 chip; CPU in use for mapping address of CSA to space of system address as well as setting up address for Ethernet chip to receive and transmit data and data descriptor to the mapped address.
Description
Technical field
The present invention relates to a kind of data transfer control system of Ethernet chip, relate in particular to the data transfer control system of the Ethernet chip under a kind of many Ethernet chip environment.
Background technology
At present, embedded communication equipment generally all has multichannel communication, multi-protocols exchange disposal ability, for the real-time that guarantees to communicate by letter and can handle huge data traffic, need the CPU (Central Processing Unit, CPU) in the equipment to have the high processing ability.How utilizing the existing lower CPU of performance, reducing equipment cost as far as possible, reducing under the prerequisite of power consumption, realize the above-mentioned disposal ability of communication equipment, is one of emphasis of communications equipment manufacturer research.
At present, Chang Yong embedded many ethernet communications equipment generally is made of equipment such as CPU element, internal storage location, Ethernet chip and hardware logic unit.Except internal storage location, communication is realized by PCI (Perpheral Component Interconnect, peripheral devices is interconnected) bus in other unit, as shown in Figure 1.The hardware logic that generally adopts is FPGA (Field Programmable Gate Army now, field programmable gate array), EPLD (Erasable Programmable Logic Device, Erasable Programmable Logic Device) etc., hardware logic cooperates can finish physical signalling and data-handling capacity, in some application scenarios, can finish data processing work by replaced C PU.
In many ethernet communications equipment, we are divided into two classes to Ethernet chip from application point of view: a class Ethernet chip is used for debugging control and signaling transmission, and another kind of Ethernet chip is used for the transmission of business datum.For first kind Ethernet chip, CPU need participate in the control of transfer of data, so that CPU can resolve the go forward side by side processing of line correlation agreement of signaling; For the second class Ethernet chip, CPU can carry out the control of transfer of data to it, but CPU can not do the signaling extraction, only do data-moving and transparent transmission, but consume a part of CPU disposal ability like this, for the lower CPU of performance, can't finish the concurrent processing of a plurality of Ethernet datas sometimes, thereby can't satisfy system requirements.
Summary of the invention
The technical problem to be solved in the present invention is, overcome the deficiency of Ethernet chip data transmission control technology in the prior art, propose a kind of data transfer control system of the Ethernet chip under many Ethernet chip environment, make the communication apparatus of the CPU with lower-performance can finish many Ethernet chip transfer of data.
In order to address the above problem, the invention provides a kind of data transfer control system of Ethernet chip, comprise CPU, memory modules, PCI bridge sheet, hardware logic unit, a plurality of Ethernet chip and E1/T1 chip; Wherein Ethernet chip 3 is used for the transmission of business datum, and this system also comprises and can be used to preserve the reception of Ethernet chip 3 and E1/T1 chip and be sent data by the shared memory of the direct visit in hardware logic unit; Wherein,
The hardware logic unit and is connected with pci bus, is connected with the E1/T1 chip with control interface by data by local bus between the Ethernet chip 3; Hardware logic comprises in the unit: ethernet control module is used for Ethernet chip 3 is carried out Data Transmission Controlling; The E1/T1 control module is used to dispose the address of the transceive data of E1/T1 chip, and starts the exchanges data between Ethernet chip 3 and the E1/T1 chip;
CPU is connected with Ethernet chip 3 and hardware logic unit by pci bus, is used for the shared memory map addresses to system address space, and be address after the above-mentioned mapping with the address setting of the transceive data of Ethernet chip 3 and transceive data descriptor.
In addition, described shared memory can be positioned at inside, hardware logic unit, can directly be visited by ethernet control module and E1/T1 control module.
In addition, described shared memory also can be positioned at outside, hardware logic unit, and hardware logic comprises memory interface in the unit, and ethernet control module and E1/T1 control module conduct interviews to shared memory by this memory interface.
In addition, described hardware logic unit can be the FPGA device.
In addition, when described shared memory was positioned at outside, hardware logic unit, described hardware logic unit can be the CPLD/EPLD device.
The present invention finishes the work of part Ethernet chip Data Transmission Controlling by using hardware logic unit replaced C PU, reduced the processing load of CPU, under the situation of the lower CPU of system's serviceability, make communication equipment have the transmission control ability of many Ethernet chip, thereby reached the effect that reduces equipment cost and energy consumption.
Description of drawings
Fig. 1 is the system construction drawing of the data transfer control system of Ethernet chip of the present invention;
Fig. 2 is the system construction drawing of another embodiment of the data transfer control system of Ethernet chip of the present invention.
Embodiment
Basic ideas of the present invention are, in many ethernet communications environment, according to function Ethernet chip is classified,, use the hardware logic unit to come replaced C PU to carry out the transmission control of this Ethernet chip business datum for the Ethernet chip that is mainly used in business data transmission.
To be example with the many ethernet communications equipment that comprises 3 Ethernet chip below, the invention will be further described in conjunction with the accompanying drawings.
Fig. 1 is the system construction drawing of the data transfer control system of Ethernet chip of the present invention.
As shown in Figure 1, this communication apparatus comprises CPU, memory modules, PCI bridge sheet, FPGA, 3 Ethernet chip and 1 E1/T1 chip.Wherein:
Ethernet chip 1 is used for the transmission of signaling;
Ethernet chip 2 is used for the transmission of signaling between the main and standby boards;
Ethernet chip 3 is used for the transmission of business datum;
FPGA and is connected with pci bus, is connected with the E1/T1 chip with control interface by data by local bus between each Ethernet chip: comprise among the FPGA: ethernet control module is used for Ethernet chip 3 is carried out Data Transmission Controlling; The E1/T1 control module is used to dispose the address of the transceive data of E1/T1 chip, and starts the exchanges data between Ethernet chip 3 and the E1/T1 chip; Shared memory is used to preserve the reception of Ethernet chip 3 and E1/T1 chip and sends data;
CPU is connected with memory modules by rambus, and is connected with equipment such as Ethernet chip 1, Ethernet chip 2, Ethernet chip 3 and FPGA by pci bus; Be used for Ethernet chip 3 being carried out basic initialization operation such as chip reset, port speed setting, dual-mode setting, physical address configuration in power up; And with the shared memory map addresses of FPGA inside to system address space, use after this mapping address configuration FPGA and with the address setting of the transceive data of Ethernet chip 3 and the transceive data descriptor address after for this mapping, CPU transmits control to Ethernet chip 1, Ethernet chip 2 simultaneously.
Fig. 2 is the system construction drawing of another embodiment of the data transfer control system of Ethernet chip of the present invention.
As shown in Figure 2, also can use the FPGA outside but can realize the present invention by the memory of FPGA direct access, but use the implementation complexity of this mode hardware logic can be high, real-time is understood weaker.
The memory that uses the FPGA outside is provided with memory interface module during as shared memory in FPGA, be used for carrying out read and write access with shared memory.In addition, CPU needs map addresses with this memory to system address space, and uses address configuration Ethernet chip and FPGA after shining upon, makes Ethernet chip and FPGA can use this memory to carry out data manipulation.
Though adopt the data transfer control system of Ethernet chip of the present invention, CPU has given the hardware logic unit Ethernet chip transmission control, but CPU still can inquire about the operating state and the information of Ethernet chip by pci bus interface, and is used for system's detection and diagnostic process.
Through actual test proof, all adopt Intel ER82551 in above-mentioned Ethernet chip, when the E1/T1 process chip adopts Dallas DS21455, adopt the data transfer control system of Ethernet chip of the present invention, by FPGA an Ethernet chip is transmitted control, the utilance that can reduce CPU reaches more than 30%.
Ethernet chip data transfer control system of the present invention is simple, practical, is accompanied by the extensive use of various real-time ethernet communication equipments in different field, and this system also will have abundant and huge application potential.
Claims (5)
1. the data transfer control system of an Ethernet chip comprises CPU, memory modules, PCI bridge sheet, hardware logic unit, a plurality of Ethernet chip and E1/T1 chip; Wherein Ethernet chip (3) is used for the transmission of business datum, it is characterized in that,
This system also comprises and can be used to preserve the reception of Ethernet chip (3) and E1/T1 chip and be sent data by the shared memory of the direct visit in hardware logic unit; Wherein,
The hardware logic unit and is connected with pci bus, is connected with the E1/T1 chip with control interface by data by local bus between the Ethernet chip (3); Hardware logic comprises in the unit: ethernet control module is used for Ethernet chip (3) is carried out Data Transmission Controlling; The E1/T1 control module is used to dispose the address of the transceive data of E1/T1 chip, and starts the exchanges data between Ethernet chip (3) and the E1/T1 chip;
CPU is connected with Ethernet chip (3) and hardware logic unit by pci bus, is used for the shared memory map addresses to system address space, and uses address configuration FPGA and Ethernet chip (3) after this mapping.
2. the data transfer control system of Ethernet chip as claimed in claim 1 is characterized in that, described shared memory is positioned at inside, hardware logic unit, is directly visited by ethernet control module and E1/T1 control module.
3. the data transfer control system of Ethernet chip as claimed in claim 1, it is characterized in that, described shared memory is positioned at outside, hardware logic unit, hardware logic comprises memory interface in the unit, and ethernet control module and E1/T1 control module conduct interviews to shared memory by this memory interface.
4. as the data transfer control system of claim 1 or 2 or 3 described Ethernet chip, it is characterized in that described hardware logic unit is the FPGA device.
5. the data transfer control system of Ethernet chip as claimed in claim 3 is characterized in that, described hardware logic unit is the CPLD/EPLD device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101522767A CN101136754A (en) | 2006-09-27 | 2006-09-27 | Data transmission control system of ethernet chip |
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| CNA2006101522767A CN101136754A (en) | 2006-09-27 | 2006-09-27 | Data transmission control system of ethernet chip |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101963948A (en) * | 2010-08-26 | 2011-02-02 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN102480426A (en) * | 2010-11-25 | 2012-05-30 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN102495820A (en) * | 2011-11-24 | 2012-06-13 | 中国航空工业集团公司第六三一研究所 | Special aviation multi-interface maintenance method and special aviation multi-interface maintenance system |
| CN102647321A (en) * | 2012-05-16 | 2012-08-22 | 浙江中控研究院有限公司 | Data transmission device between Ethernet for plant automation (EPA) bus and controller area network (CAN) bus |
| CN102754397A (en) * | 2010-02-12 | 2012-10-24 | 株式会社日立制作所 | Information processing device, and method of processing information upon information processing device |
| CN101668233B (en) * | 2008-09-01 | 2013-01-16 | 中兴通讯股份有限公司 | Hardware device and method for assisting in processing dynamic bandwidth allocation algorithm |
| CN105743668A (en) * | 2014-12-09 | 2016-07-06 | 中兴通讯股份有限公司 | Method and device for achieving function of package transmitting and receiving |
| WO2019136983A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Low-delay instruction scheduler |
| CN111752895A (en) * | 2020-06-28 | 2020-10-09 | 北京经纬恒润科技有限公司 | Log storage method and device among multi-system-level chips |
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2006
- 2006-09-27 CN CNA2006101522767A patent/CN101136754A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101668233B (en) * | 2008-09-01 | 2013-01-16 | 中兴通讯股份有限公司 | Hardware device and method for assisting in processing dynamic bandwidth allocation algorithm |
| CN102754397A (en) * | 2010-02-12 | 2012-10-24 | 株式会社日立制作所 | Information processing device, and method of processing information upon information processing device |
| CN101963948A (en) * | 2010-08-26 | 2011-02-02 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN101963948B (en) * | 2010-08-26 | 2012-10-24 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN102480426A (en) * | 2010-11-25 | 2012-05-30 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN102480426B (en) * | 2010-11-25 | 2014-07-09 | 迈普通信技术股份有限公司 | Communication method based on peripheral component interconnect-express (PCIE) switching bus and PCIE switching system |
| CN102495820A (en) * | 2011-11-24 | 2012-06-13 | 中国航空工业集团公司第六三一研究所 | Special aviation multi-interface maintenance method and special aviation multi-interface maintenance system |
| CN102647321A (en) * | 2012-05-16 | 2012-08-22 | 浙江中控研究院有限公司 | Data transmission device between Ethernet for plant automation (EPA) bus and controller area network (CAN) bus |
| CN102647321B (en) * | 2012-05-16 | 2014-10-29 | 浙江中控研究院有限公司 | Data transmission device between Ethernet for plant automation (EPA) bus and controller area network (CAN) bus |
| CN105743668A (en) * | 2014-12-09 | 2016-07-06 | 中兴通讯股份有限公司 | Method and device for achieving function of package transmitting and receiving |
| WO2019136983A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Low-delay instruction scheduler |
| CN111752895A (en) * | 2020-06-28 | 2020-10-09 | 北京经纬恒润科技有限公司 | Log storage method and device among multi-system-level chips |
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