CN101958278B - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN101958278B CN101958278B CN 200910054971 CN200910054971A CN101958278B CN 101958278 B CN101958278 B CN 101958278B CN 200910054971 CN200910054971 CN 200910054971 CN 200910054971 A CN200910054971 A CN 200910054971A CN 101958278 B CN101958278 B CN 101958278B
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Abstract
The invention discloses a manufacturing method of a semiconductor device, which comprises the steps of: providing a wafer, wherein a wafer surface comprises a conductive layer and an insulating layer which is positioned above the conductive layer; coating a photomask layer on the surface of the insulating layer; patterning the photomask layer in the center area of the wafer, with the photomask layer on the edge area of the wafer unpatterned; exposing a partial insulating layer in the center area on the wafer; completely covering the insulating layer of the edge area of the wafer; etching the exposed insulating layer; and consequently forming a through hole for exposing the conductive layer in the insulating layer. The defect of the surface of the wafer, caused by chips of conductive impurities, is reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacturing approach of semiconductor device.
Background technology
The making of semiconductor integrated circuit is extremely complicated process, and purpose is various electronic building bricks and circuit that particular electrical circuit is required, dwindles on the wafer that is produced on small size.Wherein, each assembly must be done electric connection by suitable internal connecting line, the competence exertion desired function.
Because the making of integrated circuit is to very lagre scale integrated circuit (VLSIC) (ULSI) development, its inner current densities is increasing, along with contained number of elements in the chip constantly increases, has in fact just reduced the free space of surperficial line.This way to solve the problem is to adopt the design of multiple layer metal lead, utilizes multilayer dielectric layer to be connected with the multilayer of conductive layer mutual superposition, and this wherein just needs to make a large amount of contact holes.
In the manufacturing process of said contact hole, at first need on said insulating barrier, form one deck photo mask layer, then carry out photoetching with this photo mask layer patterning.For example, the photo mask layer that needs is formed the contact hole position is made public, and then the photo mask layer after the exposure becomes and is developed removal easily; Then develop and remove the photo mask layer of being made public.Photo mask layer after being patterned like this just will form the said insulating layer exposing of contact hole position, and the said insulating barrier of other position is covered.Form the mask layer of patterning in photoetching after, utilize plasma etch process that the part of said insulating layer exposing is carried out etching again, thereby form through hole.
In said through hole, just formed contact hole behind the filled conductive material, this contact hole can be realized the conductive interconnection of different conductive layers.For " CN1731286A " name is called in the Chinese patent of " etching method for forming through hole of radio-frequency devices product " a kind of etching method for forming through hole is disclosed at publication number for example.
In semiconductor is made; Entire wafer is divided into the inactive area 10 at edge and the effective coverage 20 (with reference to figure 1) of central authorities; Inactive area is not used for making device usually; For example the wafer of 300mm will think inactive area apart from zone or the zone nearer apart from the edge in the Waffer edge 0.05mm scope, and the part except that inactive area 10 is effective coverage 20.In fabrication of semiconductor device, earlier wafer surface is divided into several different zones usually, on each zone, make a device then; After completing; This wafer is cut apart, inactive area is abandoned again, and the effective coverage is divided into the device of several separation.But; In the manufacture process of device, owing to be on same wafer, to carry out, so the same processing step in all element manufacturing; The etching of contact hole for example; Can in same step, accomplish simultaneously, and better for the consistency that makes the surperficial device of making of entire wafer, and inactive area also can be carried out all processing steps simultaneously.
But, to the wafer sort that utilizes said method forms contact hole in 65nm technology after, a lot of conductive impurity chips of finding on wafer, distributing, thus form defective in wafer surface.Fig. 1 as can beappreciated from fig. 1, utilizes existing method for the resolution chart to the wafer behind the method formation contact hole that utilizes prior art, and then there is the defective that the conductive impurity chip causes in wafer surface.
Summary of the invention
The purpose of this invention is to provide a kind of manufacturing approach of semiconductor device, thereby reduced wafer surface because the defective that the conductive impurity chip causes.
In order to achieve the above object, the invention provides a kind of manufacturing approach of semiconductor device, comprise step:
Wafer is provided, comprises conductive layer, be positioned at the insulating barrier on conductive layer upper strata in said wafer surface;
Apply photo mask layer at said surface of insulating layer;
The said photo mask layer of patterned wafers middle section, and the photo mask layer of wafer edge region do not carry out patterning makes being exposed of partial insulative layer of middle section on the said wafer, and the insulating barrier of wafer edge region is covered fully;
Insulating barrier to exposing carries out etching, thereby in insulating barrier, forms the through hole that exposes said conductive layer.
Optional, said step: the said photo mask layer of patterned wafers middle section, and the step that the photo mask layer of wafer edge region is not carried out patterning comprises:
Wafer surface is divided into the exposure area of arrayed;
Make public in exposure area to comprising middle section;
Making public in exposure area to comprising fringe region, when made public in the exposure area that comprises fringe region, the printing opacity position of the pairing mask of fringe region is blocked;
Photo mask layer on the wafer is developed.
Optional, the material of said photo mask layer is a positive photoresist.
Optional, said wafer edge region comprises apart from 1/300 times of wafer diameter of Waffer edge with interior zone.
Optional, the diameter of said wafer is 300mm, said wafer edge region comprises apart from Waffer edge 1mm with interior zone.
Optional, also comprise the semiconductor device layer that is positioned at said conductive layer lower floor on the said wafer.
Optional, the characteristic size of said process for fabrication of semiconductor device is 65nm or below the 65nm.
Technique scheme of the present invention and prior art relative merit are:
The present invention is through improving the step of the mask layer in the existing formation contact hole method; Make and the photo mask layer of wafer edge region is not made public, thereby insulating barrier is covered by photo mask layer fully, form in the step of contact hole at follow-up etching insulating barrier like this; Owing to there is photo mask layer to do protection; Therefore wafer edge region can not form contact hole, has so just reduced in plasma etching contact hole step, when insulating barrier was worn by quarter; Plasma causes the conductive layer of insulating barrier lower floor on the wafer to be burnt in the Waffer edge point discharge probability, thus the probability reduction that occurs the conductive impurity chip in wafer surface made.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 is the resolution chart to the wafer behind the method formation contact hole that utilizes prior art;
Fig. 2 is the flow chart of manufacturing approach one embodiment of semiconductor device of the present invention;
Fig. 3 to Fig. 8 is the sketch map of manufacturing approach one embodiment of semiconductor device of the present invention;
Fig. 9 is for to utilizing method of the present invention to form the resolution chart of the wafer behind the contact hole.
Embodiment
In semiconductor is made; Entire wafer is divided into inactive area and effective coverage, and inactive area is not used for making device, the for example wafer of 300mm; To can think inactive area apart from the zone in the Waffer edge 0.05mm scope, and the zone except that inactive area is the effective coverage.In fabrication of semiconductor device, earlier said semiconductor wafer is divided into several different zones usually, on each zone, make a device then; After completing; This wafer is cut apart, inactive area is abandoned again, and the effective coverage is divided into the device of several separation.But; In the manufacture process of device, owing to be on same wafer, to carry out, so the same processing step in all element manufacturing; The etching of contact hole for example; Can in same step, accomplish simultaneously, and better for the consistency that makes the surperficial device of making of entire wafer, and inactive area also can be carried out all processing steps with the effective coverage simultaneously.
But to the wafer sort that utilizes said method forms contact hole in 65nm technology after, a lot of conductive impurity chips of finding on wafer, distributing are from forming defective in wafer surface.
Think after inventor's research: because plasma etching is normally put into a circular chamber with wafer; Utilize plasma to wafer engraving then, thus plasma wafer effective coverage and wafer effective coverage with electric charge also different, and plasma wafer edge region with the quantity of electric charge very high; The dielectric layer of working as Waffer edge was like this worn by quarter; When forming contact hole, the conductive layer of lower floor is exposed, and plasma is known from experience the discharge that tapers off to a point in this contact hole position then; Cause the conductive layer of entire wafer conducting to be burnt like this, thereby the chip that is burnt is splashed to wafer surface.Thereby form defective in wafer surface.
The invention provides a kind of manufacturing approach of semiconductor device, comprise step:
Wafer is provided, comprises conductive layer, be positioned at the insulating barrier on conductive layer upper strata in said wafer surface;
Apply photo mask layer at said surface of insulating layer;
The said photo mask layer of patterned wafers middle section, and the photo mask layer of wafer edge region do not carry out patterning makes being exposed of partial insulative layer of middle section on the said wafer, and the insulating barrier of wafer edge region is covered fully;
Insulating barrier to exposing carries out etching, thereby in insulating barrier, forms the through hole that exposes said conductive layer.
Optional, said step: the said photo mask layer of patterned wafers middle section, and the step that the photo mask layer of wafer edge region is not carried out patterning comprises:
Wafer surface is divided into the exposure area of arrayed;
Make public in exposure area to comprising middle section;
Making public in exposure area to comprising fringe region, when made public in the exposure area that comprises fringe region, the printing opacity position of the pairing mask of fringe region is blocked;
Photo mask layer on the wafer is developed.
Optional, the material of said photo mask layer is a positive photoresist.
Optional, said wafer edge region comprises apart from 1/300 times of wafer diameter of Waffer edge with interior zone.
Optional, the diameter of said wafer is 300mm, said wafer edge region comprises apart from Waffer edge 1mm with interior zone.
Optional, also comprise the semiconductor device layer that is positioned at said conductive layer lower floor on the said wafer.
Optional, the characteristic size of said process for fabrication of semiconductor device is 65nm or below the 65nm.
The present invention is through improving the mask layer step in the existing formation contact hole method; Make and the photo mask layer of wafer edge region is not made public, thereby insulating barrier is covered by photo mask layer fully, form in the step of contact hole at follow-up etching insulating barrier like this; Owing to there is photo mask layer to do protection; Therefore wafer edge region can not form contact hole, has so just reduced in plasma etching contact hole step, when insulating barrier was worn by quarter; Plasma causes the conductive layer of insulating barrier lower floor on the wafer to be burnt in the Waffer edge point discharge probability, thus the probability reduction that occurs the conductive impurity chip in wafer surface made.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Embodiment one
Fig. 2 is the flow chart of manufacturing approach one embodiment of semiconductor device of the present invention.Fig. 3 to Fig. 8 is the sketch map of manufacturing approach one embodiment of semiconductor device of the present invention.Wherein, Fig. 3 to Fig. 5 and Fig. 7 to Fig. 8 are generalized section, and Fig. 6 is a schematic top plan view.
With reference to figure 2, a kind of manufacturing approach of semiconductor device comprises step:
S1: wafer is provided, comprises conductive layer, be positioned at the insulating barrier on conductive layer upper strata in said wafer surface.
Concrete, with reference to figure 3, on wafer 100, comprising conductive layer 110, it can be the metal connecting line of various wirings layer, conductive layer 110 also can be source electrode, drain electrode or the grid of MOS device in addition.In a further embodiment, between conductive layer 110 and wafer 100, can also have semiconductor device layer.Said conductive layer 110 is used to realize the wire interconnects of semiconductor device.Have insulating barrier 120 on conductive layer 110 upper stratas, said insulating barrier is used to realize semiconductor device between the metal connecting line of different layers, the perhaps insulation between the grid of MOS device, source electrode and drain electrode and the metal connecting line.
S2: in said insulating barrier 120 surface-coated photo mask layer.
Concrete; With reference to figure 4, this step can be utilized method well known to those skilled in the art, and for example spin-coating method applies photoresist at said insulating barrier 120; Concrete; Earlier photoresist is instiled at the center of wafer, carry out whirl coating then, the rotation through wafer just makes photoresist be evenly distributed to insulating barrier 120 surfaces on the wafer.Said photo mask layer 130 can be DUV (DUV) photoresist layer composition, and for example positivity is the photoresist layer of light source with ArF.
S3: the said photo mask layer of patterned wafers middle section, and the photo mask layer of wafer edge region do not carry out patterning make being exposed of partial insulative layer of middle section on the said wafer, and the insulating barrier of wafer edge region is covered fully.
With reference to figure 5, be specially, on mask 420, have transmission region and light tight zone, through 130 exposures of 420 pairs of photo mask layer of said mask, light is radiated on the photo mask layer 130 from the transmission region of mask 420 with light source 410.In this enforcement, light source can be ultraviolet, electron beam, ion beam and X ray.Because said photo mask layer is a positive photoresist, so can be developed the softening and dissolving of liquid behind the photoresist generation chemical change after illuminated, not have irradiated part then can not be developed the softening and dissolving of liquid.Photo mask layer 130 to after the exposure is carried out development treatment.Soak photo mask layer 130 with the dissolving of chemical development liquid; To wash through the solubilized zone that overexposure causes; So just accurately copy to mask graph in the photomask pattern 130; Thereby the said photo mask layer 130 of wafer middle section is patterned, and needs the insulating barrier 120 of etching to be exposed, and does not need the insulating barrier 120 of etching to be covered by photo mask layer 130.
In the present invention, concrete, extremely shown in Figure 7 like Fig. 6; Wherein Fig. 6 is a vertical view; Fig. 7 is a cutaway view, and wafer surface is divided into some exposure areas (among Fig. 6 vertical line and horizontal line enclose intersect the zone fence up) of arrayed, is made public in said exposure area one by one.At first adopt above-mentioned exposure method, to the exposure area at wafer middle section 115 places, for example make public in exposure area 116.When making public when comprising the exposure area of fringe region 117; For example during exposure area 118; Utilize shadow shield 430 (with reference to figure 7) that the position of corresponding wafer edge region 117 on the mask 420 is blocked in the present embodiment, thereby after exposure, in the exposure area that comprises fringe region 117 of the above exposure of wafer; The photo mask layer of fringe region 117 is not made public, and the photo mask layer of middle section 115 is made public.Because light exists diffraction and interference effect, guaranteed that like this exposure in the middle section 115 adjacent with fringe region is not affected because fringe region 117 does not make public.Therefore when guaranteeing that middle section 115 is by normal exposure, also kept fringe region 117 and do not made public.
Originally be that 1mm among the embodiment is for illustrating; If the diameter of wafer changes certainly; The fringe region of said wafer also can change; Said fringe region is apart from the zone of Waffer edge less than 1/300 times of wafer diameter, and perhaps said wafer edge region also can be set according to the scope that produces defective, and for example defective occurs in the zone of Waffer edge 0.1mm; Then said fringe region can be set at apart from the zone of Waffer edge 0.1mm, can reach the purpose of saving wafer material like this.
Inactive area that in addition also can wafer is set to said fringe region, can reach the purpose of saving wafer material so that the effective coverage of wafer can be utilized fully like this.
Certainly, in other embodiments, said fringe region also can because as long as the part photomask layer that keeps in the wafer edge region does not make public, then will reduce because the defective that point discharge brought in the etching process for apart from the zone of Waffer edge greater than 0mm.
Can also comprise in addition and made public in the exposure area that only comprises fringe region 117, in this step of exposure, the light transmission part on the mask 420 blocked fully.
After the photo mask layer on the entire wafer 130 is accomplished exposure, after then developing, just formed the photo mask layer 130a of patterning as shown in Figure 8.
S4: the insulating barrier to exposing carries out etching, thereby in insulating barrier, forms the through hole that exposes said conductive layer.
Concrete, this etch step can be utilized method well known to those skilled in the art, for example plasma etching.Because this step is the step that adopts usually in the prior art, therefore repeat no more.When this step etching, because the photo mask layer of wafer edge region 117 has been protected the insulating barrier 120 of its lower floor, so insulating barrier 120 can not be etched, and so just can not form defective because of point discharge.
After the manufacture process of accomplishing each regional semiconductor device on the semiconductor wafer, according to the Region Segmentation of dividing before, wafer middle section 115 pairing semiconductor device are exactly the qualified semiconductor device that finally obtains with said semiconductor wafer.
Fig. 9 is for to utilizing method of the present invention to form the resolution chart of the wafer behind the contact hole, and as shown in Figure 9, as can be seen from the figure defective significantly reduces.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (6)
1. the manufacturing approach of a semiconductor device is characterized in that, comprises step:
Wafer is provided, comprises conductive layer, be positioned at the insulating barrier on conductive layer upper strata in said wafer surface;
Apply photo mask layer at said surface of insulating layer;
The said photo mask layer of patterned wafers middle section, and the photo mask layer of wafer edge region do not carry out patterning make that the partial insulative layer of middle section is exposed on the said wafer, and the insulating barrier of wafer edge region is covered fully;
Insulating barrier to exposing carries out etching, thereby in insulating barrier, forms the through hole that exposes said conductive layer;
Wherein, the said photo mask layer of said patterned wafers middle section, and the step that the photo mask layer of wafer edge region is not carried out patterning comprises:
Wafer surface is divided into the exposure area of arrayed;
Make public in exposure area to all being positioned at said middle section;
A part is positioned at the exposure area that said middle section another part is positioned at said fringe region makes public, block a part being positioned at the printing opacity position that will be positioned at the pairing mask of part of said fringe region when make public in exposure area that said middle section another part is positioned at said fringe region;
Photo mask layer on the wafer is developed.
2. the manufacturing approach of semiconductor device according to claim 1 is characterized in that, the material of said photo mask layer is a positive photoresist.
3. the manufacturing approach of semiconductor device according to claim 2 is characterized in that, said wafer edge region comprises apart from 1/300 times of wafer diameter of Waffer edge with interior zone.
4. the manufacturing approach of semiconductor device according to claim 3 is characterized in that, the diameter of said wafer is 300mm, and said wafer edge region comprises apart from Waffer edge 1mm with interior zone.
5. the manufacturing approach of semiconductor device according to claim 1 is characterized in that, also comprises the semiconductor device layer that is positioned at said conductive layer lower floor on the said wafer.
6. the manufacturing approach of semiconductor device according to claim 1 is characterized in that, the characteristic size of said process for fabrication of semiconductor device is 65nm or below the 65nm.
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| CN 200910054971 CN101958278B (en) | 2009-07-16 | 2009-07-16 | Manufacturing method of semiconductor device |
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| CN 200910054971 CN101958278B (en) | 2009-07-16 | 2009-07-16 | Manufacturing method of semiconductor device |
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| CN101958278A CN101958278A (en) | 2011-01-26 |
| CN101958278B true CN101958278B (en) | 2012-12-12 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102456542A (en) * | 2010-10-19 | 2012-05-16 | 华邦电子股份有限公司 | Semiconductor manufacturing process |
| CN107367910B (en) * | 2017-08-28 | 2018-09-28 | 睿力集成电路有限公司 | Photoetching offset plate figure method, the preparation method of semiconductor structure and semiconductor equipment |
| CN111799179B (en) * | 2020-07-31 | 2022-03-18 | 武汉新芯集成电路制造有限公司 | Method for forming semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101089734A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Cleaning method for photoetching glue residue |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101089734A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Cleaning method for photoetching glue residue |
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