CN101919046A - 采用双金属镶嵌工艺和压印光刻形成三维存储器阵列中的存储器线和通路的方法和装置 - Google Patents
采用双金属镶嵌工艺和压印光刻形成三维存储器阵列中的存储器线和通路的方法和装置 Download PDFInfo
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- CN101919046A CN101919046A CN2008801236724A CN200880123672A CN101919046A CN 101919046 A CN101919046 A CN 101919046A CN 2008801236724 A CN2008801236724 A CN 2008801236724A CN 200880123672 A CN200880123672 A CN 200880123672A CN 101919046 A CN101919046 A CN 101919046A
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- memory
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- imprint lithography
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- 230000015654 memory Effects 0.000 title claims abstract description 174
- 238000001459 lithography Methods 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 65
- 230000008569 process Effects 0.000 title claims abstract description 22
- 238000003491 array Methods 0.000 title abstract description 4
- 230000009977 dual effect Effects 0.000 title description 9
- 239000000463 material Substances 0.000 claims abstract description 55
- 238000012546 transfer Methods 0.000 claims abstract description 47
- 230000015572 biosynthetic process Effects 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 8
- 238000007373 indentation Methods 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 79
- 239000000126 substance Substances 0.000 description 6
- -1 3-acryl propoxyl Chemical group 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000007654 immersion Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000016 photochemical curing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- KUDUQBURMYMBIJ-UHFFFAOYSA-N 2-prop-2-enoyloxyethyl prop-2-enoate Chemical compound C=CC(=O)OCCOC(=O)C=C KUDUQBURMYMBIJ-UHFFFAOYSA-N 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- GUHKMHMGKKRFDT-UHFFFAOYSA-N 1785-64-4 Chemical compound C1CC(=C(F)C=2F)C(F)=C(F)C=2CCC2=C(F)C(F)=C1C(F)=C2F GUHKMHMGKKRFDT-UHFFFAOYSA-N 0.000 description 1
- 229930185605 Bisphenol Natural products 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- 241000790917 Dioxys <bee> Species 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 208000034189 Sclerosis Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- QQWICBKIBSOBIT-WXUKJITCSA-N [(e)-2-(4-bicyclo[4.2.0]octa-1(6),2,4-trienyl)ethenyl]-[[(e)-2-(4-bicyclo[4.2.0]octa-1(6),2,4-trienyl)ethenyl]-dimethylsilyl]oxy-dimethylsilane Chemical compound C1=C2CCC2=CC(/C=C/[Si](C)(O[Si](C)(C)\C=C\C=2C=C3CCC3=CC=2)C)=C1 QQWICBKIBSOBIT-WXUKJITCSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- CBFPXJNABCOVCA-UHFFFAOYSA-N [B].[P].CCO[Si](OCC)(OCC)OCC Chemical compound [B].[P].CCO[Si](OCC)(OCC)OCC CBFPXJNABCOVCA-UHFFFAOYSA-N 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical group C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1021—Pre-forming the dual damascene structure in a resist layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Shaping Of Tube Ends By Bending Or Straightening (AREA)
Abstract
Description
Claims (73)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/967,638 US8466068B2 (en) | 2007-12-31 | 2007-12-31 | Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography |
US11/967,638 | 2007-12-31 | ||
PCT/US2008/088628 WO2009088922A2 (en) | 2007-12-31 | 2008-12-31 | Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101919046A true CN101919046A (zh) | 2010-12-15 |
CN101919046B CN101919046B (zh) | 2013-11-06 |
Family
ID=40797036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200880123672.4A Expired - Fee Related CN101919046B (zh) | 2007-12-31 | 2008-12-31 | 采用双金属镶嵌工艺和压印光刻形成三维存储器阵列中的存储器线和通路的方法和装置 |
Country Status (7)
Country | Link |
---|---|
US (2) | US8466068B2 (zh) |
EP (1) | EP2227823A4 (zh) |
JP (1) | JP2011508459A (zh) |
KR (1) | KR20100120117A (zh) |
CN (1) | CN101919046B (zh) |
TW (1) | TW200943491A (zh) |
WO (1) | WO2009088922A2 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107946237A (zh) * | 2017-11-23 | 2018-04-20 | 长江存储科技有限责任公司 | 三维存储结构连线方法、存储结构、存储器及电子设备 |
CN110391242A (zh) * | 2019-07-31 | 2019-10-29 | 中国科学院微电子研究所 | L形台阶状字线结构及其制作方法及三维存储器 |
US10535669B2 (en) | 2017-11-23 | 2020-01-14 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100944605B1 (ko) * | 2007-12-24 | 2010-02-25 | 주식회사 동부하이텍 | 반도체 소자 |
US20100301449A1 (en) * | 2007-12-31 | 2010-12-02 | Sandisk 3D Llc | Methods and apparatus for forming line and pillar structures for three dimensional memory arrays using a double subtractive process and imprint lithography |
US8466068B2 (en) | 2007-12-31 | 2013-06-18 | Sandisk 3D Llc | Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography |
JP4945609B2 (ja) * | 2009-09-02 | 2012-06-06 | 株式会社東芝 | 半導体集積回路装置 |
EP2494586A2 (en) | 2009-10-26 | 2012-09-05 | Sandisk 3D LLC | Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning |
EP2686883B1 (en) * | 2011-03-29 | 2015-07-01 | Hewlett-Packard Development Company, L.P. | Dual-plane memory array |
US9230611B2 (en) | 2011-11-04 | 2016-01-05 | Hewlett Packard Enterprise Development Lp | Structure of a switching device in an array |
US20140353019A1 (en) * | 2013-05-30 | 2014-12-04 | Deepak ARORA | Formation of dielectric with smooth surface |
US9728584B2 (en) | 2013-06-11 | 2017-08-08 | Micron Technology, Inc. | Three dimensional memory array with select device |
KR102449571B1 (ko) * | 2015-08-07 | 2022-10-04 | 삼성전자주식회사 | 반도체 장치 |
TWI562281B (en) * | 2015-08-07 | 2016-12-11 | Macronix Int Co Ltd | Memory device and method of manufacturing the same |
US9812502B2 (en) | 2015-08-31 | 2017-11-07 | Toshiba Memory Corporation | Semiconductor memory device having variable resistance elements provided at intersections of wiring lines |
KR102475454B1 (ko) | 2016-01-08 | 2022-12-08 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법 |
US10354912B2 (en) * | 2016-03-21 | 2019-07-16 | Qualcomm Incorporated | Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) |
KR102673120B1 (ko) * | 2016-12-05 | 2024-06-05 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US11156914B2 (en) * | 2017-02-10 | 2021-10-26 | Northeastern University | Damascene template for nanoelement printing fabricated without chemomechanical planarization |
US11121143B2 (en) * | 2019-05-24 | 2021-09-14 | Micron Technology, Inc. | Integrated assemblies having conductive posts extending through stacks of alternating materials |
JP7414597B2 (ja) | 2020-03-12 | 2024-01-16 | キオクシア株式会社 | 配線形成方法 |
JP7458948B2 (ja) | 2020-09-17 | 2024-04-01 | キオクシア株式会社 | テンプレート、テンプレートの製造方法、及び半導体装置の製造方法 |
JP7438904B2 (ja) | 2020-09-17 | 2024-02-27 | キオクシア株式会社 | テンプレート、テンプレートの製造方法、及び半導体装置の製造方法 |
JP2022076684A (ja) * | 2020-11-10 | 2022-05-20 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010050385A1 (en) * | 1999-04-28 | 2001-12-13 | Kotecki David E. | Method for simultaneously forming a storage-capacitor electrode and interconnect |
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CN107946237A (zh) * | 2017-11-23 | 2018-04-20 | 长江存储科技有限责任公司 | 三维存储结构连线方法、存储结构、存储器及电子设备 |
CN110100307A (zh) * | 2017-11-23 | 2019-08-06 | 长江存储科技有限责任公司 | 三维存储器件及其制作方法 |
US10535669B2 (en) | 2017-11-23 | 2020-01-14 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
US10770468B2 (en) | 2017-11-23 | 2020-09-08 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
CN110100307B (zh) * | 2017-11-23 | 2021-08-03 | 长江存储科技有限责任公司 | 三维存储器件及其制作方法 |
CN110391242A (zh) * | 2019-07-31 | 2019-10-29 | 中国科学院微电子研究所 | L形台阶状字线结构及其制作方法及三维存储器 |
CN110391242B (zh) * | 2019-07-31 | 2021-08-20 | 中国科学院微电子研究所 | L形台阶状字线结构及其制作方法及三维存储器 |
Also Published As
Publication number | Publication date |
---|---|
US20090166682A1 (en) | 2009-07-02 |
US8466068B2 (en) | 2013-06-18 |
US20130264675A1 (en) | 2013-10-10 |
JP2011508459A (ja) | 2011-03-10 |
EP2227823A2 (en) | 2010-09-15 |
CN101919046B (zh) | 2013-11-06 |
KR20100120117A (ko) | 2010-11-12 |
WO2009088922A3 (en) | 2009-09-24 |
EP2227823A4 (en) | 2012-04-18 |
WO2009088922A2 (en) | 2009-07-16 |
TW200943491A (en) | 2009-10-16 |
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