CN101840928B - 带有自对准存储元件的多晶硅柱双极晶体管 - Google Patents
带有自对准存储元件的多晶硅柱双极晶体管 Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
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Abstract
本发明提出一种具有自对准于双极接面晶体管存取装置的射极的存储元件的存储单元及此种装置的制造方法。在此所述的储存装置包括多个存储单元。在这些存储单元中的存储单元包含一包括射极的双极接面晶体管(BJT),该射极包括掺杂的多晶硅柱。这样的存储单元包含一个在射极上的绝缘元件,且绝缘元件具有一个延伸穿过绝缘层的开口,这个开口在射极上的中心。而这些存储单元还包含在开口中的一存储元件,且此一存储元件与上述射极电性相连。
Description
技术领域
本发明是有关于一种以相变存储材料(phase change based memorymaterials)为基础的高密度储存装置(memory devices),且相变存储材料包括硫属材料(chalcogenide based materials)及其它可编程电阻材料(programmable resistive material),以及制造这种装置的方法。
背景技术
相变存储材料如硫属材料及类似的材料,可由供应适于施行在集成电路中的程度的电流,而导致非晶态与结晶态之间的相变化。一般的非晶态的特点是具有比一般的结晶态更高的电阻值(electrical resistivity),这能被立即感测出用以表示数据(data)。这样的特性已经引发使用可编程电阻材料来形成非挥发性存储器电路的关注,这能随机存取的进行读与写。
从非晶态到结晶态的变化通常是一种较低电流操作。而在此被称为重置(reset)的从结晶态到非晶态的变化通常是一种较高电流操作,其包含一个短的高电流密度脉冲(pulse),以便熔化或打断结晶结构,之后迅速冷却相变材料,将被熔化的相变材料淬火并使至少部分的相变材料于非晶态中稳定。
因为相变化的发生是由于加热使然,所以为了加热相变材料及诱使所需的相变化,需要相当大的电流。由于场效晶体管的相对低的电流驱动,因而在获得具有场效晶体管存取装置的相变化存储单元(cell)所需的电流上产生问题。
虽然双极接面晶体管可提供比场效晶体管还要大的电流驱动,但是双极接面晶体管与CMOS周边电路的整合(integration)困难且可能导致高度复杂的设计与工艺。
由降低单元中的相变存储元件尺寸可降低电流的量,以便以通过相变存储元件的小绝对电流值(absolute current values)达到较高的电流密度。然而,在制造具有极小尺寸的装置及在制造符合大尺寸高密度储存装置(largescale high-density memory device)所需的严格的允差条件(tolerancerequirement)所需的工艺上的变化的装置产生问题。
因此需要提供带双极接面晶体管存取装置的相变存储单元,来满足与CMOS周边电路在设计整合上的复杂性并在相同集成电路上可兼容于周边电路的制造。而且,需要提供制造满足大尺寸高密度储存装置所需的严格的允差条件的相变存储单元的方法。
发明内容
在此描述具有自对准于双极接面晶体管(bipolar junction transistor,BJT)存取装置的射极的存储元件(element)的存储单元。在此描述的一种储存装置(device)包括多个存储单元。这些存储单元中的存储单元包括一双极接面晶体管,双极接面晶体管包括一射极,射极包括一掺杂多晶硅柱(pillar ofdoped polysilicon)。在射极上有一绝缘元件,并具有延伸穿过绝缘元件的一开口,这个开口位在射极上的中心。在开口内还有一存储元件与射极电性相连。
具体而言,在形成牺牲元件期间可形成上述射极,这个牺牲元件是用来定义后续形成的存储元件的位置。之后去除牺牲元件,以于射极上定义一个介层窗(via),而在上述介层窗中形成绝缘元件。上述存储元件是形成在一个由绝缘元件所定义的一开口中。可由造成在存储元件的次光刻宽度(sublithographic width)的很小变化的工艺形成横过存储单元的一阵列的这个由绝缘元件所定义的开口。
在此描述的一个存储单元造成在能被做得极小的存储元件内的主动区(active region),由此降低诱使相变化所需的电流的量(magnitude)。由绝缘元件所定义的开口中的存储元件的宽度小于掺杂多晶硅柱的宽度与作为射极的导体盖(conductive cap),较佳是比一个如光刻工艺的最小特征长度(feature size)还小,上述的工艺是指用于形成掺杂多晶硅柱、导体盖与位线的工艺。而小的宽度会集中存储元件内的电流密度,由此降低主动区中诱使相变化所需的电流的量。此外,绝缘元件可提供主动区一些热绝缘(thermal isolation),以促进降低诱使相变化必需的电流量(amount ofcurrent)。而且,存储元件的剩余部分可为主动区提供与位线的热绝缘。
在此描述的一种制造一储存装置的方法包括形成具有一第一导电态的一单晶基底(single-crystalline substrate)。然后在单晶基底中形成多个介电沟渠(dielectric trenches),并在单晶基底中形成多个字符线。介电沟渠其中之一的介电沟渠隔开相邻的字符线。然后,在单晶基底中上形成一种结构,这种结构包括掺杂多晶硅材料、在掺杂多晶硅材料上的导电盖材料以及在导电盖材料上的牺牲材料(sacrificial material)。接着,图案化上述结构,以在字符线上形成多个叠层(stacks)。之后,在叠层的侧壁上形成多个侧壁间隔物(sidewall spacers)。然后,去除牺牲材料,以定义出多个介层窗(via),并在介层窗内形成一绝缘层,这个绝缘层定义出多个开口。然后,在开口中形成多个存储元件,且在存储元件上形成多个位线。
在此描述的实施例中,可同时制造在周边区(peripheral region)的逻辑装置以及在存储区具有双极接面晶体管的存储单元。在存储区与周边区内先形成栅极介电材料。然后去除存储区内的栅极介电材料,以及在存储区与周边区内形成一层掺杂多晶硅材料以及一层导电盖材料。之后,使用掺杂多晶硅材料及导电盖材料来一起形成逻辑装置的栅极与双极接面晶体管存取装置(access devices)的射极。结果,在此描述的储存装置将包括带有双极接面晶体管存取装置相变存储单元(phase change memory cells)与CMOS周边电路,且满足设计整合与工艺的复杂性(complexity)。
附图说明
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下,其中:
图1是在此描述的一种借着使用具有带多晶硅射极与自对准存储元件(self-aligned memory elements)的双极接面晶体管(BJT)的存储单元实现的一部分的存储单元阵列的示意图。
图2A与图2B显示排列于阵列中的一部分的存储单元的剖面图,图2A是沿着位线以及图2B是沿着字符线。
图3A显示类似图2A~图2B的实施例的一第二实施例的剖面图,并在位线的较高掺杂区的顶面上有包括硅化物的一顶导体。
图4~图17B显示一种制造在此描述的具有带多晶硅射极与自对准存储元件的双极接面晶体管的存储单元的阵列的制作顺序的步骤。
图18~图21显示一种针对在图5A~图5B中显示的形成字符线的替代实施例。
图22是一种集成电路的简化的方块图,前述集成电路包括在此描述的一种借着使用具有带多晶硅射极与自对准存储元件的双极接面晶体管的存储单元实现的存储单元阵列。
具体实施方式
本文揭露的下列描述是作为代表地关于具体的结构实施例与方法。应知这些描述并没有要将揭露的内容限制在这些具体披露的实施例与方法中,而是可使用其它特征、元件、方法与实施例来实践揭露的内容。所述的较佳实施例是用以解说本发明而非用以限制其范围,应以权利要求范围定义为准。所属技术领域中具有通常知识者应理解在下文描述上多种相等的变更(variation)。在各个实施例中相似的元件通常参照相似的元件符号。
图1显示在此描述的一种借着使用具有带多晶硅射极与自对准存储元件(self-aligned memory elements)的双极接面晶体管(BJT)的存储单元实现的一部分的存储单元阵列100的示意图。
如图1的示意图所示,阵列100的每个存储单元包括排列成电性串联(electrical series)的一双极接面晶体管存取装置与一存储元件,所述的存储元件能被设定成多个阻态(resistive states)中之一并因此能储存一或多个位的数据(data)。
阵列100包括多个字符线130,其包含并联延伸于第一方向且与字符线译码器/驱动器(decoder/driver)150电性相连的字符线130a、130b、130c、130d。字符线130连至阵列100的双极存取晶体管的基极端(baseterminals)。
包含位线120a、120b、120c、120d的多个位线120并联延伸于第二方向且与位线译码器160电性相连。而各别的双极接面晶体管的射极端经由存储元件连至一对应位线120。
阵列100的存储单元连接成一共集极组态(common collectorconfiguration)。在一共集极组态中,存储单元的集极端是连至一固定的参考电压(reference voltage),且输入与输出分别为基极端与射极端。因此,在操作时于位线120与字符线130上的电压会感应一电流经由射极端与存储元件自位线120到集极端,或者反之亦然。
在图1中,集极端连到地线(ground)。集极端还可选择连至一电压源,以供应有别于地线的一参考电压。比如请参见图22的偏压配置供应电压、电流电源(Biasing Arrangement Supply Voltages,Current Sources)2236。
存储单元110是代表阵列100的存储单元并包括排列为电性串联的双极接面晶体管115与相变存储元件125。双极接面晶体管115的基极端连至字符线130b,而晶体管115的射极端经由相变存储元件125连至位120b。
可由供应适当的电压以及/或是电流至对应字符线130b与对应位线120b,以感应一电流通过所选的存储单元110,来达成读取或写入阵列100的存储单元110。所供应的电压/电流的位准(level)与持续期间(duration)是依据所施行的操作如读取操作或写入操作而定。
在存储单元110的一重置(擦除)操作中,供应一重置脉冲(reset pulse)至字符线130b并使位线120b经由存储元件125感应一电流,以引起存储元件125的主动区的转变(transition)成为一非晶相,从而使这个相变材料成为一个电阻值在重置状态的范围内的电阻。所述的重置脉冲是一个相当高的能量脉冲,足以提高存储元件125的至少主动区的温度到相变材料的转变(结晶)温度以上并且也在熔化温度以上,以便让至少主动区处在液态。之后迅速终止所述的重置脉冲,导致一个相当快的淬火时间而主动区迅速冷却至转变温度以下,以使主动区稳定至一般的非晶相。
在存储单元110的一设置(或编程)操作中,供应一编程脉冲到适合的振幅与持续期间的字符线130b与位线120b,以经由存储单元110感应一个电流,此电流足以提高至少一部分的主动区的温度到转变温度以上以及导致至少一部分的主动区从非晶相转变成结晶相,这样的转变将减少存储元件125的电阻并使存储单元110处于所要的状态。
在储存于存储单元110中的数据值的一读取(或感测)操作中,供应一读取脉冲到适合的振幅与持续期间的对应字符线130b和对应位线120b,以感应电流流动而不会使存储元件125经历电阻状态(resistive state)的变化。流经存储单元110的电流是依据存储元件125的电阻而定,并因而使数据值储存于存储单元110中。因此,存储单元的数据状态,例如可由比较位线120b上的电流与方块165的感测放大器(sense amplifiers)的适当的参考电流来确定。
图2A与图2B显示排列于阵列100中的一部分的存储单元(包括代表的存储单元110)的剖面图,图2A是沿着位线120以及图2B是沿着字符线130。
阵列100包括在一单晶半导体基底200上的一存储区280与一周边区(periphery region)285。周边区285包括逻辑装置286,其具有在一栅极介电层293上与基底200上的一栅极结构287,以及作为源极区和漏极区的掺杂区288、289。栅极结构287包括在一掺杂多晶硅部分290上的一导电盖291,以及位于导电盖291与掺杂多晶硅部分290的侧壁上的介电间隔物(dielectric spacer)292。导电盖291包括一种包含例如Ti、W、Co、Ni或Ta的硅化物。一种导电插塞295连至掺杂区288并延伸到介电质294的顶面,以接触位线120b,所述介电质294包括一层或多层的介电材料。一种导电插塞296则连至掺杂区289并延伸到介电质294的顶面,以接触导线297。
存储区280包括位于基底200中具有一第一导电态(conductivity type)的阱202,而这个阱202包括一个第一掺杂区205与一个比第一掺杂区205更高掺杂的第二掺杂区210。基底200还包括位在阱202内并延伸于第一方向的字符线130,此处的第一方向是进入并穿出图2A所示的剖面,且字符线130在阱中被介电沟渠(沟渠隔离结构)230隔间,其中介电沟渠230包括介电材料。字符线130具有相对于第一导电态的一第二导电态。
存储单元110包括一掺杂多晶硅柱(doped polysilicon pillar)220,掺杂多晶硅柱220接触对应的字符线130b。掺杂多晶硅柱220比掺杂多晶硅柱220下面的字符线130b部分的掺杂要更高。因此,柱220与字符线130b在接近界面222处定义出一个pn接面,所述界面222大半是在字符线130b内部。
存储单元110包括在掺杂多晶硅柱220的一导电盖240。在说明的实施例中,导电盖240包括一种包含例如Ti、W、Co、Ni或Ta的硅化物。导电盖240在掺杂多晶硅柱220与存储元件125之间提供一低电阻接触(resistance contact),以由提供一个比柱220的多晶硅材料更高导电性的接触面来帮助维持操作期间的掺杂多晶硅柱220中的电流一致(uniformity),且导电盖240可以在柱220上面的材料的选择性蚀刻期间作为掺杂多晶硅柱220的保护蚀刻中止层(protective etch stop layer)使用。在一些实施例中,可省略导电盖240。
掺杂多晶硅柱220与导电盖240延伸穿过介电质270。在说明的实施例中,介电质270包括硼磷硅玻璃(boro-phospho-silicate glass,BPSG)或磷硅玻璃(PSG)。
如图2B中所示,字符线130包括掺杂多晶硅柱220之间的区域,其比间隔物260和掺杂多晶硅柱220底下的区域的掺杂要高,这个较高掺杂区帮助改善字符线130的导电率(electrical conductivity)并因此降低字符线130的负载(loading)和改善阵列的一致性(uniformity)。此外,掺杂多晶硅柱220底下的字符线130的较淡掺杂区能增加其间的pn接面的崩溃电压(breakdown voltage)。
掺杂多晶硅柱220与导电盖240作为存储单元110的双极接面晶体管115的射极。在柱220底下的一部分的字符线130b作为存储单元110的双极接面晶体管115的基极。在字符线130b底下的一部分的阱作为存储单元110的双极接面晶体管115的集极。
导电接触窗215连接阱202的第二掺杂区210与导电材料140,所述导电材料140连到一参考电压。
在说明的实施例中,掺杂多晶硅柱220包括高掺杂N型(N++)多晶硅、字符线130包括基底200中掺杂P型材料的区域、第一掺杂区205包括基底200中掺杂N型材料的区域、第二掺杂区210包括基底200中高掺杂N型(N+)材料的区域,从而形成npn双极晶体管115。
在一可替代的实施例中,掺杂多晶硅柱220包括高掺杂P型(P++)多晶硅、字符线130包括基底200中掺杂N型材料的区域、第一掺杂区205包括基底200中掺杂P型材料的区域、第二掺杂区210包括基底200中高掺杂P型(P+)材料的区域,从而形成pnp双极晶体管115。
存储元件125是位于一个由一绝缘元件245定义的开口中,并电性连接导电盖240与位线120b。结果是存储元件125具有带有一表面积的底面,该表面积小于射极的顶面的表面积。存储元件125例如可包括选自Ge、Sb、Te、Se、In、Ti、Ga、Bi、Sn、Cu、Pd、Pb、Ag、S、Si、O、P、As、N与Au的族群中的一种或多种材料。
绝缘元件245较佳是包括可阻止存储元件125的存储材料的扩散(diffusion)的材料。在一些实施例中,为了下文更详细讨论的理由,绝缘元件245的材料可选择低导热系数(thermal conductivity)的材料。
位线120(包含作为存储单元110的顶电极的位线120b)延伸进入并穿出图2B所示的剖面。在说明的实施例中,位线120包括接触存储单元的一第一导电层以及位于第一导电层上的一第二导电层。位线120也可选择包括一单一导电层。
位线120具有双层的优势包括为了与存储元件125的材料兼容而选择第一导电层的材料,同时为了其它优点如比第一导电层的材料高的导电率,而选择第二导电层的材料。在说明的实施例中,第一导电层包括TiN及第二导电层包括Al。在存储元件125包括GST(将于下文讨论)的实施例中TiN适于作为第一导电层,因为其可与GST有良好的接触,TiN是一种用于半导体制造的一般材料,且其提供了一个良好的扩散阻挡(diffusionbarrier)。第一导电层还可选择是TaN、TiAlN或TaAlN。
作为另外的例子,位线120的第一与第二导电层各自可包括选自包含Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、N、O与Ru的族群与其组合中的一种或多种元素。
在说明的实施例中,导电材料140和导线297也包括第一与第二导电层如同位线120的第一与第二导电层。此外,导电材料140和导线297各自可包括一层或多层的材料,其例如各自包括上述所讨论有关位线120的一种或多种元素。
绝缘元件245具有侧面(sides)246,其垂直对准于射极(掺杂多晶硅柱220与导电盖240)的侧面221,以便定义出侧壁262。还有一个包括介电材料的侧壁间隔物260位在侧壁262上以及围绕射极和绝缘元件245。
当投影于射极上时,射极的侧面221在射极上方定义出一个柱面(cylinder)。在图2A~图2B的说明的实施例中,由侧面221定义的柱面如同绝缘元件245的侧面246。在说明的实施例中,因为射极圆形的剖面,所以具有由射极的侧面221定义的柱面具有一圆形的剖面。由射极的侧面221定义的柱面根据射极的剖面形状,也可选择具有方形(square)、椭圆形、矩形或稍微不规则形状的剖面。
在图2A~图2B中所示的剖面图中,绝缘元件245具有一个开口,放在由射极的侧面221定义的柱面内的中心,而存储元件125是置于开口中并自对准于射极(掺杂多晶硅柱220与导电盖240)。在下面有关图4~图17所更加详细描述的制造实施例中,掺杂多晶硅柱220与导电盖240是在材料的图案化期间形成,而所述图案化是用以定义出后续形成的绝缘元件245与存储元件125的位置。然后,形成间隔物260再选择性去除被图案化的材料,以形成一个由间隔物260定义并位在导电盖240上的介层窗。接着,在介层窗内形成绝缘元件245并具有一个放在导电盖240的中心的开口,再于由绝缘元件245所定义的开口内形成存储元件125。
再者在下面有关图4~图17所更加详细描述中,在存储区与周边区内形成栅极介电材料。自存储区去除所述栅极介电材料,然后在存储区与周边区内形成一层掺杂多晶硅材料和一层导电盖材料。之后利用该层掺杂多晶硅材料的材料和该层导电盖材料形成逻辑装置的栅极与双极接面晶体管存取装置的射极。结果,于此描述的储存装置包括带有与CMOS周边电路兼容的双极接面晶体管存取装置并满足设计整合与工艺的相变存储单元。
在操作中,在位线120b上的电压以及字符线130b可感应一电流经由存储单元110从射极流到集极。
主动区128是存储元件125的区域,在其中存储材料被诱使而在至少两种固相之间改变。应知道在说明的结构中,所述主动区128可做得极小,由此降低诱使相变化所需的电流的量。在由绝缘元件245所定义的开口内的存储元件125的宽度129小于掺杂多晶硅柱220与导电盖240的宽度,且较佳是小于用来形成掺杂多晶硅柱220、导电盖240与位线120的工艺(如光刻工艺)的最小特征尺寸(feature size)。小的宽度129集中了存储元件125内的电流密度,由此降低诱使主动区128中的相变化所需的电流的量。此外,绝缘元件245可提供主动区128的一些热隔绝,这也能帮助降低诱使相变化所需的电流量。再者,存储元件125的剩余部分可提供主动区128一些来自位线120b的热隔绝。
如上所述,双极接面晶体管可提供比场效晶体管大的电流驱动。此外,因为晶体管的射极包括掺杂多晶硅材料,所以能得到一相当大的电流增益(gain),从而降低在位线120b上诱使存储元件中的相变化所需的电流量。在字符线130上的降低的电流量降低了共享同一字符线的装置间的串音(cross-talk),进而改善阵列的功效。在字符线130上的降低的电流也能避免寄生BJT行为(parasitic BJT behavior),亦即一个邻近的存储单元中的射极变成一个集极。
图3A显示类似图2A~图2B的实施例的的第二实施例的剖面图,其中有一个顶导体(top conductor)300,其包括字符线130的该较高掺杂区的顶面上的硅化物。顶导体300包括一种包含例如Ti、W、Co、Ni或Ta的硅化物。顶导体300增加了字符线130的导电率(electrical conductivity)并且因此降低字符线130的开启电流(turn on current)与负载,从而导致阵列的一致性(uniformity)。包括硅化物的顶导体300也可除去来自字符线130的少数载子以避免寄生BJT行为。同时,如图21所示,在一些实施例中,在字符线130的侧壁上形成包括硅化物的侧壁导体1900。侧壁导体1900可除去来自字符线的少数载子并增进字符线130的导电率。
于此描述的存储单元的实施例包括用于存储元件的相变存储材料,包括硫属材料或其它材料。硫属(chalcogens)包括这四个元素氧(O)、硫(S)、硒(Se)与碲(Te)中的任一种,其形成周期表的部分VIA族。硫族化合物包括一种硫属与一种较正电性的元素或根(radical)的化合物。硫族化合物合金包括硫族化合物与其它如过渡金属的其它材料的组成物。一种硫族化合物合金通常包含一或多种元素,其来自元素周期表的IVA族,如锗(Ge)和锡(Sn)。硫族化合物合金总是包括锑(Sb)、镓(Ga)、铟(In)、银(Ag)其中之一或多种的组成物。很多相变存储材料已经描述于技术文献中,包括:Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te和Te/Ge/Sb/S的合金。在Ge/Sb/Te合金的家族中,广范围的合金混合物(compositions)也许是可行的。所述混合物可以TeaGebSb100-(a+b)作为特征。已有研究者描述最有用的合金,其在沉积材料中具有Te的平均浓度在70%以下,典型是在60%以下并且一般是在低到约23%及高到约58%Te的范围,最适宜地是约48%~58%。Ge的浓度在约5%以上且在材料中平均从约8%的低点到约30%的范围,剩下的通常低于50%。最适当的是Ge的浓度在约8%到约40%的范围。而此一混合物中的主要组成元素的余料是Sb。这些百分比是组成元素的原子的全部100%的原子百分比(atomic percentages)。(Ovshinsky的美国专利5687112的第10~11栏)。由其它研究者提出的特定合金包括Ge2Sb2Te5、GeSb2Te4与GeSb4Te7(Noboru Yamada所着的“Potential of Ge-Sb-Te Phase-Change Optical Disks for High-Data-RateRecording”,SPIE v.3109,pp.28-37(1997))。更一般的可将一种如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)的过渡金属与其混合物或合金与Ge/Sb/Te结合,以形成具有编程电阻特性的一种相变合金。在Ovshinsky‘112的第11~13栏中所提出的有用的存储材料的具体例子将合并作为参照用。
在一些实施例中,可掺杂杂质(impurities)到硫族化合物与其它相变材料中,以便使用掺杂的硫族化合物来改变导电率、转变温度、熔化温度及存储元件的其它特性。用来掺杂硫族化合物的代表的杂质包括氮、硅、氧、二氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛与氧化钛。请见例如美国专利专利号6800504与美国专利公开号2005/0029502。
在一第一结构态与一第二结构态之间能够开关相变合金,在单元的主动信道区中在其局部秩序(local order)中第一结构态是材料通常在其中是非晶固相、第二结构态是材料通常在其中是结晶固相。这些合金至少是双稳态。所谓的非晶表示一种比单晶更为无序、相对较少的有序结构(orderedstructure),其具有可检测特性如比结晶相高的电阻率(resistivity)。所谓的结晶是表示一种比非晶结构有序、相对较为有序的结构,其具有可检测特性如比非晶相低的电阻率。一般相变材料可由电力在穿过完全非晶态与完全结晶态之间的范围(spectrum)的局部秩序中的不同双稳态之间开关。其余受非晶相与结晶相之间的相影响的材料特征包括原子序度(atomic order)、自由电子密度与活化能。这样的材料不转换成不同固相就是转换成两个或多个固相的混合物(mixture),以提供在完全非晶态与完全结晶态之间的灰阶(gray scale)。因此在此种材料中的电特性是多变的。
相变合金可由电脉冲的运用而从一个相态转变到另一个。已知一种较短、较高的幅脉冲(amplitude pulse)有助于使相变材料转变成一般的非晶态。而一种较长、较低的幅脉冲有助于使相变材料转变成一般的结晶态。在较短、较高的幅脉冲中的能量是高到能打断结晶结构的键并且短得能避免原子再结合成结晶态。适合特定的相变合金的脉冲的适当数据曲线,不需过度实验就可具体决定。在下面的章节中,相变材料是以GST为例,且应知也可以使用其它种类的相变材料。在此描述对于完成一种PCRAM有用的材料是Ge2Sb2Te5。
在本发明的其它实施例中可使用其它可编程电阻存储材料,包括使用不同晶相来决定电阻的其它材料,或使用电脉冲来改变电阻值状态(resistance state)的其它存储材料。这些例子包括用于电阻式随机存取存储器(resistance random access memory,RRAM)的材料,如金属氧化物(metal-oxides)包含氧化钨(WOX)、NiO、Nb2O5、CuO2、Ta2O5、Al2O3、CoO、Fe2O3、HfO2、TiO2、SrTiO3、SrZrO3或(BaSr)TiO3。附加的例子包括用于像是旋转力矩转移(spin-torque-transfer,STT)磁电阻式随机存取存储器(magnetoresistance random access memory,MRAM)的MRAM的材料,例如CoFeB、Fe、Co、Ni、Gd、Dy、CoFe、NiFe、MnAs、MnBi、MnSb、CrO2、MnOFe2O3、FeOFe2O5、NiOFe2O3、MgOFe2、EuO和Y3Fe5O12至少其中的一种。请见例如题目为“Magnetic Memory device and Methodof Fabricating the Same”的美国专利公开号2007/0176251,其在此合并作为参照用。附加的例子还包括用于可编程金属单元(programmable-metallization-cell,PMC)存储器或者奈米离子存储器(nano-ionic memory)的固态电解质(solid electrolyte)材料,比如掺杂银的硫化锗电解质与掺杂铜的硫化锗电解质。请见例如N.E.Gilbert et al.所著的“A macro model of programmable metallization cell devices,”Solid-StateElectronics 49(2005)1813~1819,其在此合并作为参照用。
一种形成硫族化合物的示范的方法是在1mTorr~100mTorr的压力下利用PVD溅镀或者磁控溅镀法和Ar、N2、以及/或是He等的来源气体。这样的沉积通常是在室温进行。使用一种高宽比在1~5的准直管(collimator)来改善充填能力(fill-in performance)。也可以用数十伏特到数百伏特的DC偏压来改善充填能力。另一方面,可同时使用DC偏压与准直管的结合。于题目为“Chemical Vapor Deposition of Chalcogenide Materials”的美国专利公开号2006/0172067中揭露一种利用化学气相沉积(CVD)形成硫族化合物的示范的方法,其在此被合并作为参照用。于Lee,et al.所着的“HighlyScalable Phase Change Memory with CVD GeSbTe for Sub 50nmGeneration”,2007年在VLSI Technology Digest of Technical Papers的专题论文集(Symposium)上的pp.102-103揭露了利用CVD形成硫族化合物的其它示范的方法。
可选择性地施行一种在真空下或N2环境下的沉积后退火处理(post-deposition annealing treatment),以改善硫族化合物材料的结晶态。而上述退火温度通常在100℃到400℃的范围且退火时间低于30分钟。
图4~图17B显示一种制造在此描述的具有带多晶硅射极与自对准存储元件的双极接面晶体管的存储单元的阵列的制作顺序的步骤。
图4显示形成一基底的第一步骤,这个基底包括位在含第一与第二掺杂区205、210的存储区280内的一个阱202以及位在阱202内并延伸进入并穿出图4所示的剖面的介电沟渠230。第一与第二掺杂区205、210可使用已知的植入与活化退火工艺来形成。在说明的实施例中,第一掺杂区205包括掺杂N型材料的基底200、第二掺杂区210包括高掺杂N型(N+)材料的基底200。在一替代的实施例中,第一掺杂区205包括掺杂P型材料的基底200、第二掺杂区210包括高掺杂P型(P+)材料的基底200。
然后,由植入步骤在阱的第一掺杂区205内形成字符线130,结果得到图5A与图5B的剖面图所示的结构。同时在说明的实施例中,由一第二离子植入步骤在阱内形成一高掺杂区,从基底200顶面延伸至第二掺杂区210。字符线130具有第二导电态,并且在说明的实施例中,字符线130包括掺杂P型材料的基底200。在一替代的实施例中,字符线130包括掺杂N型材料的基底200。
接着,在存储区280与周边区285内的图5A与图5B所示的结构上形成栅极介电层293,结果得到图6所示的结构。在说明的实施例中,栅极介电层293包括二氧化硅。
之后,去除图6所示的结构的存储区280中的栅极介电层293,再形成一层700具有第一导电态的掺杂多晶硅材料,然后在掺杂多晶硅层700上形成一层710导电盖材料,结果得到图7A与图7B的剖面图所示的结构。导电盖材料层710包括一种例如含Ti、W、Co、Ni或Ta的硅化物。在一实施例中,该层710包括硅化钴(cobalt silicide,CoSi)并由沉积一层钴并进行一快速热工艺(RTP)形成,以使钴与层700中的硅反应而形成所述层710。应知其它硅化物也可用类似于此处描述的使用钴的例子的方式,由钛、砷、掺杂的镍或其合金的沉积的方式来形成。
然后,在图7A与图7B所示的结构的周边区285内形成逻辑装置286,结果得到图8A与图8B所示的结构。在说明的实施例中,逻辑装置286的形成包括,由图案化周边区285内的所述层700与710形成栅极结构287的掺杂多晶硅部分290与导电盖291,再施行一浅掺杂漏极(LDD)植入工艺,以于邻近栅极结构287的基底200中形成浅掺杂区之后在导电盖291与掺杂多晶硅部分290的侧壁上形成一绝缘层292,再施行一第二植入工艺,以形成作为逻辑装置286的源极与漏极的掺杂区288和289。当然也可使用其它技术来形成逻辑装置286。
接着,于图8A与图8B所示的结构上形成一层900介电材料,结果得到图9A与图9B所示的结构。在说明的实施例中,所述层900包括氮化硅。
然后,图案化图9A与图9B的存储区280内的所述层900、700和710,以于字符线130上形成多个多层叠层(multi-layer stacks)1000,结果得到图10A与图10B所示的结构。例如是由在多层叠层1000的位置上的所述层900上形成一掩膜(例如一层图案化光刻胶),再使用所述掩膜作为蚀刻掩膜来蚀穿所述层900、700和710,来形成多层叠层1000。
从图10A与图10B可知,多层叠层1000包括掺杂多晶硅柱220,其包括在对应字符线130上接近界面222之间定义出一pn接面的所述层700(请见图9A与图9B)的材料、在柱220上包括所述层700(请见图9A与图9B)的材料的一导电盖240、及在导电盖240上包括所述层900的材料的一牺牲元件(sacrificial element)1010。
在说明的实施例中,多层叠层1000具有一圆形剖面。在其它实施例中,可根据用于形成多层叠层1000的制造技术,使多层叠层1000具有方形、椭圆形、矩形或稍微不规则形的剖面。
接着,在多层叠层1000的侧壁上形成包括介电材料的侧壁间隔物260,再进行一植入工艺来形成位于相邻侧壁间隔物260之间的字符线130的较高掺杂区(more highly doped regions),然后在字符线130的较高掺杂区上形成包括自对准硅化物(salicide)的顶导体(top conductors)300,结果得到图11A与图11B所示的结构。在某些实施例中,可省略上述顶导体300。
侧壁间隔物260的形成可由于图10A与图10B所示的结构上沉积一层侧壁间隔物材料的共形层(conformal layer),再非等向地蚀刻所述共形层,以形成上述侧壁间隔物260。在形成顶导体300的硅化物工艺期间,侧壁间隔物260会保护叠层1000及叠层1000与字符线130间的界面。
在一实施例中,顶导体300包括硅化钴(CoSi)且顶导体300的形成是由沉积一层钴并进行一快速热工艺(RTP)以使钴与字符线130中的硅反应而形成所述顶导体。应知其它硅化物也可用类似于此处描述的使用钴的例子的方式,由钛、砷、掺杂的镍或其合金的沉积的方式来形成。
随后,于图11A~图11B所示的结构上形成一层介电层270,再进行如CMP的一平坦化工艺(planarization process)以暴露出多层叠层1000的牺牲元件1010的顶面,结果得到图12A与图12B所示的结构。
然后,形成穿过介电层270的导电接触窗215阵列,以接触所述阱的第二掺杂区210以及形成分别接触掺杂区288与289的导电插塞295、296,结果得到图13A与图13B所示的结构。
接着,去除图13A与图13B的牺牲元件1010,以形成由间隔物260定义出的介层窗1400,其往下延伸至导电盖240,结果得到图14A与图14B所示的结构。
之后,在图14A与图14B的介层窗1400内形成绝缘元件245,结果得到图15A与图15B所示的结构。绝缘元件245在介层窗1400内定义出自对准中心的开口(self-centered opening)1510,且在说明的实施例中,绝缘元件245包括氮化硅。
绝缘元件245的形成可藉由于图14A与图14B所示的结构上形成一层绝缘介电材料层,再非等向地蚀刻所述介电材料层,以露出一部分的导电盖240。
所述绝缘元件245的形成还可选择先在介电层270的顶面上形成一层在介层窗1400上具有开口的材料层。然后,在介层窗1400上进行一道选择性过切(undercutting)蚀刻,以便在蚀刻绝缘元件245的同时使介电层270的顶面上的材料层能完整地留下。然后,在介层窗1400中形成绝缘层材料,而由于选择性过切蚀刻工艺导致形成在介层窗1400中的绝缘层材料中有一自对准孔洞(void)。然后,在绝缘层材料上进行一非等向性蚀刻工艺,以打开所述孔洞,再继续蚀刻直到孔洞下的区域中的导电盖240的一部分顶面暴露出来,由此在介层窗1400中形成包括绝缘层材料的绝缘元件245。
接着,在由图15A~图15B所示的结构的绝缘元件245所定义的开口1510内形成存储元件125,结果得到图16A~图16B所示的结构。存储元件125的形成可由在图15A~图15B所示的结构上先沉积存储材料再接着一道如CMP的平坦化工艺。
然后,在图16A~图16B所示的结构上形成位线120、连到一参考电压(reference voltage)的导电材料140以及导线297,结果得到图17A~图17B所示的结构。在说明的实施例中,位线120导电材料140以及导线297包括第一与第二导电层,且藉由沉积所述第一与第二导电层再图案化的而形成的。
如上所述,掺杂多晶硅柱220与导电盖240是在定义后续形成的绝缘元件245与存储元件125的位置的牺牲元件1010形成期间形成的。然后,形成间隔物260,再选择性去除牺牲元件1010,以形成位于导电盖240上并由间隔物260所定义的介层窗1400。接着在介层窗1400内形成绝缘元件245,其具有置于由射极的侧面所定义的柱面内的中心的开口,之后于由绝缘元件245所定义的一开口1510内形成存储元件125。因此,存储元件位在掺杂多晶硅柱220与导电盖240的中心上并自对准于掺杂多晶硅柱220与导电盖240,而掺杂多晶硅柱220和导电盖240作为存储单元的双极接面晶体管的射极。
因为同时制作周边区内的逻辑装置和存储区内具有双极接面晶体管的存储单元在上述制造步骤中,所以储存装置具有降低的复杂性(complexity)以及满足上述讨论的设计整合的兼容性(compatibility)问题,以降低成本。如上所述,双极接面晶体管可提供比场效晶体管要大的电流驱动。此外,因为晶体管的射极包括掺杂多晶硅材料,所以能获得相当大的电流增益,从而降低引起存储元件中的相变化而在字符线130上所需的电流量。在字符线130上降低的电流量将会降低共享相同字符线的装置间的串音(cross-talk),进而改善阵列的功效。
图18~图21显示一种针对在图5A~图5B中显示的形成字符线130的替代实施例。
如图18的剖面图所示,进行蚀刻来去除图4的介电沟渠230的一部分的介电材料,以露出介电沟渠230间的阱的第一掺杂区205的侧壁面1800。
然后,在图18的阱的第一掺杂区205的露出的侧壁面1800上形成侧壁导体1900,结果得到图19的剖面图所示的结构。所述侧壁导体1900包括一种例如含Ti、W、Co、Ni或Ta的硅化物。侧壁导体1900的形成可由在露出的侧壁面1800上先沉积一硅化物前驱物(precursor)再进行退火,以使硅化物形成。然后去除基底上剩余的硅化物前驱物,留下侧壁面1800的侧面上的自对准硅化物侧壁导体。典型的硅化物前驱物包含金属或金属的化合物如钴、钛、镍、钼、钨、钽与铂。同时,所述硅化物前驱物还可包括金属氮化物或其它金属混合物。最终的硅化物侧壁导体1900会从字符线去除少数载子并增进字符线130的导电率。
接着,在图19所示的结构上形成介电材料以填入介电沟渠230,结果得到图20的剖面图所示的结构。
随后,进行离子植入以植入掺质(dopants)来形成字符线130,这种字符线130具有与阱的第一和第二掺杂区205和210的导电态相反的一导电态,且结果得到图21的剖面图所示的结构。
图22是一种集成电路2210的简化的方块图,前述集成电路2210包括在此描述的一种借着使用具有带多晶硅射极与自对准存储元件的双极接面晶体管的存储单元实现的一存储单元阵列100。具有读取、设定与重置模式(read,set,and reset modes)的一字符线译码器2214连至并在电性上相连于多个在存储阵列100中沿着列(rows)排列的多个字符线2216。一位(行)译码器2218在电性上相连于在存储阵列100中沿着行(columns)排列的多个位22220,用以读取、设定与重置阵列100中的相变存储单元(未绘示)。在总线(bus)2222上供应地址(addresses)到字符线译码器与驱动器2214和位线译码器2218。在方块2224中包含用于读取、设定与重置模式的电压源及/或电流源(current source)的感测放大器(sense amplifiers)与Data-In结构经由数据总线2226连到位线译码器2218。从集成电路2210上的输出/输入(input/output)接口(ports)经由一data-in导线2228提供数据到方块2224中的Data-In结构,或是从其它集成电路2210的内部或外部的数据来源将数据供应到方块2224中的Data-In结构。其它电路(Other circuitry)2230则可包括在集成电路2210中,如通用处理器(general purpose processor)或特殊目的应用电路,或是一种提供由阵列100支持的***单芯片(system-on-a-chip)功能的模块组合(combination)。从方块2224中的感测放大器经由一data-out导线2232将数据提供到集成电路2210上的输出/输入接口,或是将数据提供到集成电路2210的内部或外部的其它数据终点(datadestinations)。
在这里的例子中提供的控制器(controller)2234使用一偏压配置状态机器(bias arrangement state machine)来控制偏压配置供应电压与电流电源2236的运用,如读取、编程、擦除、擦除验证(erase verify)与编程验证电压以及/或是电流。可使用已知技术中的特殊用途(special-purpose)逻辑电路来完成控制器2234。在替代的实施例中,控制器2234包括一通用处理器,其可在相同的集成电路上实现,以执行一计算机程序来控制所述装置的操作。在另一实施例中,也可利用特殊用途(special-purpose)逻辑电路与通用处理器的组合来完成控制器2234。
虽然本发明已以实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视权利要求范围所界定的为准。
Claims (27)
1.一种包括多个存储单元的储存装置,在该多个存储单元中的一个存储单元包括:
一双极接面晶体管,包括一射极,该射极包括一掺杂多晶硅柱,该掺杂多晶硅柱接触对应的字符线,该掺杂多晶硅柱比该掺杂多晶硅柱下面的字符线部分的掺杂要更高,该掺杂多晶硅柱与字符线在接近界面处定义出一个pn接面;
一绝缘元件,位在该射极上并具有延伸穿过该绝缘元件的一开口,该开口位在该射极上的中心;以及
一存储元件,位在该开口内并与该射极电性相连。
2.如权利要求1所述的包括多个存储单元的储存装置,其中:
当该多个存储单元的该掺杂多晶硅柱投影于该射极上,在该射极上定义出一柱面的侧边;以及
该开口位在该柱面内的中心。
3.如权利要求1所述的包括多个存储单元的储存装置,其中该多个存储单元的该多个存储元件具有一表面积的底面,该表面积小于对应的该射极的顶面的表面积。
4.如权利要求1所述的包括多个存储单元的储存装置,其中该多个存储单元的该射极还包括一导电盖,位在该掺杂多晶硅柱上,该导电盖包括一硅化物。
5.如权利要求1所述的包括多个存储单元的储存装置,其中该多个存储单元的该绝缘元件具有一外表面垂直对准于对应的该射极的一外表面。
6.如权利要求5所述的包括多个存储单元的储存装置,其中在该多个存储单元中的存储单元还包括一侧壁间隔物环绕该绝缘元件与该射极。
7.如权利要求1所述的包括多个存储单元的储存装置,还包括一单晶基底以及位在该单晶基底中的多个字符线,该多个存储单元的该射极接触该多个字符线中的一对应字符线,其中该多个存储单元的该双极接面晶体管还包括:
位于该射极下的一部分的该对应字符线,以作为一基极;以及
一集极,包括位于该基极下的一部分的该单晶基底。
8.如权利要求7所述的包括多个存储单元的储存装置,其中该多个字符线还包括位在相连的该多个存储单元的该射极之间的区域的顶表面上的多个顶导体,该多个顶导体包括硅化物。
9.如权利要求7所述的包括多个存储单元的储存装置,还包括位在该多个字符线的侧壁表面上的多个侧壁导体,该多个侧壁导体包括硅化物。
10.如权利要求7所述的包括多个存储单元的储存装置,其中:
该单晶基底包括n型掺杂半导体材料;
该多个字符线包括p型掺杂半导体材料;以及
该多个存储单元的该射极包括n型掺杂多晶硅。
11.如权利要求7所述的包括多个存储单元的储存装置,其中:
该单晶基底包括p型掺杂半导体材料;
该多个字符线包括n型掺杂半导体材料;以及
该多个存储单元的该射极包括p型掺杂多晶硅。
12.如权利要求7所述的包括多个存储单元的储存装置,还包括多个位线,其中该多个存储单元的该多个存储元件电性相连至该射极与该多个位线中的一对应位线之间。
13.如权利要求12所述的包括多个存储单元的储存装置,还包括多个导电接触窗,接触该单晶基底并连到一参考电压。
14.一种制造储存装置的方法,包括形成多个存储单元,在形成该多个存储单元的方法中,至少有一个方法包括:
形成一双极接面晶体管,该双极接面晶体管包括一射极,该射极包括一掺杂多晶硅柱,该掺杂多晶硅柱接触对应的字符线,该掺杂多晶硅柱比该掺杂多晶硅柱下面的字符线部分的掺杂要更高,该掺杂多晶硅柱与字符线在接近界面处定义出一个pn接面;
在该射极上形成一绝缘元件,该绝缘元件具有延伸穿过该绝缘元件的一开口,该开口位在该射极上的中心;以及
在该开口内形成一存储元件,且该存储元件与该射极电性相连。
15.如权利要求14所述的制造储存装置的方法,其中:
当该多个存储单元的该掺杂多晶硅柱投影于该射极上,在该射极上定义出一柱面的侧边;以及
该开口位在该柱面内的中心。
16.如权利要求14所述的制造储存装置的方法,其中该多个存储单元的所述射极还包括一导电盖,位在该掺杂多晶硅柱上,该导电盖包括一硅化物。
17.如权利要求14所述的制造储存装置的方法,其中该多个存储单元的该绝缘元件具有一外表面垂直对准于对应的该射极的一外表面。
18.如权利要求17所述的制造储存装置的方法,其中形成该多个存储单元还包括形成一侧壁间隔物环绕该绝缘元件与该射极。
19.如权利要求14所述的制造储存装置的方法,还包括:
形成一单晶基底;
在该单晶基底中形成多个字符线,该多个存储单元的该射极接触该多个字符线中的一对应字符线,其中该多个存储单元的该双极接面晶体管还包括位于该射极下的部分该对应字符线作为一基极,以及包括位于该基极下的一部分的该单晶基底的一集极;以及
形成多个位线,其中该多个存储单元的该多个存储元件电性相连于该射极与所述位线中的一对应位线之间。
20.如权利要求19所述的制造储存装置的方法,其中形成该多个字符线,还包括在相连的该多个存储单元的该射极之间的区域的顶表面上形成多个顶导体,该多个顶导体包括硅化物。
21.如权利要求14所述的制造储存装置的方法,还包括形成多个导电接触窗,接触该单晶基底并连到一参考电压。
22.一种制造储存装置的方法,该方法包括:
形成具有一第一导电态的一单晶基底;
在该单晶基底中形成多个介电沟渠;
在该单晶基底中形成多个字符线,在该多个字符线中相邻的字符线由该多个介电沟渠中的一介电沟渠隔开;
在该单晶基底上形成一结构,该结构包括掺杂多晶硅材料、在该掺杂多晶硅材料上的导电盖材料以及在该导电盖材料上的牺牲材料;其中,该掺杂多晶硅材料接触对应的字符线,该掺杂多晶硅材料比该掺杂多晶硅材料下面的字符线部分的掺杂要更高,该掺杂多晶硅材料与字符线在接近界面处定义出一个pn接面;
图案化该结构,以在所述字符线上形成多个叠层;
在该多个叠层的侧壁上形成多个侧壁间隔物;
去除该牺牲材料,以定义出多个介层窗;
在该多个介层窗内形成一绝缘层,该绝缘层定义出多个开口;
在该多个开口中形成多个存储元件;以及
在该多个存储元件上形成多个位线。
23.如权利要求22所述的制造储存装置的方法,在形成该多个侧壁间隔物的步骤后,还包括施行一植入工艺,以于相邻的该多个叠层之间的该多个字符线内形成多个更高掺杂区域。
24.如权利要求22所述的制造储存装置的方法,还包括在该多个字符线的该多个更高掺杂区域的顶表面上形成多个顶导体,该多个顶导体包括硅化物。
25.如权利要求22所述的制造储存装置的方法,其中该储存装置包括一存储区与一周边区、在该存储区内的该多个字符线以及还包括:
在形成该多个字符线的步骤后与在该单晶基底上形成该结构的步骤前,在该存储区与该周边区内沉积栅极介电材料;
去除该存储区内的该栅极介电材料;以及
在该周边区内形成一逻辑装置,并电性连接到该多个位线中的位线及该多个字符线中的字符线,该逻辑装置包括在该单晶基底上的一栅极结构与在该单晶基底中的第一和第二掺杂区,该栅极结构包括在该栅极介电材料上的一掺杂多晶硅部分以及在该掺杂多晶硅部分上的一导电盖部分,该掺杂多晶硅部分包括该掺杂多晶硅材料,而该导电盖部分包括该导电盖材料。
26.如权利要求25所述的制造储存装置的方法,其中形成该逻辑装置包括:
图案化在该周边区内的该掺杂多晶硅材料与该导电盖材料;
施行一浅掺杂漏极植入工艺,以于该单晶基底中形成多个浅掺杂区;
在该掺杂多晶硅部分与该导电盖部分的一侧壁上形成一侧壁间隔物;以及
施行一第二植入工艺,以于该单晶基底中形成该第一和第二掺杂区。
27.如权利要求22所述的方法,其中形成该单晶基底与形成该多个字符线包括:
形成该单晶基底;
在该单晶基底中形成该多个介电沟渠;
从该多个介电沟渠中去除一部分的材料,以暴露出该单晶基底的侧面;
在该单晶基底的暴露出的侧面上形成多个侧壁导体,该多个侧壁导体包括硅化物;
在该多个介电沟渠中填入介电材料;以及
在该多个介电沟渠之间的该单晶基底中植入掺质,以形成该多个字符线。
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KR101019986B1 (ko) * | 2008-10-10 | 2011-03-09 | 주식회사 하이닉스반도체 | 성장 방식에 의해 형성되는 콘택 구조를 절연시키는 절연막을 포함하는 상변화 메모리 소자, 이를 포함하는 반도체 소자, 및 그들의 제조방법 |
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2009
- 2009-01-22 US US12/357,912 patent/US8933536B2/en active Active
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US20100181649A1 (en) | 2010-07-22 |
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TWI404244B (zh) | 2013-08-01 |
CN101840928A (zh) | 2010-09-22 |
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