CN101834606A - Front-end sampling hold and margin amplification circuit of analog-to-digital converter - Google Patents
Front-end sampling hold and margin amplification circuit of analog-to-digital converter Download PDFInfo
- Publication number
- CN101834606A CN101834606A CN200910047261A CN200910047261A CN101834606A CN 101834606 A CN101834606 A CN 101834606A CN 200910047261 A CN200910047261 A CN 200910047261A CN 200910047261 A CN200910047261 A CN 200910047261A CN 101834606 A CN101834606 A CN 101834606A
- Authority
- CN
- China
- Prior art keywords
- meets
- amplifier
- sampling
- capacitor
- sole plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
- Amplifiers (AREA)
Abstract
The invention relates to the technical field of streamline operating analog-to-digital converters, and discloses a front-end sampling hold and margin amplification circuit of an analog-to-digital converter. The circuit comprises an operational amplifier, a first switching capacitor unit, a second switching capacitor unit and two sampling switches, wherein the first switching capacitor unit and the second switching capacitor unit are alternately combined with the operational amplifier and the two sampling switches to form the sampling hold or margin amplification circuit. In a sampling phase, the first switching capacitor unit or the second switching capacitor unit and the two sampling switches sample the current signals, and meanwhile the second switching capacitor unit or the first switching capacitor unit and the operational amplifier amplify the margin (the part of signal removal quantization) of the last sampled signals; and in a holding phase, the first switching capacitor unit or the second switching capacitor unit and the operational amplifier hold the current signals. The circuit can realize the functions of a front-end sampling hold circuit and a fist-stage MDAC circuit of the streamline analog-to-digital converter with lower power consumption at the same time, and improve the precision of the streamline analog-to-digital converter.
Description
Technical field
The present invention relates to pile line operation analog to digital converter technical field, relate in particular to the circuit that a kind of pile line operation analog to digital converter front-end sampling keeps and surplus is amplified.
Background technology
Analog to digital converter is the important component part in the mixed-signal system, and multiple structure type is arranged, and wherein pipeline organization helps analog to digital converter and compromises between power consumption, area, speed and precision, thereby is subjected to extensive use.
Traditional pile line operation analog to digital converter front end needs an accurate sampling hold circuit [], this sampling hold circuit has been introduced noise and various error inevitably, but its required precision is the highest in each streamline sub level, so it has consumed the most power consumption of production line analog-digital converter.
The sampling hold circuit of eliminating the production line analog-digital converter front end has reduced the power consumption of circuit greatly, but the time constant of input signal arrival first order MDAC and first order sub-adc converter is inconsistent, makes the precision of analog to digital converter reduce greatly.Traditional sampling hold circuit technology for eliminating is consistent the time constant of this two signal path by the size of design capacitance and switch accurately, but factors such as process variations and clock jitter have still limited the raising of precision.Second kind of solution is after the sampling of sampling phase sampler electric capacity, keep institute's number of accepting and believing and do thick the quantification by sub-adc converter, carry out surplus mutually again at next then and amplify [], but this scheme needs that original sampling is divided into sampling mutually to be quantized mutually with thick mutually, thereby has limited the further raising of sample rate.Thereby another method is by sharing the power consumption [] that amplifier reduces circuit between front-end sampling holding circuit and first order MDAC, but because sampling hold circuit and first order MDAC are respectively with a cover sampling capacitance, when the sampling capacitance of first order MDAC is sampled, still can introduce various errors, be unfavorable for the raising of precision.
Summary of the invention
Main purpose of the present invention is to solve the problem that prior art exists, and the circuit that a kind of pile line operation analog to digital converter front-end sampling keeps and surplus is amplified is provided, and this circuit can reduce the power consumption of circuit, improves the precision of analog to digital converter.
For achieving the above object, the invention provides the circuit that a kind of pile line operation analog to digital converter front-end sampling keeps and surplus is amplified, this circuit comprises amplifier (1), the first switching capacity unit (2), second switch capacitor cell (3) and two sampling switchs (4); Wherein, the first switching capacity unit (2), second switch capacitor cell (3) are alternately formed sampling maintenance or surplus amplifying circuit with amplifier (1) and two sampling switchs (4); In the sampling phase, the first switching capacity unit (2) or second switch capacitor cell (3) and the current signal of two sampling switchs (4) sampling, the sample that the while second switch capacitor cell (3) or the first switching capacity unit (2) and amplifier (1) sampled the last time carry out surplus and amplify; Keeping phase, the first switching capacity unit (2) or second switch capacitor cell (3) and amplifier (1) keep current sample.
In the such scheme, this circuit adopts the first switching capacity unit or second switch capacitor cell and two sampling switchs to sample, and makes two cover switching capacity unit sample constantly at the same edge of each clock cycle.
In the such scheme, this circuit is worked under the control of four mutual do not overlap clock ph1, ph2, ph3 and ph4, wherein,
In the ph1 phase, sample in the first switching capacity unit, simultaneously the second switch capacitor cell to the ph3 phase sampler to voltage carry out surplus and amplify, at this moment, the sole plate of capacitor C sp1 and Cfp1 meets the anode Vinp of difference input voltage, the sole plate of capacitor C sn1 and Cfn1 meets the negative terminal Vinn of difference input voltage, the top crown of these four electric capacity meets the common mode input Vicom of amplifier respectively through two sampling switchs, in addition, the top crown of capacitor C sp2 and Csn2 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output Vdacp and the Vdacn of subnumber weighted-voltage D/A converter at the corresponding levels respectively, the top crown of capacitor C fp2 and Cfn2 meets the differential input end opinp and the opinn of amplifier respectively, and the sole plate meets the difference output end outn and the outp of amplifier respectively;
In the ph2 phase, the first switching capacity unit to the ph1 phase sampler to voltage keep, second switch capacitor cell discharge zero clearing, at this moment, the top crown of capacitor C fp1 and Cfn1 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output end outn and the outp of amplifier respectively, the top crown of capacitor C sp1 and Csn1 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate is unsettled, in addition, capacitor C sp2, Csn2, the top crown of Cfp2 and Cfn2 all meets the common mode input Vicom of amplifier, and the sole plate all meets the output common mode voltage Vocom of amplifier;
In the ph3 phase, the second switch capacitor cell is sampled, simultaneously the first switching capacity unit to the ph1 phase sampler to voltage carry out surplus and amplify, at this moment, the sole plate of capacitor C sp2 and Cfp2 meets the anode Vinp of difference input voltage, the sole plate of capacitor C sn2 and Cfn2 meets the negative terminal Vinn of difference input voltage, the top crown of these four electric capacity meets the common mode input Vicom of amplifier respectively through two sampling switchs, in addition, the top crown of capacitor C sp1 and Csn1 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output Vdacp and the Vdacn of subnumber weighted-voltage D/A converter at the corresponding levels respectively, the top crown of capacitor C fp1 and Cfn1 meets the differential input end opinp and the opinn of amplifier respectively, and the sole plate meets the difference output end outn and the outp of amplifier respectively;
In the ph4 phase, the second switch capacitor cell to the ph3 phase sampler to voltage keep, the first switching capacity cell discharge zero clearing, at this moment, the top crown of capacitor C fp2 and Cfn2 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output end outn and the outp of amplifier respectively, the top crown of capacitor C sp2 and Csn2 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate is unsettled, in addition, capacitor C sp1, Csn1, the top crown of Cfp1 and Cfn1 all meets the common mode input Vicom of amplifier, and the sole plate all meets the output common mode voltage Vocom of amplifier.
In the such scheme, described amplifier does not reset in sampling phase and maintenance continuous operation mutually.
The present invention has following beneficial effect compared with the prior art:
1, utilizes the present invention, adopt two cover switching capacity unit and an amplifier to form the circuit that pile line operation analog to digital converter front-end sampling keeps and surplus is amplified, realized the function of front-end sampling holding circuit and first order MDAC simultaneously, improve the utilance of amplifier by the continuous operation of amplifier, greatly reduced the power consumption of circuit.
2, utilize the present invention, for a signal, sampling keeps and same set of sampling capacitance is all used in the surplus amplification, adopts another set of sampling capacitance sampling and introduce new error during keeping with regard to having avoided like this, has improved the precision of analog to digital converter.
3, utilize the present invention, two cover switching capacity units in series a pair of common sampling switch, eliminated the influence of sampling clock deviation, improved the precision of analog to digital converter.
4, utilize the present invention, sampling capacitance zero clearing that resets before sampling, can eliminate memory error, promptly eliminate of the influence of last sample to this sampling, further improve the linearity of analog to digital converter, and the requirement of the preceding stage drive circuit of reduction, help A/D converter with high speed and high precision and related system design for scheme and realize.
Description of drawings
Fig. 1 is the structural representation of the circuit of pile line operation analog to digital converter front-end sampling maintenance provided by the invention and surplus amplification.
Fig. 2 is each clock signal sequential relationship schematic diagram in Fig. 1 circuit.
Fig. 3 is the structural representation of Fig. 1 circuit when ph1 works mutually.
Fig. 4 is the structural representation of Fig. 1 circuit when ph2 works mutually.
Fig. 5 is the structural representation of Fig. 1 circuit when ph3 works mutually.
Fig. 6 is the structural representation of Fig. 1 circuit when ph4 works mutually.
For the ease of understanding, describe in detail of the present invention below with reference to concrete drawings and Examples.It needs to be noted, instantiation and accompanying drawing only are in order to illustrate, obviously those of ordinary skill in the art can illustrate according to this paper, within the scope of the invention the present invention is made various corrections and change, and these corrections and change are also included in the scope of the present invention.
Embodiment
As shown in Figure 1, Fig. 1 is the structural representation of the circuit of pile line operation analog to digital converter front-end sampling maintenance provided by the invention and surplus amplification, and this circuit comprises amplifier, the first switching capacity unit, second switch capacitor cell and two sampling switchs.Wherein, the first switching capacity unit, second switch capacitor cell are alternately formed sampling maintenance and surplus amplifying circuit with amplifier and two sampling switchs.In the sampling phase, the first switching capacity unit or second switch capacitor cell and two current samples of sampling switch sampling, the sample that the while second switch capacitor cell or the first switching capacity unit and amplifier sampled the last time carries out surplus and amplifies; Keeping phase, the first switching capacity unit or second switch capacitor cell and amplifier keep current sample.
Fig. 1 circuit is worked under the control of each clock signal shown in Figure 2.As depicted in figs. 1 and 2, the rising edge of clock signal sample is identical with the rising edge of ph1 or ph2 or ph3 or ph4, trailing edge shifts to an earlier date slightly than the trailing edge of ph1 or ph2 or ph3 or ph4, it is connected on two sampling switchs on the first switching capacity unit and the second switch capacitor cell by control, make two cover switching capacity unit sample constantly at the same edge of each clock cycle, eliminate the influence of sampling clock deviation, improved the precision of analog to digital converter.As shown in Figure 2, ph1, ph2, ph3 and ph4 are four clock signals that do not overlap mutually, and under the control of this four phase clocks signal, first switching capacity unit in Fig. 1 circuit and second switch capacitor cell hocket, and sampling keeps and surplus is amplified.Because the switch that has is closed continuously mutually with ph3 mutually at ph2, the switch that has is closed continuously mutually with ph1 in the ph4 phase, therefore adopts respectively to comprise ph2 phase and ph3 clock signal ph2﹠amp mutually; 3 with comprise ph4 mutually with ph1 clock signal ph4﹠amp mutually; 1 is controlled.
Fig. 1 circuit in the operating state of ph1 phase as shown in Figure 3, sample in the first switching capacity unit, the second switch capacitor cell carries out the surplus amplification simultaneously, at this moment, the sole plate of capacitor C sp1 and Cfp1 meets the anode Vinp of difference input voltage, the sole plate of capacitor C sn1 and Cfn1 meets the negative terminal Vinn of difference input voltage, the top crown of these four electric capacity meets the common mode input Vicom of amplifier respectively through two sampling switchs, in addition, the top crown of capacitor C sp2 and Csn2 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output Vdacp and the Vdacn of subnumber weighted-voltage D/A converter at the corresponding levels respectively, the top crown of capacitor C fp2 and Cfn2 meets the differential input end opinp and the opinn of amplifier respectively, and the sole plate meets the difference output end outn and the outp of amplifier respectively.
Fig. 1 circuit in the operating state of ph2 phase as shown in Figure 4, the first switching capacity unit to the ph1 phase sampler to voltage keep, second switch capacitor cell discharge zero clearing, at this moment, the top crown of capacitor C fp1 and Cfn1 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output end outn and the outp of amplifier respectively, the top crown of capacitor C sp1 and Csn1 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate is unsettled, in addition, capacitor C sp2, Csn2, the top crown of Cfp2 and Cfn2 all meets the common mode input Vicom of amplifier, and the sole plate all meets the output common mode voltage Vocom of amplifier.
Fig. 1 circuit in the operating state of ph3 phase as shown in Figure 5, the second switch capacitor cell is sampled, the first switching capacity unit carries out the surplus amplification simultaneously, at this moment, the sole plate of capacitor C sp2 and Cfp2 meets the anode Vinp of difference input voltage, the sole plate of capacitor C sn2 and Cfn2 meets the negative terminal Vinn of difference input voltage, the top crown of these four electric capacity meets the common mode input Vicom of amplifier respectively through two sampling switchs, in addition, the top crown of capacitor C sp1 and Csn1 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output Vdacp and the Vdacn of subnumber weighted-voltage D/A converter at the corresponding levels respectively, the top crown of capacitor C fp1 and Cfn1 meets the differential input end opinp and the opinn of amplifier respectively, and the sole plate meets the difference output end outn and the outp of amplifier respectively.
Fig. 1 circuit in the operating state of ph4 phase as shown in Figure 6, the second switch capacitor cell to the ph3 phase sampler to voltage keep, the first switching capacity cell discharge zero clearing, at this moment, the top crown of capacitor C fp2 and Cfn2 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate meets the difference output end outn and the outp of amplifier respectively, the top crown of capacitor C sp2 and Csn2 meets the differential input end opinp and the opinn of amplifier respectively, the sole plate is unsettled, in addition, capacitor C sp1, Csn1, the top crown of Cfp1 and Cfn1 all meets the common mode input Vicom of amplifier, and the sole plate all meets the output common mode voltage Vocom of amplifier.
As Fig. 3, Fig. 4, Fig. 5 and shown in Figure 6, amplifier has improved utilance in ph1 phase, ph2 phase, ph3 phase and ph4 continuous operation mutually, greatly reduces the power consumption of circuit.For the voltage that the first switching capacity unit arrives at the ph1 phase sampler, it keeps relatively at ph2, and it carries out the surplus amplification relatively at ph3, and sampling maintenance and surplus are amplified and all carried out on capacitor C sp1, Csn1, Cfp1 and Cfn1; For the voltage that the second switch capacitor cell arrives at the ph3 phase sampler, it keeps relatively at ph4, and it carries out the surplus amplification relatively at ph1, and sampling maintenance and surplus are amplified and all carried out on capacitor C sp2, Csn2, Cfp2 and Cfn2.Therefore, for each sample, sampling keeps and surplus is amplified all to overlap on the electric capacity one and carried out, and during keeping the total amount of electric charge conservation on this cover electric capacity, can not introduce new error, thereby improve the precision of analog to digital converter.
As Fig. 3 and shown in Figure 5, this circuit adopts 1.5/grade structure during surplus is amplified, and with respect to the structure of multidigit/level, improved the degrees of tolerance of comparator to the voltage imbalance, but this circuit can be generalized to the structure of multidigit/level equally.
Claims (4)
1. an analog to digital converter front-end sampling keeps and the circuit of surplus amplification, it is characterized in that this circuit comprises amplifier (1), the first switching capacity unit (2), second switch capacitor cell (3) and two sampling switchs (4); Wherein, the first switching capacity unit (2), second switch capacitor cell (3) are alternately formed sampling maintenance or surplus amplifying circuit with amplifier (1) and two sampling switchs (4); In the sampling phase, the first switching capacity unit (2) or second switch capacitor cell (3) and the current signal of two sampling switchs (4) sampling, the sample that the while second switch capacitor cell (3) or the first switching capacity unit (2) and amplifier (1) sampled the last time carry out surplus and amplify; Keeping phase, the first switching capacity unit (2) or second switch capacitor cell (3) and amplifier (1) keep current sample.
2. the circuit that analog to digital converter front-end sampling according to claim 1 keeps and surplus is amplified, it is characterized in that, this circuit adopts the first switching capacity unit (2) or second switch capacitor cell (3) and two sampling switchs (4) to sample, and makes two cover switching capacity unit sample constantly at the same edge of each clock cycle.
3. the circuit that analog to digital converter front-end sampling according to claim 1 keeps and surplus is amplified is characterized in that, this circuit is worked under the control of four mutual do not overlap clock ph1, ph2, ph3 and ph4, wherein,
In the ph1 phase, sample in the first switching capacity unit (2), simultaneously second switch capacitor cell (3) to the ph3 phase sampler to voltage carry out surplus and amplify, at this moment, the sole plate of capacitor C sp1 and Cfp1 meets the anode Vinp of difference input voltage, the sole plate of capacitor C sn1 and Cfn1 meets the negative terminal Vinn of difference input voltage, and the top crown of these four electric capacity meets the common mode input Vicom of amplifier (1) respectively through two sampling switchs (4); The top crown of capacitor C sp2 and Csn2 meets the differential input end opinp and the opinn of amplifier (1) respectively, the sole plate meets the difference output Vdacp and the Vdacn of subnumber weighted-voltage D/A converter at the corresponding levels respectively, the top crown of capacitor C fp2 and Cfn2 meets the differential input end opinp and the opinn of amplifier (1) respectively, and the sole plate meets the difference output end outn and the outp of amplifier (1) respectively;
In the ph2 phase, the first switching capacity unit (2) to the ph1 phase sampler to voltage keep, second switch capacitor cell (3) discharge zero clearing, at this moment, the top crown of capacitor C fp1 and Cfn1 meets the differential input end opinp and the opinn of amplifier (1) respectively, the sole plate meets the difference output end outn and the outp of amplifier (1) respectively, and the top crown of capacitor C sp1 and Csn1 meets the differential input end opinp and the opinn of amplifier (1) respectively, and the sole plate is unsettled; The top crown of capacitor C sp2, Csn2, Cfp2 and Cfn2 all meets the common mode input Vicom of amplifier (1), and the sole plate all meets the output common mode voltage Vocom of amplifier (1);
In the ph3 phase, second switch capacitor cell (3) is sampled, simultaneously the first switching capacity unit (2) to the ph1 phase sampler to voltage carry out surplus and amplify, at this moment, the sole plate of capacitor C sp2 and Cfp2 meets the anode Vinp of difference input voltage, the sole plate of capacitor C sn2 and Cfn2 meets the negative terminal Vinn of difference input voltage, and the top crown of these four electric capacity meets the common mode input Vicom of amplifier (1) respectively through two sampling switchs (4); The top crown of capacitor C sp1 and Csn1 meets the differential input end opinp and the opinn of amplifier (1) respectively, the sole plate meets the difference output Vdacp and the Vdacn of subnumber weighted-voltage D/A converter at the corresponding levels respectively, the top crown of capacitor C fp1 and Cfn1 meets the differential input end opinp and the opinn of amplifier (1) respectively, and the sole plate meets the difference output end outn and the outp of amplifier (1) respectively;
In the ph4 phase, second switch capacitor cell (3) to the ph3 phase sampler to voltage keep, the discharge zero clearing of the first switching capacity unit (2), at this moment, the top crown of capacitor C fp2 and Cfn2 meets the differential input end opinp and the opinn of amplifier (1) respectively, the sole plate meets the difference output end outn and the outp of amplifier (1) respectively, and the top crown of capacitor C sp2 and Csn2 meets the differential input end opinp and the opinn of amplifier (1) respectively, and the sole plate is unsettled; The top crown of capacitor C sp1, Csn1, Cfp1 and Cfn1 all meets the common mode input Vicom of amplifier (1), and the sole plate all meets the output common mode voltage Vocom of amplifier (1).
4. the circuit that analog to digital converter front-end sampling according to claim 1 keeps and surplus is amplified is characterized in that, described amplifier (1) does not reset in sampling phase and maintenance continuous operation mutually.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100472618A CN101834606B (en) | 2009-03-09 | 2009-03-09 | Front-end sampling hold and margin amplification circuit of analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100472618A CN101834606B (en) | 2009-03-09 | 2009-03-09 | Front-end sampling hold and margin amplification circuit of analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101834606A true CN101834606A (en) | 2010-09-15 |
| CN101834606B CN101834606B (en) | 2012-11-14 |
Family
ID=42718561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100472618A Expired - Fee Related CN101834606B (en) | 2009-03-09 | 2009-03-09 | Front-end sampling hold and margin amplification circuit of analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101834606B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101977059A (en) * | 2010-11-23 | 2011-02-16 | 复旦大学 | Sample-and-hold circuit at front end of superhigh speed flash analog-digital converter |
| CN102904571A (en) * | 2011-07-29 | 2013-01-30 | 比亚迪股份有限公司 | Allowance gain circuit |
| CN103199863A (en) * | 2013-04-24 | 2013-07-10 | 中国电子科技集团公司第二十四研究所 | Charge supplementing circuit for shortening reference settling time in A/D (analog-digital) converter of assembly line |
| CN105763198A (en) * | 2016-02-24 | 2016-07-13 | 芯海科技（深圳）股份有限公司 | Integrator gain multiplying circuit in modulator |
| CN106230438A (en) * | 2016-08-04 | 2016-12-14 | 成都博思微科技有限公司 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
| CN112003577A (en) * | 2020-08-28 | 2020-11-27 | 无锡英迪芯微电子科技股份有限公司 | High-precision switch capacitance type differential measurement circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100586024C (en) * | 2007-04-05 | 2010-01-27 | 中国科学院微电子研究所 | Double-sampling multiplication digital-analog conversion circuit and application thereof |
| CN100546194C (en) * | 2007-05-16 | 2009-09-30 | 中国科学院微电子研究所 | Operational amplifier shared circuit and pipeline analog-to-digital converter applying same |
| US7683677B2 (en) * | 2007-08-06 | 2010-03-23 | Mediatek Inc. | Sample-and-hold amplification circuits |
-
2009
- 2009-03-09 CN CN2009100472618A patent/CN101834606B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101977059A (en) * | 2010-11-23 | 2011-02-16 | 复旦大学 | Sample-and-hold circuit at front end of superhigh speed flash analog-digital converter |
| CN102904571A (en) * | 2011-07-29 | 2013-01-30 | 比亚迪股份有限公司 | Allowance gain circuit |
| CN103199863A (en) * | 2013-04-24 | 2013-07-10 | 中国电子科技集团公司第二十四研究所 | Charge supplementing circuit for shortening reference settling time in A/D (analog-digital) converter of assembly line |
| CN103199863B (en) * | 2013-04-24 | 2016-01-20 | 中国电子科技集团公司第二十四研究所 | The electric charge supplementary circuitry with reference to settling time is shortened in pipeline a/d converter |
| CN105763198A (en) * | 2016-02-24 | 2016-07-13 | 芯海科技（深圳）股份有限公司 | Integrator gain multiplying circuit in modulator |
| CN106230438A (en) * | 2016-08-04 | 2016-12-14 | 成都博思微科技有限公司 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
| CN112003577A (en) * | 2020-08-28 | 2020-11-27 | 无锡英迪芯微电子科技股份有限公司 | High-precision switch capacitance type differential measurement circuit |
| CN112003577B (en) * | 2020-08-28 | 2022-03-18 | 无锡英迪芯微电子科技股份有限公司 | High-precision switch capacitance type differential measurement circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101834606B (en) | 2012-11-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102420612B (en) | Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching | |
| CN101834606B (en) | Front-end sampling hold and margin amplification circuit of analog-to-digital converter | |
| CN102255615B (en) | Microsoft data access component (MDAC) structure applied to pipeline analogue-to-digital converter | |
| CN101814920B (en) | Analog-digital converter with sample hold and MDAC (Multiplying Digital-to-Analog Conversion) sharing capacitance and operational amplifier in time sharing way | |
| CN101295983B (en) | Double-sampling fully-differential sampling hold circuit | |
| CN104485957B (en) | Production line analog-digital converter | |
| CN100546194C (en) | Operational amplifier shared circuit and pipeline analog-to-digital converter applying same | |
| US7429946B2 (en) | Capacitor averaging converter | |
| CN104168025B (en) | A kind of charge type streamline gradual approaching A/D converter | |
| CN101854174A (en) | Streamline analog-digital converter and sub conversion stage circuit thereof | |
| CN107070450A (en) | Multichannel DAC phase errors calibration circuit based on charge-domain signal transacting | |
| CN104124969A (en) | Pipelined analog-to-digital converter | |
| CN100574112C (en) | Pipeline organization analog to digital converter capable of inhibiting comparator detuning influence | |
| CN103916125A (en) | Assembly line analog-digital converter | |
| TWI431946B (en) | Switched-capacitor circuit and pipelined analog-to-digital converter | |
| CN102270988B (en) | Shared operational transconductance amplifier pipelined ADC | |
| CN101980446B (en) | High-performance low-power consumption pipeline analogue-to-digital converter | |
| CN102013894B (en) | Low-power pipeline analogue-digital converter (ADC) | |
| CN109462402B (en) | Mixed type assembly line ADC structure | |
| CN101282120A (en) | Multiplication digital-to-analog conversion circuit and application thereof | |
| CN104753533B (en) | One kind is classified shared binary channels flow-line modulus converter | |
| CN1561000B (en) | Pipeline structure analogue/digital converter of controlling input common-mode drift | |
| CN101277115B (en) | Multiplying digital-analog conversion circuit sharing operational amplifier | |
| CN102801423A (en) | 2-phase threshold detector based circuits | |
| CN100586024C (en) | Double-sampling multiplication digital-analog conversion circuit and application thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121114 Termination date: 20170309 |