CN102420612B - Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching - Google Patents
Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching Download PDFInfo
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- CN102420612B CN102420612B CN2011104244764A CN201110424476A CN102420612B CN 102420612 B CN102420612 B CN 102420612B CN 2011104244764 A CN2011104244764 A CN 2011104244764A CN 201110424476 A CN201110424476 A CN 201110424476A CN 102420612 B CN102420612 B CN 102420612B
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Abstract
The invention discloses a time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching, and relates to the technical field of micro-electronics. The invention provides the structure of the time-interleaving analogue-to-digital converter capable of suppressing the sampling time mismatching aiming at the influence of the sampling time mismatching on the time-interleaving analogue-to-digital converter. The analogue-to-digital converter comprises a channel sampling and holding circuit, a sub-analogue-to-digital converter and a multiplexor. The channel sampling and holding circuit introduces a system main clock to determine a sampling time, so that the sampling time mismatching caused by sampling by each channel respectively is avoided, and the dynamic performance of the time-interleaving analogue-to-digital converter is improved effectively. In the method, the sampling and holding circuit does not need to be preposed, so that influence on an input signal bandwidth is avoided; moreover, the influence of charge injection is eliminated and the linearity of a system is improved by utilizing a lower pole plate sampling technology by the channel sampling and holding circuit.
Description
Technical field
The present invention relates to the analog to digital converter in microelectric technique, particularly relate to a kind of design of structure of the time-interleaved analog to digital converter that suppresses the sampling time mismatch.
Background technology
Analog to digital converter is a kind of instrument that is digital signal by analog signal conversion, and it is widely used in the fields such as Industry Control, radar, communication, consumer electronics as the interface of analogue technique and digital technology, in information technology, plays an important role.Along with updating with the introducing of new material of integrated circuit fabrication process makes Digital Signal Processing constantly progressive, thereby the speed of analog to digital converter is had higher requirement.
Improve at present one of most popular method of analog to digital converter speed and be the use that is together in parallel of a plurality of analog to digital converters.Utilize staggered clock that a plurality of analog to digital converters are taken turns to operate, in the situation that maintain single analog to digital converter tick-over, realize the raising of bulk velocity, this structure is called time-interleaved analog to digital converter (Time-interleaved ADC).
The basic structure that Fig. 1 is a time-interleaved analog to digital converter of four-way, each passage consists of a sampling hold circuit (S/H) and a sub-adc converter (ADC), and therefore the time-interleaved analog to digital converter of whole four-way comprises four sampling hold circuit (S/H
1, S/H
2, S/H
3and S/H
4), four sub-adc converter (ADC
1, ADC
2, ADC
3and ADC
4) and a multiplexer (MUX).The precision of each passage sub-adc converter is the N position, and operating rate is f
s/ 4, be operated in respectively four different phase places, the clock skew of adjacency channel is 90 °.Four passages are sampled and data transaction to input signal successively, and output speed is f respectively
s/ 4, the digital signal that precision is the N position is f finally by the multiplexer output speed
s, the precision digital signal that is the N position, thereby the operating rate that realizes whole analog to digital converter rises to 4 times of single analog to digital converter rate.The sequential chart that Fig. 2 is the time-interleaved analog to digital converter of four-way.
In theory, port number is more, and the operating rate of time-interleaved analog to digital converter is faster.But, in fact, there are the non-ideal factors such as sampling time mismatch (Timing mismatch), gain mismatch (Gain mismatch), imbalance mismatch (Offset mismatch) and bandwidth mismatch (Bandwidth mismatch) between each passage sub-adc converter, had a strong impact on the dynamic property of whole analog to digital converter.
For the sampling time mismatch, there are relevant paper and patent to propose a kind of solution, i.e. the preposition technology of sampling switch.The method by sampling switch is preposition, is controlled sampling instant by master clock, has avoided each channel clock caused sampling time mismatch of sampling respectively, can significantly improve the dynamic property of whole analog to digital converter.But the method can be brought two shortcomings:
1, the introducing of prefix switch can increase conducting resistance and the parasitic capacitance of signal path, reduces the input signal bandwidth, makes the relative error of signal bandwidth become large, and the impact of bandwidth mismatch further aggravates.
2, sampling instant is determined by the master clock of preposition sampling switch, make each channel sample holding circuit can not adopt the bottom crown Sampling techniques, thereby non-linear can't the avoiding such as charge injection that cause sampling switch to be introduced, worsen the linearity of whole analog to digital converter.
Summary of the invention
The object of the present invention is to provide and a kind ofly both can suppress the sampling time mismatch, do not affect again the time-interleaved analog-digital converter structure of input signal bandwidth and system linear degree, thereby effectively avoid the impact of sampling time mismatch, improve the dynamic property of whole analog to digital converter.
To achieve these goals, time-interleaved analog to digital converter provided by the invention as shown in Figure 3, comprises four identical sampling hold circuit (S/H
1, S/H
2, S/H
3and S/H
4), four identical sub-adc converter (ADC
1, ADC
2, ADC
3and ADC
4) and a multiplexer (MUX).With the difference of prior art (Fig. 5) be that sampling hold circuit of the present invention (Fig. 6) adds switch S 4, by four switches (S1, S2, S3 and S4), a sampling capacitance (C
sample) and an operational amplifier (AMP) composition.Switch S 4 is controlled by master clock MCLK, so the sampling instant of each passage determines by the trailing edge of MCLK, thereby has suppressed the sampling time mismatch that each channel clock is sampled respectively and caused.
The concrete annexation of the sampling hold circuit shown in Fig. 6 is as follows: the left end of switch S 1 meets input signal Vin, and right-hand member meets sampling capacitance (C
sample) left pole plate and the left end of switch S 2; The right-hand member of switch S 2 meets the right-hand member of switch S 4 and the output Vout of operational amplifier (AMP); The right pole plate of sampling capacitance connects the left end of switch S 3 and the anode of operational amplifier (AMP), the negativing ending grounding of operational amplifier (AMP), and the right-hand member of switch S 3 connects the left end of switch S 4.Switch S 1 and S3 have identical clock control signal CLKi(i and mean different passages, i=1,2,3,4), switch S 2 is by from the non-overlapping clock CLKib(i of CLKi two-phase, meaning different passages, i=1,2,3,4) control, switch S 4 is controlled by master clock MCLK.
The accompanying drawing explanation:
The schematic diagram that Fig. 1 is the time-interleaved analog to digital converter of traditional four-way
The sequential chart that Fig. 2 is the time-interleaved analog to digital converter of traditional four-way
The time-interleaved analog-digital converter structure figure of four-way that Fig. 3 designs for the present invention
The sequential chart of the time-interleaved analog-digital converter structure of four-way that Fig. 4 designs for the present invention
Fig. 5 is traditional sampling hold circuit (S/H) structure
The sampling hold circuit that Fig. 6 designs for the present invention (S/H) structure
The sequential chart of the sampling hold circuit that Fig. 7 designs for the present invention (S/H)
Embodiment
Further describe the present invention below in conjunction with figure.
Be illustrated in figure 3 the time-interleaved analog to digital converter of four-way that the present invention proposes, its sequential chart as shown in Figure 4.In Fig. 4, the duty ratio of each channel clock is 25%, at each sampling clock phase, only has all the time a channel sample, has therefore reduced the input signal load, increases the input bandwidth.Than the time-interleaved analog to digital converter of tradition (as shown in Figure 1), in Fig. 3, each channel sample holding circuit means different passages, i=1,2,3,4 by channel clock CLKi(i) and master clock MCLK control together, each channel sample time determines by MCLK.The specific works mode be take passage one as example, and the rest channels working method is identical.
As shown in Figure 6, its work schedule as shown in Figure 7 for the sampling hold circuit structure of passage one.Wherein, MCLK is master clock, and operating frequency is f
s; CLK1 and CLK1b are the non-overlapping clocks of two-phase, and operating frequency is f
s/ 4.The control signal of switch S 1 and S3 is CLK1, and the control signal of switch S 2 is CLK1b, and the control signal of switch S 4 is master clock MCLK.
Step 1, t
1constantly, MCLK and CLK1 saltus step simultaneously is high level, and the CLK1b saltus step is low level, so switch S 1, S3 and S4 conducting, and S2 disconnects, sampling capacitance C
sampleinput signal is followed the tracks of;
Step 2, t
2constantly, the MCLK saltus step is low level, and switch S 4 disconnects, sampling capacitance C
sampleright pole plate electric charge no longer changes;
Step 3, t
3constantly, the CLK1 saltus step is low level, and the CLK1b saltus step is high level, so switch S 1 and S3 disconnection, the S2 conducting, and the sampling capacitance upset, passage one enters maintenance stage, sub-adc converter ADC
1sampled value is changed to output N position digital signal DIG
1.
Step 5, in like manner, when the CLK2 saltus step is low level, passage two completes sampling and enters controlization maintenance stage, sub-adc converter ADC
2sampled value is changed to output N position digital signal DIG
2.Now, shown in Fig. 4, the CLK3 saltus step is high level, and three pairs of inputs of passage are followed the tracks of, and keep-process (repeating step 1～step 3) starts to sample.
Step 6, in like manner, when the CLK3 saltus step is low level, passage three completes sampling and enters maintenance stage, sub-adc converter ADC
3sampled value is changed to output N position digital signal DIG
3.Now, shown in Fig. 4, the CLK4 saltus step is high level, and four pairs of inputs of passage are followed the tracks of, and keep-process (repeating step 1～step 3) starts to sample.
Step 7, in like manner, when the CLK4 saltus step is low level, passage four completes sampling and enters maintenance stage, sub-adc converter ADC
4sampled value is changed to output N position digital signal DIG
4.Now, shown in Fig. 4, CLK1 saltus step again is high level, and a pair of input of passage is followed the tracks of, and keep-process (repeating step 1～step 3) starts to sample.
Visible according to step 1～step 7, four passages are sampled and are kept and data transaction input signal successively according to the timing relationship shown in Fig. 4, and constantly circulation, and cycle period is 4*T
s(T
sfor the cycle of master clock MCLK, T
s=1/f
s).Multiplexer (MUX) according to the phase relation of clock shown in Fig. 4 by each channel digital signal (DIG
1～DIG
4) output successively, thereby realized that precision is that N position, speed are f
shigh-speed transitions.The port number of time-interleaved analog to digital converter of the present invention can be for being more than or equal to two integer.
Time-interleaved analog to digital converter of the present invention has following four advantages:
1, at t
2constantly, the MCLK saltus step is low level, and switch S 4 disconnects, and the right pole plate electric charge of sampling capacitance is no longer followed input and changed, so this moment has determined sampled value.Then switch S 3 is than the late half master clock cycle (T of S4
s) disconnect, to sampled value without contribution, so the phase deviation of channel clock CLK1 on sampled result without any impact, in like manner the phase deviation of its excess-three channel clock on sampled result without any impact.
2, at t
2constantly, the MCLK saltus step is low level, and switch S 4 disconnects, and the right pole plate electric charge of sampling capacitance is no longer followed input and changed, and realizes the bottom crown sampling, has avoided the charge injection of sampling switch S1, has eliminated the nonlinear effect caused thus.
3, because the sampling switch S4 that master clock MCLK controls is not placed on the input signal path, the conducting resistance of switch and parasitic capacitance can not increase the load of input signal, therefore on the input signal bandwidth, can not produce any impact.
4, in this example, MCLK and CLK1 are saltus steps simultaneously, but in fact, as long as the high level of MCLK is covered by the high level of CLK1, just can realize above-mentioned functions, have therefore alleviated the master clock requirement of time of delay.
Above example is only preferred example of the present invention, and use of the present invention is not limited to this example, within the spirit and principles in the present invention all, any modification of doing, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (4)
1. the time-interleaved analog to digital converter that can suppress the sampling time mismatch, include sampling hold circuit (S/H), sub-adc converter (ADC) and a multiplexer (MUX), it is characterized in that: sampling hold circuit (S/H) is connected with master clock (MCLK), by master clock (MCLK), controls sampling instant;
This sampling hold circuit (S/H) is by four switches (S1, S2, S3 and S4), a sampling capacitance (C
sample) and an operational amplifier (AMP) composition, concrete annexation is as follows: the left end of switch S 1 meets input signal Vin, and right-hand member meets sampling capacitance (C
sample) left pole plate and the left end of switch S 2, the right-hand member of switch S 2 meets the right-hand member of switch S 4 and the output Vout of operational amplifier (AMP), the right pole plate of sampling capacitance connects the left end of switch S 3 and the anode of operational amplifier (AMP), the negativing ending grounding of operational amplifier (AMP), the right-hand member of switch S 3 connects the left end of switch S 4, switch S 1 and S3 have identical clock control signal CLKi(i and mean different passages, i=1, 2, 3, 4), by the non-overlapping clock CLKib control of the two-phase from clock CLKi, (i means different passages to switch S 2, i=1, 2, 3, 4), switch S 4 is controlled by master clock MCLK, each channel sample determines by the trailing edge of master clock MCLK constantly.
2. time-interleaved analog to digital converter according to claim 1, it is characterized in that: this time-interleaved analog to digital converter is by four sampling hold circuit (S/H
1, S/H
2, S/H
3and S/H
4), four sub-adc converter (ADC
1, ADC
2, ADC
3and ADC
4) and a multiplexer (MUX) formation, sampling hold circuit (S/H
1, S/H
2, S/H
3and S/H
4) connect respectively master clock (MCLK).
3. according to claim 1, or the time-interleaved analog to digital converter that suppresses the sampling time mismatch claimed in claim 2, it is characterized in that: passage one sampling hold circuit S/H
1the process that sampling keeps is as follows:
Step 1: when clock CLK1 and master clock MCLK saltus step simultaneously is high level, when clock CLK1b saltus step is low level, switch S 1, S3 and S4 conducting, S2 disconnects, sampling capacitance C
sampleit is that sampling hold circuit is followed input signal that input signal is followed the tracks of;
Step 2: when master clock MCLK saltus step is low level, switch S 4 disconnects, sampling capacitance C
sampleright pole plate electric charge no longer changes, and sampling finishes;
Step 3: when clock CLK1 saltus step is low level, clock CLK1b saltus step is high level, so switch S 1 and S3 disconnection, the S2 conducting, and the sampling capacitance upset, passage one enters the maintenance stage, sub-adc converter (ADC
1) sampled value is changed to output N position digital signal, DIG
1;
In like manner: the sampling hold circuit (S/H of rest channels
2, S/H
3and S/H
4) according to timing relationship, successively input signal is sampled and kept and data transaction, repeat passage one sampling hold circuit (S/H
1) the sampling keep-process, step 1～step 3 as mentioned above, respectively by sub-adc converter (ADC
2, ADC
3and ADC
4) sampled value is changed, export respectively N position digital signal (DIG
2, DIG
3, DIG
4), enter multiplexer (MUX), multiplexer (MUX) according to the phase relation of clock by each channel digital signal (DIG
1～DIG
4) output successively, thereby realized that precision is that N position, speed are that operating frequency is f
shigh-speed transitions.
4. according to the time-interleaved analog to digital converter of the mismatch of the suppressed sampling time described in claim 1, it is characterized in that: the total number of channels of analog to digital converter can be the integer that is more than or equal to two.
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|---|---|---|---|
| CN2011104244764A CN102420612B (en) | 2011-12-16 | 2011-12-16 | Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching |
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| CN102420612A CN102420612A (en) | 2012-04-18 |
| CN102420612B true CN102420612B (en) | 2013-11-13 |
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| US7292170B2 (en) * | 2005-06-13 | 2007-11-06 | Texas Instruments Incorporated | System and method for improved time-interleaved analog-to-digital converter arrays |
| CN101281792A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Sampling hold circuit |
| CN101217278A (en) * | 2008-01-10 | 2008-07-09 | 复旦大学 | A time interlacing structure A/D converter that can suppress the influence of sampling clock phase deviation |
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