CN101277115B - Multiplying digital-analog conversion circuit sharing operational amplifier - Google Patents
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Abstract
The invention relates to the technical field of digital signal processing, and discloses an MDAC circuit shared by operational amplifiers, which comprises: a first stage MDAC circuit for performing residual amplification on differential signals in1 and in2 received from the outside and outputting the obtained differential signals out1 and out2 to a second stage MDAC; and the second-stage MDAC circuit is used for performing residual amplification on the differential signals out1 and out2 received from the first-stage MDAC and outputting the obtained differential signals at the same pair of differential nodes out1 and out2 in another clock phase which is not overlapped. The invention also discloses a production line ADC using the operational amplifier shared multiplication digital-to-analog conversion circuit. The invention realizes the improvement of the traditional operational amplifier sharing MDAC circuit, and improves the precision and the speed of the operational amplifier sharing MDAC circuit while having the same power consumption optimization with the traditional operational amplifier sharing MDAC circuit.
Description
Technical field
The present invention relates to digital signal processing technique field, relate in particular to a kind of multiplication D/A conversion circuit (Multiplying Digital to Analog Circuit of shared operational amplifier, MDAC), and use this MDAC circuit production line analog-digital converter (Analog to Digital Circuit, ADC).
Background technology
At present, along with the extensive use of Digital Signal Processing in the communications field, high speed modem, broadband cabled and wireless telecommunication system is increasing to the demand of medium accuracy, high-speed AD converter.In the ADC of various structures, pipeline ADC is widely adopted in distinctive compromise advantage aspect speed, power consumption and the area with it.
As shown in Figure 1, Fig. 1 is the structural representation of traditional pipeline ADC.It by front-end sampling/maintenance (S/H) circuit, several sub levels (STAGE1, STAGE2 ..., STAGE k-1, FLASH), time-delay SYN register array and digital correction module form.In Fig. 1, except that the low level flash type ADC (being FLASH) of front end S/H circuit and afterbody, all the other are at different levels (STAGE1, STAGE2 ..., STAGE k-1) all comprise S/H circuit, subnumber weighted-voltage D/A converter (SubDAC), sub-adc converter (SubADC), subtracter and surplus poor amplifier.As shown in Figure 2, Fig. 2 is the structural representation of each sub level in the traditional pipeline ADC structure.
In Fig. 2, ph1 and ph2 are the two-phase clocks that do not overlap, and odd level is controlled sampling with ph1, and even level and front end S/H circuit are controlled sampling with ph2, and promptly the control clock of adjacent two-stage is opposite mutually.Generally the S/H circuit in the sub level shown in Figure 2, subnumber weighted-voltage D/A converter, subtracter and surplus poor amplifier are combined into MDAC.
Pipeline ADC is under two-phase does not overlap clock control, make front end S/H circuit in the pipeline ADC and each streamline sub level sampling mutually and between amplifying mutually alternation finish conversion.Input signal is at first sampled by front end S/H circuit, and in the maintenance stage, the signal that is kept is handled by the sub-adc converter among the STAGE1, produces B
1+ r
1Digit numeric code, the subnumber weighted-voltage D/A converter of sending among the STAGE1 when this digital code is admitted to time-delay SYN register array is converted to analog signal again, and in subtracter, subtract each other with original input signal, the result who subtracts each other is called as surplus poor, and this surplus difference signal multiply by 2 in surplus poor amplifier
R1, being admitted to STAGE2 again and handling, this process repeats up to STAGE k-1 level, and afterbody only carries out analog-to-digital conversion, produces B
kDigit numeric code is sent into time-delay SYN register array, does not carry out surplus difference and amplifies.The digital codes that produce at different levels are exported final digital code then through time-delay SYN register arrays alignings of delaying time after digital correction module is carried out correction process.
High-speed high-precision flow line ADC needs the surplus poor amplifier of high-speed, high precision, this has proposed higher requirement to the operational amplifier that carries out surplus difference amplification, and it is high more to the precision and the rate request of operational amplifier, the power consumption of operational amplifier is big more, therefore under the certain condition of operational amplifier power consumption, the number that reduces operational amplifier is very effective for the power consumption that reduces whole ADC.
Traditional MDAC circuit as shown in Figure 3, Fig. 3 is the structural representation of traditional MDAC circuit.In Fig. 3, ph1 represents two clocks that do not overlap mutually with ph2, and ph1e opens a little in advance than ph1, during the switch conduction of ph1 and ph1e control for sampling mutually, during the switch conduction of ph2 control for amplifying phase.Can see that operational amplifier is in reset mode mutually in sampling, only work mutually in amplification.Utilize operational amplifier in the mutually idle characteristics of sampling, the operational amplifier technology of sharing is at the shared operational amplifier of the mutually opposite two-stage of clock, make operational amplifier in running order always mutually at two clocks, thus make operational amplifier decreased number half.
Traditional operational amplifier is shared the MDAC circuit as shown in Figure 4, and Fig. 4 is the structural representation that traditional operational amplifier is shared the MDAC circuit.In Fig. 4, clock signal ph2e opens a little in advance than ph2, and in1 is the input voltage of clock phase ph1 MDAC, the output of a phase on the input voltage of clock phase ph2 MDAC is.The subject matter that this circuit exists has two: the one, because operational amplifier is in running order all the time, the parasitic capacitance of operational amplifier input has been preserved the information of a last phase, especially operational amplifier input parasitic capacitance is very big when the gain of operational amplifier and bandwidth are all bigger, has had a strong impact on the precision of MDAC; The 2nd, be in the amplification phase time when the MDAC circuit, influenced the speed of MDAC with the conducting resistance of the switch (i.e. the switch switch1 and the switch2 of ph1 and ph2 control among the figure) of input polyphone.
Summary of the invention
(1) technical problem that will solve
In view of this, the MDAC circuit that one object of the present invention is to provide a kind of operational amplifier to share, to realize the conventional operation amplifier is shared the improvement of MDAC circuit, sharing precision and the speed that improves the shared MDAC circuit of operational amplifier when the MDAC circuit has identical optimised power consumption with the conventional operation amplifier.
(2) technical scheme
For reaching an above-mentioned purpose, the invention provides the multiplication D/A conversion circuit that a kind of operational amplifier is shared, this circuit comprises:
First order multiplication D/A conversion (MDAC) circuit is used for carrying out surplus difference amplification to being received from outside differential signal in1 and in2, and differential signal out1 and the out2 that obtains exported to second level MDAC;
Second level MDAC circuit is used for the differential signal out1 and the out2 that are received from first order MDAC are carried out surplus difference amplification, and at another clock that does not overlap the differential signal that obtains is being exported with a pair of difference node out1 and out2;
Wherein, the double input end operational amplifier of described first order MDAC circuit and second level MDAC circuit clock system in shared a period of time, the double input end operational amplifier of this clock control adopts the double input end folded form operational amplifier of clock control, or adopt the double input end folded form gain of clock control to promote operational amplifier, the double input end folded form operational amplifier of clock control or the gain of the double input end folded form of clock control promote operational amplifier and have two pairs of identical inputs, when being in the ph1 phase time, input is to the first metal-oxide-semiconductor M1 and second metal-oxide-semiconductor M2 work, and receiving common-mode point, opin1 and opin2 reset, the second phase place metal-oxide-semiconductor Mph2 disconnects, and does not have electric current to flow through the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4; Then opposite when being in the ph2 phase time, input is to the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 work, and opin1_2 and opin2_2 receive common-mode point and reset, and the first phase place metal-oxide-semiconductor Mph1 disconnects, and does not have electric current to flow through the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2.
In the such scheme, described first order MDAC circuit comprises: the first differential switch capacitor cell, the second differential switch capacitor cell and the double input end operational amplifier of clock system for the moment, the described first differential switch capacitor cell, the second differential switch capacitor cell and for the moment the double input end operational amplifier of clock system realize that jointly the sampling of differential signal in1 and in2 and surplus difference amplify.
In the such scheme, described second level MDAC circuit comprises the double input end operational amplifier of the 3rd differential switch capacitor cell and clock system in a period of time, and the double input end operational amplifier of described the 3rd differential switch capacitor cell and clock control is realized sampling and the surplus difference amplification of differential signal out1 and out2 jointly.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilize the present invention, because each clock cycle opin1, opin2 and opin1_2, opin2_2 have one to receive the process that common-mode point resets, the input parasitic capacitance can not preserved the information of a phase, thereby effectively raises the precision of MDAC.
2, utilize the present invention, because whether do not overlap time that or not of clock of two-phase very short in high-speed pipeline analog-to-digital converter, the tail current of operational amplifier remains unchanged when two pairs of input exchanges substantially, and eliminated the switch that input is contacted, so this structure effectively raises the speed of MDAC.
3, utilize the present invention because the shared operational amplifier of two-stage, the operational amplifier technology of sharing with the decreased number of operational amplifier half, effectively shortened the design cycle, the area that also reduced chip has greatly reduced cost.
Description of drawings
Fig. 1 is the structural representation of traditional pipeline ADC;
Fig. 2 is the structural representation of each sub level in the traditional pipeline ADC structure;
Fig. 3 is the structural representation of traditional MDAC circuit;
Fig. 4 is the structural representation that traditional operational amplifier is shared the MDAC circuit;
Fig. 5 is the structural representation that operational amplifier provided by the invention is shared the MDAC circuit;
Fig. 6 is the circuit structure diagram of the double input end folded form operational amplifier of clock control;
Fig. 7 promotes the circuit structure diagram of operational amplifier for the double input end folded form gain of clock control;
Fig. 8 is the structural representation that application operational amplifier provided by the invention is shared the pipeline ADC of MDAC circuit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and, be example with every grade of effective MDAC circuit of output 2 bits, 1 bit with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 5, Fig. 5 is the structural representation that operational amplifier provided by the invention is shared the MDAC circuit.This operational amplifier is shared the MDAC circuit and is comprised first order MDAC circuit and second level MDAC circuit.Wherein, first order MDAC circuit is used for carrying out surplus difference amplification to being received from outside differential signal in1 and in2, and differential signal out1 and the out2 that obtains exported to second level MDAC.First order MDAC circuit comprises: the first differential switch capacitor cell 2, the second differential switch capacitor cell 3 and the double input end operational amplifier 1 of clock system for the moment, the described first differential switch capacitor cell 2, the second differential switch capacitor cell 3 and the double input end operational amplifier 1 common differential signal in1 of realization of clock system and sampling and the surplus difference of in2 are amplified for the moment.
Second level MDAC circuit is used for differential signal out1 that is received from first order MDAC and out2 are carried out surplus difference amplification, and at another clock that does not overlap the differential signal that obtains is being exported with a pair of difference node out1 and out2.Second level MDAC circuit comprises the double input end operational amplifier 1 of the 3rd differential switch capacitor cell 4 and clock system in a period of time, described the 3rd differential switch capacitor cell 4 and the double input end operational amplifier 1 common realization differential signal out1 of clock system and sampling and the surplus poor amplification of out2 for the moment.
The double input end operational amplifier of first order MDAC circuit and second level MDAC circuit clock system in shared a period of time, the double input end operational amplifier of this clock control can adopt the double input end folded form operational amplifier of clock control, also can adopt the double input end folded form gain of clock control to promote operational amplifier.As shown in Figure 6 and Figure 7, Fig. 6 is the circuit structure diagram of the double input end folded form operational amplifier of clock control, and Fig. 7 promotes the circuit structure diagram of operational amplifier for the double input end folded form gain of clock control.
Node opin1, opin2 among Fig. 5, opin1_2, opin2_2, ph1, ph2, out1, out2 correspond respectively to node opin1, opin2, opin1_2, opin2_2, ph1, ph2, out1, the out2 among Fig. 6 and Fig. 7.
In Fig. 6 and Fig. 7, operational amplifier has two pairs of identical inputs, and when being in the ph1 phase time, input is to pipe M1 and M2 work, and opin1 and opin2 receive common-mode point and reset, and Mph2 disconnects, and does not have electric current to flow through M3 and M4; Then opposite when being in the ph2 phase time, input is to pipe M3 and M4 work, and opin1_2 and opin2_2 receive common-mode point and reset, and Mph1 disconnects, and does not have electric current to flow through M1 and M2.
In first order MDAC circuit, the top crown of the top crown of Cs1, Cf1 and Cs2, Cf2 is received respectively on node opin1, the opin2.In the ph1 phase, node opin1, opin2 connect common mode, and in1 and in2 are received the sole plate of capacitor C s1, Cf1 and Cs2, Cf2 respectively and sample; In the ph2 phase, the sole plate of Cf1 and Cf2 is received out1 and out2 respectively, and the sole plate of Cs1 and Cs2 connects the output of DAC1 respectively.The in1 that is input as the ph1 phase and the in2 of first order MDAC circuit are output as the out1 and the out2 of ph2 phase.
In the MDAC circuit of the second level, the top crown of the top crown of Cs1_2, Cf1_2 and Cs2_2, Cf2_2 is received respectively on node opin1_2, the opin2_2.In the ph2 phase, node opin1_2, opin2_2 connect common mode, and out1 and out2 are received the sole plate of capacitor C s1_2, Cf1_2 and Cs2_2, Cf2_2 respectively and sample; In the ph2 phase, the sole plate of Cf1_2 and Cf2_2 is received out1 and out2 respectively, and the sole plate of Cs1_2 and Cs2_2 connects the output of DAC2 respectively.The out1 that is input as the ph2 phase and the out2 of second level MDAC circuit are output as the out1 and the out2 of ph1 phase.
Because each clock cycle opin1, opin2 and opin1_2, opin2_2 have one to receive the process that common-mode point resets, the input parasitic capacitance can not preserved the information of a phase, thereby effectively raises the precision of MDAC; Because whether do not overlap time that or not of clock of two-phase very short in high-speed pipeline analog-to-digital converter, the tail current of operational amplifier remains unchanged when two pairs of input exchanges substantially, and eliminated the switch that input is contacted, so this structure effectively raises the speed of MDAC.
Because the shared operational amplifier of two-stage, the operational amplifier technology of sharing with the decreased number of operational amplifier half, effectively shortened the design cycle, the area that also reduced chip has greatly reduced cost.
The MDAC circuit that the operational amplifier that provides based on the invention described above is shared, the present invention also provides a kind of pipeline ADC that operational amplifier is shared multiplication D/A conversion circuit of using, and this pipeline ADC comprises front end S/H circuit, flowing water sub level, time-delay SYN register array and digital correction module.
Wherein, front end S/H circuit is used for being received from the V of ADC input
InSignal is sampled and is kept, with the first order in the flowing water sub level exported to that obtains.The flowing water sub level is used for analog-to-digital conversion and surplus difference amplification are carried out in the analog signal classification that is received from sampling hold circuit, and the numeral that obtains is exported to time-delay SYN register array, and next stage flowing water sub level is exported in simulation.Time-delay SYN register array is used for the digital signal that is received from each the flowing water sub level aligning of delaying time is exported to digital correction module with the numeral that obtains.The numeral correction module is used for the digital signal that is received from time-delay SYN register array is carried out shifter-adder, obtains the numeral output of ADC.
As shown in Figure 8, Fig. 8 is the structural representation that application operational amplifier provided by the invention is shared the pipeline ADC of MDAC circuit.This pipeline ADC is one 10 bit stream waterline ADC, is made up of front end S/H circuit, 9 flowing water sub levels (being STAGE1, STAGE2, STAGE3, STAGE4, STAGE5, STAGE6, STAGE7, STAGE8 and FLASH), time-delay SYN register array and digital correction module.
In Fig. 8, ph1 represents two clocks that do not overlap mutually with ph2, and odd level is controlled sampling with ph1, and even level and sampling hold circuit (S/H) are controlled sampling with ph2.STAGE1, STAGE2 ..., STAGE8 all comprises a sub-adc converter and a MDAC circuit, 2 of every grade of outputs, 1 effectively, redundant digit is used for carrying out digital error correction.Afterbody (FLASH) is the ADC of 2 bit flash structures, exports 2 effectively.
Input signal is at first sampled by the S/H circuit, in the maintenance stage, the signal that is kept is handled by the sub-adc converter among the STAGE1, produce 2 digit numeric codes, the MDAC circuit of sending into STAGE1 when this digital code is admitted to time-delay SYN register sequence produces the surplus difference signal that amplifies and sends into STAGE2 and handle, and this process repeats until the 8th grade, and afterbody only carries out analog-to-digital conversion, produce 2 digit numeric codes and send into time-delay SYN register sequence, do not carry out surplus difference and amplify.All that produce 18 digit numeric codes at different levels are handled through digital correction module then and are exported 10 final digit numeric codes through time-delay SYN register sequences alignings of delaying time.
STAGE1, STAGE2 ..., these 8 grades of adjacent two-stages of STAGE8 the shared operational amplifier of MDAC circuit.Because previous stages is higher to the operational amplifier required precision, the folded form operational amplifier of the MDAC circuit of the MDAC circuit of the folding gain hoist type operational amplifier STAGE5 of the MDAC circuit of the MDAC circuit of STAGE1, the MDAC circuit of STAGE2, STAGE3 and the shared clock control shown in Figure 7 of MDAC circuit of STAGE4, the MDAC circuit of STAGE6, STAGE7 and the shared clock control shown in Figure 6 of MDAC circuit of STAGE8.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. the multiplication D/A conversion circuit of a shared operational amplifier is characterized in that, this circuit comprises:
First order multiplication D/A conversion MDAC circuit is used for carrying out surplus difference amplification to being received from outside differential signal in1 and in2, and differential signal out1 and the out2 that obtains exported to second level MDAC;
Second level MDAC circuit is used for the differential signal out1 and the out2 that are received from first order MDAC are carried out surplus difference amplification, and at another clock that does not overlap the differential signal that obtains is being exported with a pair of difference node out1 and out2;
Wherein, the double input end operational amplifier of described first order MDAC circuit and second level MDAC circuit clock system in shared a period of time, the double input end operational amplifier of this clock control adopts the double input end folded form operational amplifier of clock control, or adopts the double input end folded form gain of clock control to promote operational amplifier; The double input end folded form operational amplifier of clock control or the gain of the double input end folded form of clock control promote operational amplifier and have two pairs of identical inputs, when being in the ph1 phase time, input is to first metal-oxide-semiconductor (M1) and second metal-oxide-semiconductor (M2) work, and receiving common-mode point, opin1 and opin2 reset, the second phase place metal-oxide-semiconductor (Mph2) disconnects, and does not have electric current to flow through the 3rd metal-oxide-semiconductor (M3) and the 4th metal-oxide-semiconductor (M4); Then opposite when being in the ph2 phase time, input is to the 3rd metal-oxide-semiconductor (M3) and the 4th metal-oxide-semiconductor (M4) work, and opin1_2 and opin2_2 receive common-mode point and reset, and the first phase place metal-oxide-semiconductor (Mph1) disconnects, and does not have electric current to flow through first metal-oxide-semiconductor (M1) and second metal-oxide-semiconductor (M2).
2. the multiplication D/A conversion circuit of shared operational amplifier according to claim 1, it is characterized in that, described first order MDAC circuit comprises: the first differential switch capacitor cell, the second differential switch capacitor cell and the double input end operational amplifier of clock system for the moment, the described first differential switch capacitor cell, the second differential switch capacitor cell and for the moment the double input end operational amplifier of clock system realize that jointly the sampling of differential signal in1 and in2 and surplus difference amplify.
3. the multiplication D/A conversion circuit of shared operational amplifier according to claim 1, it is characterized in that, described second level MDAC circuit comprises the double input end operational amplifier of the 3rd differential switch capacitor cell and clock system in a period of time, and the double input end operational amplifier of described the 3rd differential switch capacitor cell and clock control is realized sampling and the surplus difference amplification of differential signal out1 and out2 jointly.
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| CN102025378B (en) * | 2009-09-14 | 2014-06-18 | 晨星软件研发(深圳)有限公司 | Multichannel sigma-delta converting circuit with shared operational amplifier and associated method thereof |
| CN102904571A (en) * | 2011-07-29 | 2013-01-30 | 比亚迪股份有限公司 | Allowance gain circuit |
| CN112690799A (en) * | 2020-12-25 | 2021-04-23 | 南京邮电大学 | Low-power consumption chopper amplifier circuit |
| CN114696829B (en) * | 2020-12-28 | 2024-07-02 | 北京特邦微电子科技有限公司 | Analog-to-digital conversion circuit and pipeline analog-to-digital converter |
| CN117439602A (en) * | 2023-12-21 | 2024-01-23 | 上海维安半导体有限公司 | Operational amplifier sharing multiple digital-to-analog conversion circuit |
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| CN1601907A (en) * | 2003-09-25 | 2005-03-30 | 三洋电机株式会社 | Pipelined and cyclic analog-to-digital converters |
| CN1677869A (en) * | 2004-03-31 | 2005-10-05 | 矽统科技股份有限公司 | Pipeline type analog-to-digital converter capable of conducting back ground correction |
| US20060125675A1 (en) * | 2004-12-13 | 2006-06-15 | Texas Instruments Incorporated | Reducing Errors and Power Consumption in a Multi-stage Analog to Digital Converter (ADC) Using Amplifier Sharing Techniques |
| WO2006072030A1 (en) * | 2004-12-30 | 2006-07-06 | Texas Instruments Incorporated | Switched-capacitor circuit with scaled reference voltage |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1601907A (en) * | 2003-09-25 | 2005-03-30 | 三洋电机株式会社 | Pipelined and cyclic analog-to-digital converters |
| CN1677869A (en) * | 2004-03-31 | 2005-10-05 | 矽统科技股份有限公司 | Pipeline type analog-to-digital converter capable of conducting back ground correction |
| US20060125675A1 (en) * | 2004-12-13 | 2006-06-15 | Texas Instruments Incorporated | Reducing Errors and Power Consumption in a Multi-stage Analog to Digital Converter (ADC) Using Amplifier Sharing Techniques |
| WO2006072030A1 (en) * | 2004-12-30 | 2006-07-06 | Texas Instruments Incorporated | Switched-capacitor circuit with scaled reference voltage |
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