CN101834212A - Transistor device of crystallized thin film - Google Patents
Transistor device of crystallized thin film Download PDFInfo
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- CN101834212A CN101834212A CN 201010111999 CN201010111999A CN101834212A CN 101834212 A CN101834212 A CN 101834212A CN 201010111999 CN201010111999 CN 201010111999 CN 201010111999 A CN201010111999 A CN 201010111999A CN 101834212 A CN101834212 A CN 101834212A
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Abstract
The invention provides a transistor device of a crystallized thin film. The transistor device of the crystallized thin film comprises a polysilicon thin film, a gate oxide layer, an insulating layer and a metal interconnecting layer, wherein the polysilicon thin film comprises a glass substrate, a blocking layer and a polysilicon layer with continuous crystal domains; the thickness of the polysilicon layer is 10 to 500 nanometers; crystalline grains in the polysilicon layer are distributed uniformly; and the polysilicon layer is a uniform polysilicon layer formed by the steps of photoetching induction port on a covering layer on a non-crystalline silicon thin film, contacting a metal induction film and the non-crystalline silicon thin film at the induction port and carrying out annealing crystallization twice.
Description
Technical field
The present invention relates to the polysilicon membrane preparing technical field, more specifically, the present invention relates to a kind of transistor device of crystallization thin film.
Background technology
The mature preparation process of amorphous silicon film transistor (TFT) is also simple relatively, the rate of finished products height, and cost is low, and existing Active Matrix Display adopts amorphous silicon film transistor more.But the field-effect mobility of amorphous silicon film transistor is low, and the less stable of device is difficult to satisfy the colored sequential liquid crystal demonstration of high-speed switch, the requirement that Organic Light Emitting Diode shows and integrated-type shows of current drives.Prepare on the glass substrate, by the low-temperature polysilicon film transistor that annealing furnace or LASER HEATING obtain, have higher mobility and device stability preferably, be suitable for the preparation of the display application of high-speed switch, current drives and integrated substrate.
The very high temperature (620-650 ℃ usually) of arts demand of using the conventional low chemical vapor deposition (CVD) to obtain polysilicon realizes, and only be suitable for valuable quartz substrate by the polysilicon of more high temperature (more than 1000 ℃) annealing formation, and be not suitable for common glass substrate.
At present, the crystallization method of amorphous silicon mainly comprises the crystallization method of laser radiation heating amorphous silicon and the crystallization method of metal inducement amorphous silicon.Usually in metal-induced crystallization, induce the residual volume of metal in polysilicon membrane in order effectively to control, the uniformity consistency of raising prepared in batches polysilicon on the large tracts of land substrate, adopted the technology of metal-induced lateral crystallization, but the loss that the oxidizing process in this metal-induced lateral crystallization process can produce polysilicon.
Fig. 1 illustrates the polysilicon membrane of absorbing the residual crop of metal after the metal-induced lateral crystallization process of prior art and forming.As shown in Figure 1, covering barrier layer 102 on the substrate 101, and deposition of amorphous silicon films 103, add metal induction layer 201 on amorphous silicon membrane 103, and annealing makes its crystallization, forms layer of metal absorbed layer 301 then thereon, and the unnecessary metal of inducing is absorbed out.But in this manufacture process the time of PROCESS FOR TREATMENT longer, and in crystallization owing to comprised too much nickel, make that the density of nucleus is excessive, this is unfavorable for the generation of macromeritic polysilicon.
A kind of technology (U.S. Pat 2002192884) that prior art also exists absorption process and metal-induced lateral crystallization to carry out simultaneously, in this technical scheme, pre-deposition one deck is absorbed layer before forming the precursor amorphous silicon.But the absorption process takes place too early, also the nickel that is used to form crystal grain around the nuclei of crystallization is absorbed when the nickel of nuclei of crystallization place high concentration is absorbed, and has influenced the crystalline quality and the crystallization rate of polysilicon; And, absorb metal too near the polycrystalline silicon device active layer, the existence of absorbing layer can influence the final response of TFT.
Summary of the invention
The polysilicon membrane complicated process of preparation, the residue that have now in the transistor device are many in order to overcome, the defective of poor performance, and the present invention proposes a kind of transistor device of crystallization thin film.
According to an aspect of the present invention, a kind of transistor device of crystallization thin film has been proposed, comprise: polysilicon membrane, gate oxide, insulating barrier and metal interconnecting layer, wherein, described polysilicon membrane comprises glass substrate, barrier layer and the polysilicon layer with continuous domain; Wherein, the thickness of described polysilicon layer is the 10-500 nanometer, and the uniform crystal particles in the described polysilicon layer distributes; Wherein, described polysilicon layer is the even polysilicon layer that the metal inducement film is contacted with described amorphous silicon membrane and form through the twice annealing crystallization by the cover layer photoetching induction port on amorphous silicon membrane, at described induction port.
Wherein, described gate oxide is the cryogenic oxidation silicon of the 20-200 nanometer thickness that deposits on described polysilicon membrane, and described gate oxide comprises silica, silicon nitride or silicon oxynitride.
Described transistor device also comprises the active layer that has between heavily doped source-drain area, wherein, for N type amorphous silicon film transistor (TFT), adopts the phosphorus source, and energy is 130KeV, and concentration is 4 * 10
15Square centimeter carries out ion and injects; For P type TFT, adopt the boron source, energy is 40KeV, concentration is 4 * 10
15Square centimeter, 500-600 ℃ of annealing was afterwards carried out ion in 1-2 hour and is injected.
Wherein, described glass substrate is the glass commonly used that is used to prepare TFT such as healthy and free from worry 1737F, hawk 2000, and its thickness is the 0.3-1.5 millimeter.
Described barrier layer is for adopting silicon oxide layer or the silicon nitride layer such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) growth, and thickness is the 30-900 nanometer.
Described barrier layer is the silicon nitride of 200 nanometer thickness or the cryogenic oxidation silicon (LTO) of 100 nanometer thickness.
Wherein, described amorphous silicon thin layer adopts low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or sputtering method to be deposited on the described barrier layer, and wherein said amorphous silicon thickness of thin layer is the 10-500 nanometer.
Described cover layer photoetching induction port on amorphous silicon membrane is meant sedimentary cover on described amorphous silicon membrane layer, adopts photoetching process to form the induction port of nucleus growth location then in described cover layer.
Wherein, described induction port arranges continuously, evenly distribute, and each induction port is identical square, circle of physical dimension or strip aperture.
Wherein, the width of described induction port or radius are 2 microns to 20 microns, and the spacing distance between the hole is identical, are 30 microns to 300 microns; Perhaps, described induction port width is 2 microns, 30 microns of spacing distances.
Wherein, at described induction port the metal inducement film is contacted with described amorphous silicon membrane and be meant that the described metal inducement film of the low nickel-content that methods such as adopting sputter, evaporation, ion injection, solution immersion or spin coating forms is in described induction port place and the reaction of described amorphous silicon membrane, the induced nuclei that obtains dispersing, and grow into the low-density polysilicon " island " that yardstick is 10-20 micron, circular domain.
Wherein, described process twice annealing crystallization comprises annealing process and annealing process for the first time for the second time, the described annealing first time is carried out under nitrogen atmosphere, annealing temperature 550-590 ℃, time 1-2 hour, the described second step annealing process is finished under nitrogen atmosphere, and annealing temperature 550-590 ℃, time 2-3 hour.
Wherein, the described metal of inducing is absorbed gradually by the metal absorbed layer and the propelling of metal inducement polysilicon forward position, and along with the propelling of crystallization process, the metallic nickel of induction port is absorbed in the absorbed layer, induces the peak head-on collision to form crystal boundary.
The transistorized preparation process of the present invention's preparation comprises crystallization and absorbs process targetedly that wherein: (1) forms the micro-nickel source in amorphous silicon surfaces, uses induction port to be controlled to the position of epipole in advance; (2), form the polysilicon spot at the induction port place through first step annealing; (3) at above-mentioned film surface, sedimentary phosphor silex glass (PSG) film, and carry out the annealing second time, finish the crystallization process of whole polysilicon membrane.The PSG film side absorbs the nickel crystal limit growth at induction port place, needs the ground of consumable nickel to protect well around induction port in the crystallization process and is not absorbed by PSG.Therefore, there is not the interval as the obvious high nickel content of the induction port among traditional MILC in such crystallization process, and any zone of whole polysilicon membrane can be as the active layer of TFT.
The present invention includes crystallization and absorb process targetedly, when shortening the process time, the polysilicon membrane that can obtain to have continuous domain.Thereby further make any zone of whole polysilicon membrane to have eliminated the crystallization process glass substrate and to have shunk the aligning plate problem of misalignment that causes as the active layer of high-quality TFT.
The present invention also is optimized design to the induction port of nucleus location, forms the honeycomb crystal film such as regular hexagon.Because the rule that is distributed as of induction port repeats to distribute, the domain shape of formation and measure-alike can accurately be controlled crystallization process, has the high controllability of crystallization time and the high stability of technical process, is suitable for the suitability for industrialized production requirement.
Description of drawings
Fig. 1 is the schematic diagram of the metal inducement polysilicon membrane of prior art;
Fig. 2 is the structural representation of polysilicon membrane according to an embodiment of the invention;
Fig. 3 is polysilicon membrane preparation method's a flow chart according to an embodiment of the invention;
Fig. 4 (a) is that polysilicon membrane induction port place in first time annealing process forms the schematic cross-section of polysilicon " island " according to an embodiment of the invention;
Fig. 4 (b) is the sectional view of polysilicon membrane behind the crystal film surface deposition metal absorbed layer after the first time annealing process according to an embodiment of the invention;
Fig. 5 is the polysilicon island distribution schematic diagram that induction port distributes by equilateral triangle;
Fig. 6 is the crystal structure schematic diagram of polysilicon membrane prepared in accordance with the present invention.
Embodiment
Be described in detail below in conjunction with the transistor device of the drawings and specific embodiments a kind of crystallization thin film provided by the invention.
Fig. 2 illustrates the structure of polysilicon membrane according to an embodiment of the invention.As shown in Figure 2, this polysilicon membrane comprises glass substrate 101, barrier layer 102 and the polysilicon layer 103 with continuous domain.Wherein, glass substrate 101 is the glass commonly used that healthy and free from worry 1737F, hawk 2000 etc. are used to prepare TFT, and thickness is the 0.3-1.5 millimeter.Barrier layer 102 is for adopting the silicon oxide layer or the silicon nitride layer of low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) growth, and thickness is the 30-900 nanometer; Preferably, such as the silicon nitride of 200 nanometer thickness or the cryogenic oxidation silicon (LTO) of 100 nanometer thickness.The thickness of polysilicon layer 103 is generally the 10-500 nanometer, and it is the honeycomb crystal film of regular hexagon.Uniform crystal particles distributes in this polysilicon layer 103.This polysilicon layer 103 is the even polysilicon layers that the metal inducement film contacted with amorphous silicon membrane and form through the twice annealing crystallization by the cover layer photoetching induction port on amorphous silicon membrane, at induction port, this initial amorphous silicon thin layer adopts low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) and sputtering method to be deposited on the barrier layer, and the amorphous silicon thickness of thin layer is the 10-500 nanometer.
Fig. 3 illustrates the preparation method's of polysilicon membrane flow chart according to an embodiment of the invention.Generally speaking, as shown in Figure 3, this method comprises: cvd silicon oxide or silicon nitride barrier on glass substrate, and deposition of amorphous silicon films (step 301); On amorphous silicon membrane, form one deck silica or silicon nitride cover layer, and on cover layer etching induction port (step 302); On cover layer, form layer of metal and induce film, make this metal inducement film contact (step 303) with amorphous silicon membrane at the induction port place; Carry out first step annealing process, obtain polysilicon island (step 304) in the amorphous silicon membrane below induction port; Plated metal absorbed layer on the metal inducement film carries out the annealing process second time then, forms the amorphous silicon membrane (step 305) of the crystallization of uniform crystal particles distribution; Remove metal absorbed layer and cover layer (step 306).
Continuation is with reference to figure 3, and further with reference to figure 4 (a) and 4 (b), describe the flow process of method described in Fig. 3 in detail, wherein, Fig. 4 (a) illustrates the polysilicon " island " that the induction port place forms in first time annealing process of polysilicon membrane according to an embodiment of the invention, and Fig. 4 (b) illustrates the structure of the crystal film surface deposition metal absorbed layer after first time annealing process of polysilicon membrane according to an embodiment of the invention.
In step 301, on glass substrate 101 deposit thickness be low temperature silicon nitride, cryogenic oxidation silicon or the silicon oxynitride layer of 20-900 nanometer as barrier layer 102, the amorphous silicon membrane layer 103 of deposition 10-500 nanometer thickness.Wherein, deposition process adopts low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) and sputtering method.The amorphous silicon membrane layer thickness is generally the 10-500 nanometer, preferred 50-200 nanometer.Glass substrate 101 is the glass commonly used that healthy and free from worry 1737F, hawk 2000 etc. are usually used in preparing TFT, and thickness is the 0.3-1.5 millimeter.The silicon nitride of 200 nanometer thickness or the cryogenic oxidation silicon (LTO) of 100 nanometers also can be adopted in barrier layer 102.
In step 302, sedimentary cover 104 on amorphous silicon membrane layer 103, adopt a photoetching process to form the induction port of nucleus growth location then in cover layer 104.In one embodiment, induction port arranges continuously, evenly distribute, and the physical dimension of each induction port is identical, is adopt that photoetching method forms square, circle or strip aperture.Wherein, the width of induction port or radius are 2 microns to 20 microns, and the spacing distance between the hole is identical, are 30 microns to 300 microns.Preferably, the induction port width is 2 microns, 30 microns of spacing distances.Cover layer is cryogenic oxidation silicon or the silicon nitride or the mixed film of the two of PEVCD, LPCVD or sputtering sedimentation, and thickness is 50 nanometer to 500 nanometers, preferred 100 nanometers of thickness.
In step 303, on cover layer, form layer of metal and induce film, this metal inducement film is contacted with amorphous silicon at the induction port place.In one embodiment, adopt the nisiloy hybrid target, the sputter of argon oxygen forms metal inducement film 105, contacts at the amorphous silicon layer of induction port below it.In another embodiment, the metal inducement film is the nickel oxide silicon thin film of low nickel-content.In yet another embodiment, adopt methods such as sputter, evaporation, ion injection, solution immersion or spin coating to form metal inducement film 105.
In step 304, carry out first step annealing process, the place obtains polysilicon island at induction port.In one embodiment, nickel source in the metal inducement film and with the reaction of the amorphous silicon membrane of its boundary, silicon is oxidized and discharge nickel, nickel is diffused in the contiguous amorphous silicon of its periphery very soon, form the gathering of nickel, the induced nuclei that obtains dispersing, and grow into the low-density polysilicon " island " 201 that yardstick is 10-20 micron, circular domain.This annealing is carried out under nitrogen atmosphere, and annealing temperature 550-590 ℃, time 1-2 hour.Preferably, annealing temperature is 590 degree, 1 hour time.
In step 305, plated metal absorbed layer 106 on the metal inducement film.In one embodiment, PECVD, LPCVD deposit thickness are the phosphorosilicate glass (PSG) 106 of 100-900 nanometer on the metal inducement film, and preferred thickness is 700 nanometers.Fig. 4 (b) shows the polysilicon membrane through first step annealing back plated metal absorbed layer 106.
In step 306, carry out the annealing process second time, remove metal absorbed layer and cover layer then.In one embodiment, the second step annealing process is finished under nitrogen atmosphere, and annealing temperature 550-590 ℃, time 2-3 hour, wherein preferably, temperature was 590 degree, and the time is 2 hours.Induce metal to be absorbed gradually by the metal absorbed layer and the propelling of metal inducement polysilicon forward position, along with the propelling of crystallization process, the metallic nickel of induction port is absorbed in the absorbed layer, induces the peak head-on collision to form crystal boundary.Fig. 5 illustrates the distribution of induction port by the polysilicon island of equilateral triangle distribution.Wherein, triangle 401 is a polysilicon island, and 402 of circle is an induction port, and the back polysilicon island is grown up through annealing for the second time, domain radial extension formation head-on collision crystal boundary 501.In another embodiment, metal absorbed layer 106 and cover layer 104 use removals such as hydrofluoric acid or BOE, obtain the polysilicon membrane of complete crystallization.
Fig. 6 is the crystal structure of polysilicon membrane prepared in accordance with the present invention, and it is under the environment of 20 degree in TMAH solution, corrodes 3 minutes displaing micro picture.
In another embodiment of the present invention, a kind of transistor device that uses above-mentioned crystallization thin film and preparation method thereof is described.Wherein, obtain after the polysilicon membrane of preceding method realization, with its active island of processing TFT pattern, the gate oxide of the cryogenic oxidation silicon of deposition 20-200 nanometer thickness forms gate electrode.Wherein, gate oxide comprises silica, silicon nitride or silicon oxynitride.Afterwards, N, P type doped source are injected in the active layer by ion, and form between heavily doped source-drain area.Activate doped layer with short annealing modes such as laser, flashing lights then.Depositing insulating layer is opened contact hole, splash-proofing sputtering metal electrode, plated metal interconnection layer and the photoetching related electrode figure of grid, source, drain electrode.
Wherein, for N type TFT, adopt the phosphorus source, energy is 130KeV, and concentration is 4 * 10
15Square centimeter; For P type TFT, adopt the boron source, energy is 40KeV, concentration is 4 * 10
15Square centimeter was annealed 1-2 hour for 500-600 ℃ afterwards.
It should be noted that at last, above embodiment is only in order to describe technical scheme of the present invention rather than the present technique method is limited, the present invention can extend to other modification, variation, application and embodiment on using, and therefore thinks that all such modifications, variation, application, embodiment are in spirit of the present invention and teachings.
Claims (13)
1. the transistor device of a crystallization thin film comprises: polysilicon membrane, gate oxide, insulating barrier and metal interconnecting layer, and wherein, described polysilicon membrane comprises glass substrate, barrier layer and the polysilicon layer with continuous domain; Wherein, the thickness of described polysilicon layer is the 10-500 nanometer, and the uniform crystal particles in the described polysilicon layer distributes; Wherein, described polysilicon layer is the even polysilicon layer that the metal inducement film is contacted with described amorphous silicon membrane and form through the twice annealing crystallization by the cover layer photoetching induction port on amorphous silicon membrane, at described induction port.
2. the transistor device of claim 1, wherein, described gate oxide is the cryogenic oxidation silicon of the 20-200 nanometer thickness that deposits on described polysilicon membrane, described gate oxide comprises silica, silicon nitride or silicon oxynitride.
3. the transistor device of claim 1 also comprises the active layer that has between heavily doped source-drain area, wherein, for N type amorphous silicon film transistor (TFT), adopts the phosphorus source, and energy is 130KeV, and concentration is 4 * 10
15Square centimeter carries out ion and injects; For P type TFT, adopt the boron source, energy is 40KeV, concentration is 4 * 10
15Square centimeter, 500-600 ℃ of annealing was afterwards carried out ion in 1-2 hour and is injected.
4. the transistor device of claim 1, wherein, described glass substrate is the glass commonly used that is used to prepare TFT such as healthy and free from worry 1737F, hawk 2000, its thickness is the 0.3-1.5 millimeter.
5. the transistor device of claim 1, wherein, described barrier layer is for adopting silicon oxide layer or the silicon nitride layer such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) growth, and thickness is the 30-900 nanometer.
6. the transistor device of claim 5, wherein, described barrier layer is the silicon nitride of 200 nanometer thickness or the cryogenic oxidation silicon (LTO) of 100 nanometer thickness.
7. the transistor device of claim 5, wherein, described amorphous silicon thin layer adopts low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or sputtering method to be deposited on the described barrier layer, and wherein said amorphous silicon thickness of thin layer is the 10-500 nanometer.
8. the transistor device of claim 1, wherein, described cover layer photoetching induction port on amorphous silicon membrane is meant sedimentary cover on described amorphous silicon membrane layer, adopts photoetching process to form the induction port of nucleus growth location then in described cover layer.
9. the transistor device of claim 8, wherein, described induction port is arranged continuously, is evenly distributed, and each induction port is identical square, circle of physical dimension or strip aperture.
10. the transistor device of claim 9, wherein, the width of described induction port or radius are 2 microns to 20 microns, the spacing distance between the hole is identical, is 30 microns to 300 microns; Perhaps, described induction port width is 2 microns, 30 microns of spacing distances.
11. the transistor device of claim 8, wherein, at described induction port the metal inducement film is contacted with described amorphous silicon membrane and be meant that the described metal inducement film of the low nickel-content that methods such as adopting sputter, evaporation, ion injection, solution immersion or spin coating forms is in described induction port place and the reaction of described amorphous silicon membrane, the induced nuclei that obtains dispersing, and grow into the low-density polysilicon " island " that yardstick is 10-20 micron, circular domain.
12. the transistor device of claim 1, wherein, described process twice annealing crystallization comprises annealing process and annealing process for the first time for the second time, the described annealing first time is carried out under nitrogen atmosphere, annealing temperature 550-590 ℃, time 1-2 hour, the described second step annealing process was finished under nitrogen atmosphere, annealing temperature 550-590 ℃, time 2-3 hour.
13. the transistor device of claim 12, wherein, the described metal of inducing is absorbed gradually by the metal absorbed layer and the propelling of metal inducement polysilicon forward position, along with the propelling of crystallization process, the metallic nickel of induction port is absorbed in the absorbed layer, induces the peak head-on collision to form crystal boundary.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839821A (en) * | 2012-11-27 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839821A (en) * | 2012-11-27 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacturing method thereof |
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Open date: 20100915 |