CN101064246B - Metal-induced crystallization of amorphous silicon and metal removal techniques - Google Patents
Metal-induced crystallization of amorphous silicon and metal removal techniques Download PDFInfo
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- CN101064246B CN101064246B CN200610139876XA CN200610139876A CN101064246B CN 101064246 B CN101064246 B CN 101064246B CN 200610139876X A CN200610139876X A CN 200610139876XA CN 200610139876 A CN200610139876 A CN 200610139876A CN 101064246 B CN101064246 B CN 101064246B
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Abstract
The invention relates to a technology for producing a high quality and large area polycrystalline silicon thin film by amorphous silicon-metal-induced crystallization. Crystallization-inducing metal elements of controllable amount are introduced onto an initial amorphous silicon thin film. A first, low-temperature, heat-treatment induces nucleation of metal-induced crystallization (MIC), resulting in the formation of small polycrystalline silicon''islands''. A metal-gettering layer is formed on the resulting partially crystallized thin film. A second, low-temperature, heat-treatment completes the MIC process to form the desired polycrystalline silicon thin film. While the metal-gettering layer can be removed at random after crystallization heat-treatment.
Description
Technical field
What the present invention told about is to prepare high-quality by the amorphous silicon crystallization inducing metal, the technology of large-area polycrystalline silicon thin film.This Technology Need is introduced the induced crystallization metallic element of controlled amounts to initial amorphous silicon membrane; First Low Temperature Heat Treatment causes the crystallization inducing metal nucleation and forms very little polysilicon " island "; On this partially-crystallized thin-film material, form metal and absorb layer; The crystallization inducing metal process is through finishing in second low temperature heat treatment, and forms desired polysilicon membrane; Metal is absorbed layer and is removed after finishing the crystallization heat processing.
Background technology
TFT can be applied to active matrix liquid crystal demonstration, active matrix organic light-emitting diode demonstration, active matrix e-book and active matrix imageing sensor.Non-crystalline silicon tft because operating rate low, lack P type device and be difficult to be used for realizing peripheral circuit.This has promoted the generation of the polycrystalline silicon device that obtains by annealing furnace or LASER HEATING.Obtain the very high temperature (620-650 ℃) of arts demand of polysilicon and the polycrystalline silicon material poor performance that obtains by traditional low-pressure chemical vapor deposition.Can improve the performance of material by high annealing (more than 1000 ℃), but this method only is applicable to the quartz substrate of comparison costliness and can not be used for general glass substrate.
Another method that obtains polysilicon membrane is metal-induced crystallization (U.S. Pat 5275851, US5879977 and US2001018224).The material that obtains comprises big crystal grain, but remaining metal pollutant has reduced the final performance of TFT in the polysilicon.
Therefore introduced the method for absorbing metal residue after the metal-induced lateral crystallization process.(U.S. Pat 6465287, US6100562) the oxidized and remaining metallic element of the top section of metal-induced lateral crystallization polysilicon membrane is absorbed by the oxide layer at top through after the thermal oxidation technology.The polysilicon loss that oxidizing process causes is not wished to obtain, and is especially all the more so when polysilicon layer is relatively thinner.
In amorphous silicon layer doping rare gas (U.S. Pat 6821828, US6821828, US2004121530, US6743700, US2002164843, US2002134981) or doping group-v element (U.S. Pat 6825072, US2004058486, US6420246, US6664144, US5700333, US2003134459, diffusion phosphorus realizes that to selected polysilicon region the method that metal is absorbed is suggested US6461943) or from phosphosilicate glass.But absorption process like this occurs in after the metal-induced lateral crystallization process, has prolonged the time of whole technology.And, stay the high density of defects attitude at head-on collision crystal boundary place.
The proposition of the technology that absorption process and metal-induced lateral crystallization carry out simultaneously (U.S. Pat 2002192884) is to deposit one deck in advance to absorb layer before forming the precursor amorphous silicon.But the process of absorbing like this takes place too early, can influence the crystalline quality and the crystallization rate of polysilicon, and, absorb metal too near the polycrystalline silicon device active layer, the existence of absorbing layer can influence the final response of TFT.
The present invention proposes to remove the technology of the metal residue of controlled amounts in the polysilicon grain growth course.Introduce metal inducement polysilicon nucleus and form and growth, the nickel metal edges is absorbed the crystal limit and is grown into two steps of whole crystallization.Like this, effectively the nickel in the silicon fiml is transferred in the absorbed layer phosphorosilicate glass (PSG) on the one hand, on the other hand, along with the minimizing of nickel content in the silicon fiml, the nickel amount at head-on collision crystal boundary place can obviously reduce.After the heat treatment crystallization process is finished, absorb metallic nickel in the phosphorosilicate glass (PSG) and can in removing the PSG process, come along and remove, therefore improve the polysilicon membrane quality greatly and reduced the quantity of metal residues pollutant.
Summary of the invention
The present invention is for prepare the method for high-quality polycrystalline silicon film material, and has former layer with this kind polycrystalline silicon film material as preparation high-quality multi-crystal TFT.Polysilicon membrane adopts the method for nickel metal-induced crystallization, and phosphorosilicate glass (PSG) absorption method is adopted in the absorption of remaining nickel.Technological core of the present invention is that crystallization and absorption process have been carried out optimized combination.The first step is introduced the metallic nickel of trace on amorphous silicon membrane surface, under 420-620 ℃, 1-2 hour, induce nucleation and be grown to serve as with the form of MILC discrete, the polysilicon spot of diameter 10-20 micron.Second step, at above-mentioned film surface, the PSG film of deposition 300-700 nanometer, and under the 420-620 temperature, annealed 2-3 hour, finish the crystallization process of whole polysilicon membrane.The partially-crystallized film of the first step forms, and has reduced the PSG and the crystallization that are adopted in the existing patent and has begun the influence to crystalline quality and crystallization rate that the nickel absorption is caused simultaneously; In second step, to remaining amorphous silicon region, the nickel limit is absorbed, and crystallization is gone to promote in the limit, the nickel content in the last head-on collision crystal boundary, and the content in the head-on collision crystal boundary of being mentioned in the existing patent that does not have whole crystallization under the nickel absorption situation is low.The crystal boundary of a low nickel-content and the crystal boundary of high nickel content are carried out the nickel absorption, and the former defect state is low than the latter.Therefore, adopt the combination property of polycrystalline silicon material of our invention preparation, be higher than the existing prepared polycrystalline silicon film material of patented technology.
A kind of method of preparation polysilicon membrane of the present invention, its step comprises at least
1: on the glass substrate of grown silicon nitride silica barrier layer, the deposited amorphous silicon layer.
2: introduce trace meter nickel at the amorphous silicon membrane film, and carry out first step annealing process, form the polysilicon amorphous silicon mixed film of discrete partial crystallization.
3: at mixed film surface deposition PSG layer, and carry out second step annealing, form polysilicon membrane completely.
4: remove PSG layer and absorption metallic nickel therein.
Described glass substrate is but is not limited to healthy and free from worry 1737F, hawk 2000 etc.
Described silicon nitride silica barrier layer adopts but is not limited to PECVD method deposition, and thickness is the 30-900 nanometer.
Described amorphous silicon refers to the predecessor of crystallization silicon, for but be not limited to PECVD, LPCVD method deposition, thickness is the 10-500 nanometer.
Described amorphous silicon membrane film is introduced the nickel of trace, adopt but be not limited to that sputter, evaporation, solution are soaked, solution spin coating and ion injection etc., its amount should be the 0.1%-0.01% of silicon in the amorphous silicon, is the nickel amount that guarantees to form the dish type polysilicon.
Described first step annealing is carried out under nitrogen atmosphere, and temperature 420-620 ℃, the time is 1-2 hour.
Described partially-crystallized polysilicon directly is the 10-20 micron for discrete dish type polysilicon domain.
Described mixed film surface deposition PSG layer is to adopt but be not limited to PECVD, LPCVD to grow, and thickness is the 100-900 nanometer.
Described second step annealing carries out under nitrogen atmosphere, and temperature 420-620 ℃, the time is 2-3 hour.
The process of described removal PSG adopts the corrosive liquid (BOE, hydrofluoric acid etc.) of LTO to remove the PSG layer, removes the metallic nickel that adsorbs among the PSG simultaneously.
Description of drawings
Fig. 1. covered the schematic cross-section of the amorphous silicon membrane 103 that deposits on the substrate 101 of insulating barrier 102.
Fig. 2. form the sectional view of metal or containing metal material inducing layer 201 at the exposed region on amorphous silicon membrane 103 surfaces
Fig. 3. form the process sectional view of discontinuous polysilicon " island " 302 in first heat treatment process.
Fig. 4. the distribution schematic diagram of polysilicon " island "
Fig. 5. the sectional view of film 301, the 302 surface deposition metal absorbed layers 501 after partially-crystallized
Fig. 6. induce in second heat treatment process metal be absorbed by the absorption layer and amorphous silicon be the sectional view of polysilicon by crystallization
Fig. 7. through second heat treatment process with remove the sectional view that high-test metal that the metal absorbed layer obtains is later on induced polysilicon membrane
Fig. 8. preparation thin-film transistor technical process intermediate ion injects and forms the sectional view of active layer on the high-quality polycrystalline silicon material
Fig. 9. on the high-quality polycrystalline silicon material, make the sectional view of film transistor device
Embodiment
Details are as follows with reference to accompanying drawing in the present invention:
Shown in Figure 1 is the schematic cross-section that has covered the amorphous silicon membrane 103 that deposits on the substrate 101 on barrier layer 102.Glass substrate 101 is the glass commonly used that healthy and free from worry 1737F, hawk 2000 etc. are used to prepare TFT, and thickness is the 0.3-1.5 millimeter.Barrier layer 102 is for adopting low temperature silicon nitride, cryogenic oxidation silicon or the silicon oxynitride layer of the growth of PECVD or LPCVD method, and thickness is the 30-900 nanometer.This layer in the crystallization equitemperature process, stops that the metal ion in the glass spreads in the back in silicon fiml.Amorphous silicon membrane 103 deposits for adopting PECVD or LPCVD method, and thickness is the 10-500 nanometer.This layer is the predecessor of preparation layer polysilicon film.
Shown in Figure 2 is at the nickel of amorphous silicon membrane 103 surface deposition trace or the schematic cross-section of nickeliferous material 201.The nickel of this layer trace or nickeliferous material 201 are the method acquisitions by sputter, evaporation, ion injection, solution immersion or spin coating.
Shown in Figure 3 is above-mentioned sample, and through first step annealing process, this process is carried out under nitrogen atmosphere usually, and temperature is 550-590 ℃, time 1-2 hour.In this annealing process, in amorphous silicon membrane, form discrete induced nuclei, and grow into the polysilicon island 302 that yardstick is the 10-20 micron.Other parts are still non-crystallized amorphous silicon region 301.
Shown in Figure 4 is through after the first step annealing process, the vertical view of polysilicon amorphous silicon mixed film.Polysilicon island 302 wherein is the circular domain that distributes immediately.Other parts are still non-crystallized amorphous silicon membrane zone.
After the first step annealing process, remove the natural oxidizing layer of sample surfaces and clean surface with the hydrofluoric acid of dilution.Afterwards step as shown in Figure 5, on the surface of polysilicon 301 amorphous silicons 301 mixed films, deposit thickness is the PSG501 of 100-900 nanometer.
Shown in Figure 6 is that above-mentioned sample is in second annealing process, (this process is carried out under nitrogen, temperature is 420-620 ℃, and the time is 2-3 hour) induce metallic nickel to be absorbed gradually by PSG 501 and metal inducement polysilicon forward position propelling simultaneously, amorphous silicon changes the schematic cross-section of polysilicon into.Shown in Fig. 6 (a) is at the second step annealing initial state, inducing in the peak of the forward position of metal-induced lateral crystallization polysilicon, there is more metallic nickel 602, propelling along with crystallization process, polysilicon, amorphous silicon, particularly induce the metallic nickel in the peak constantly to be absorbed in the PSG layer, form the nickel 601 that is adsorbed among the PSG.Shown in Fig. 6 (b) is above-mentioned annealing process when proceeding to coda, the nickel in the catalysis peak seldom, the crystal grain on both sides will clash together.Nickel content is less in such head-on collision crystal grain, and after nickel was absorbed, the defect state density at this place was lower.
After the second step annealing process, the PSG layer is got rid of with hydrofluoric acid or BOE etc.The metal inducement polysilicon membrane 701 that obtains at last as shown in Figure 7.
Shown in Figure 8 is the formation schematic diagram of multi-crystal TFT gate insulation layer 802, and it is but is not limited to silica, silicon nitride or silicon oxynitride.Form gate electrode 803 on gate insulation layer, afterwards, N, P type doped source 804 ions are injected in the active layer, and form between heavily doped source-drain area 801.Adopt short annealings such as laser, flashing light or boiler tube thermal annealing mode to activate doped layer then.
What Fig. 9 described is the schematic cross-section of thin-film transistor.Depositing insulating layer 901 is opened the contact hole of grid, source, drain electrode, and plated metal interconnection layer 902 also forms the related electrode figure.
The specific embodiment preparation method is:
1: the healthy and free from worry 1737F after 1.1 millimeters is on glass 101, and PECVD deposits 200 nano-silicon nitrides, 100 nanometer LTO do barrier layer 102.550 ℃ of depositions of LPCVD, 50 nano amorphous silicon layers 103.
2: adopt the nisiloy hybrid target, the sputter of argon oxygen atmosphere realizes that micro-nickel 201 adheres in amorphous silicon surfaces.
3: above-mentioned sample is annealed under nitrogen atmosphere, and temperature is 590 ℃, 1 hour time.Become the hybrid films of amorphous silicon film 301 polysilicon films 302.
4: the hydrofluoric acid with dilution removes the natural oxidizing layer of sample surfaces and clean surface.Afterwards, the LPCVD deposit thickness is the PSG 501 of 700 nanometers.
5: above-mentioned sample carries out second annealing process, nitrogen atmosphere, and temperature is 590 ℃, the time is 2 hours.
6: after the second step annealing process, PSG gets rid of with hydrofluoric acid or BOE etc. for 501 layers, obtains the polysilicon membrane 701 of complete crystallization.
7:, deposit 100 nanometer LTO gate oxides with the active island of above-mentioned polysilicon membrane processing TFT.
8: form gate electrode 803, and carry out ion implantation doping 804.To N type TFT, adopt the phosphorus source, energy is 130KeV, concentration is 4 * 10
15/ square centimeter to P type TFT, adopts the boron source, and energy is 40KeV, and concentration is 4 * 10
15/ square centimeter.Annealed 1 hour the activation doped region afterwards for 550 ℃.
9:PECVD deposits the electrode dielectric layer 901 of 500 nanometers, and opening contact hole forms metal electrode 902.
Claims (12)
1. prepare the technology of polysilicon membrane, comprise following steps:
The preparation amorphous silicon membrane;
At above-mentioned amorphous silicon membrane surface introducing trace meter nickel or nickeliferous material is inducing layer;
To carrying out first step annealing process, to obtain discontinuous polysilicon " island " by above-mentioned sample;
Plated metal absorbed layer on above-mentioned partially-crystallized film;
Finish the second step annealing process of metal-induced crystallization;
Remove the metal absorbed layer.
2. the technology of claim 1, wherein amorphous silicon membrane adopts but is not limited to low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) and sputtering method and deposits.
3. the technology of claim 1, wherein amorphous silicon membrane thickness is the 10-1000 nanometer.
4. the technology of claim 1, wherein said metal is a nickel, the method for the introducing nickel of employing comprises that sputter, evaporation, ion inject, solution soaks or spin coating.
5. the atom number of silicon is than being 0.01%-0.1% in the technology of claim 1, the nickel in wherein said metal or the containing metal material and covering amorphous silicon.
6. the technology of claim 1, wherein said first step annealing process is finished under nitrogen atmosphere, and annealing temperature 550-590 ℃, time 1-2 hour.
7. the technology of claim 1, wherein said discontinuous polysilicon " island " is the metal-induced lateral crystallization polysilicon.
8. the technology of claim 1, wherein said metal absorbed layer material is phosphorosilicate glass PSG, the preparation method of the phosphorosilicate glass of employing comprises PECVD and LPCVD.
9. the technology of claim 1, the thickness of wherein said metal absorbed layer is the 100-900 nanometer.
10. the technology of claim 1, wherein said second annealing process finished under nitrogen atmosphere, and annealing temperature 550-590 ℃, time 2-3 hour.
11. the technology of claim 8, wherein said removal metal absorbed layer process erodes phosphorosilicate glass for adopting dilute hydrofluoric acid, BOE etc., and the metallic nickel that is adsorbed on wherein is removed simultaneously.
12. application rights requires the polysilicon membrane of the technology preparation described in 1 to 11 to make thin-film transistor and related circuit, active matrix and display base plate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/413,073 US8088676B2 (en) | 2005-04-28 | 2006-04-27 | Metal-induced crystallization of amorphous silicon, polycrystalline silicon thin films produced thereby and thin film transistors produced therefrom |
| US11/413073 | 2006-04-27 |
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| CN101064246A CN101064246A (en) | 2007-10-31 |
| CN101064246B true CN101064246B (en) | 2011-05-18 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101740359B (en) * | 2009-12-08 | 2011-11-23 | 四川虹视显示技术有限公司 | Nickel stripping method in method for manufacturing low-temperature polysilicon |
| CN101834122B (en) * | 2010-02-09 | 2012-07-04 | 广东中显科技有限公司 | Manufacturing method of polycrystalline silicon film material |
| CN101819999A (en) * | 2010-05-17 | 2010-09-01 | 广东中显科技有限公司 | Multilayer film structure for transverse induced crystallization of low-temperature poly-silicon film |
| CN101859590A (en) * | 2010-06-22 | 2010-10-13 | 广东中显科技有限公司 | USB flash disk with display screen and high security |
| CN101866680A (en) * | 2010-06-22 | 2010-10-20 | 广东中显科技有限公司 | U disk having display screen and solar cell |
| CN101859591A (en) * | 2010-06-22 | 2010-10-13 | 广东中显科技有限公司 | USB flash disk with display screen and capable of wireless transmission |
| CN101859593A (en) * | 2010-06-22 | 2010-10-13 | 广东中显科技有限公司 | USB flash disk with display screen |
| CN101859592A (en) * | 2010-06-22 | 2010-10-13 | 广东中显科技有限公司 | USB flash disk with display screen and for charging external equipment |
| CN102243991B (en) * | 2011-05-06 | 2013-04-03 | 上海大学 | Method for inducing amorphous silicon film with tin to be crystallized into polycrystalline silicon film |
| CN102839347A (en) * | 2011-06-24 | 2012-12-26 | 北京石油化工学院 | Preparation method for metal aluminum induced polycrystalline cadmium zinc telluride film |
| CN104851890A (en) * | 2015-04-16 | 2015-08-19 | 武汉华星光电技术有限公司 | Method for forming polycrystalline silicon layer, LTPS array substrate, and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337259B1 (en) * | 1999-05-27 | 2002-01-08 | Sharp Kabushiki Kaisha | Method for fabricating semiconductor device with high quality crystalline silicon film |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337259B1 (en) * | 1999-05-27 | 2002-01-08 | Sharp Kabushiki Kaisha | Method for fabricating semiconductor device with high quality crystalline silicon film |
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| JP特开2003－100633A 2003.04.04 |
| US 6337259 B1,全文. |
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