CN101771010B - 集成电路结构 - Google Patents

集成电路结构 Download PDF

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Publication number
CN101771010B
CN101771010B CN200910203613.4A CN200910203613A CN101771010B CN 101771010 B CN101771010 B CN 101771010B CN 200910203613 A CN200910203613 A CN 200910203613A CN 101771010 B CN101771010 B CN 101771010B
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rdl
integrated circuit
circuit structure
tsv
silicide layer
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CN101771010A (zh
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邱文智
吴文进
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路结构包括具有前面和背面的半导体衬底。穿透硅通孔(TSV)穿透该半导体衬底。该TSV具有延伸到半导体衬底背面的后端。再分配线(RDL)在半导体衬底背面上并且与TSV的后端连接。硅化物层在该RDL的上并且与RDL接触。

Description

集成电路结构
技术领域
本发明通常涉及集成电路结构，更具体地涉及穿透硅通孔，再具体地涉及与穿透硅通孔连接的背面金属的形成。 
背景技术
自从发明了集成电路，由于各种电子部件(即晶体管、二极管、电阻、电容等)的集成密度的持续提高，半导体工业已经经历了连续快速增长。在很大程度上，集成密度的这种提高来自于最小特征尺寸的不断减小，从而允许更多的部件集成到给定的芯片区域内。 
因为被集成的部件占用的体积基本上在半导体晶片的表面上，因此这种集成度提高本质上基本是二维(2D)的。虽然在光刻上的显著提高导致了2D集成电路构成的显著改进，但是对能在二维中实现的密度存在物理限制。其中一个限制是制成这些部件需要的最小尺寸。而且，当在一个芯片中放置更多的器件时，需要更复杂的设计。 
随着器件数量的增加，另外的限制来自器件之间互连的数目和长度的显著增加。当互连的数目和长度增加时，电路的RC延迟和功耗都会增加。 
在用来解决上述限制的成果中，通常使用三维集成电路(3D IC)和叠置管芯。由此穿透硅通孔(TSV)用于3D IC和叠置管芯中用以连接管芯。在这种情况下，TSV常用来将管芯上的集成电路连接到该管芯的背面。另外，TSV也用来穿过管芯的背面提供用于将该集成电路接地的短接地路径，其可以被接地金属膜覆盖。 
图1示出了形成在芯片104中的传统的TSV 102。TSV 102位于硅衬底106中。穿过金属化层中的互连(金属引线和通孔，未示出)，TSV 102被电连接到接合焊垫110和接合焊垫110上的金属柱108，其中接合焊垫110在芯片104的前表面上。以铜柱的形式将TSV 102穿过衬底106的后表面并将其露出。当芯 片104与另一个芯片接合时，将TSV 102接合至另一个芯片上的接合焊垫上，在其之间具有焊料或不具有焊料。这种方案有缺点。由于TSV接合需要TSV间相对比较大的间距，所以TSV的位置是受到限制的，并且TSV之间的距离需要足够大以允许对于例如焊球的空间。另外，由于相邻的焊球可能会彼此接触，所以可能存在接合处失效。由此需要新的背面结构。 
发明内容
根据本发明的一个实施例，集成电路结构包括具有前面和背面的半导体衬底。穿透该半导体衬底的穿透硅通孔(TSV)。该TSV具有延伸到半导体衬底背面的后端。在半导体衬底背面上并且连接到TSV的后端的再分配线(RDL)。在该RDL的上面并且与RDL连接的硅化物层。 
根据本发明的另一个实施例，集成电路结构包括具有前面和后面的半导体衬底。TSV穿透该半导体衬底，并且具有延伸超出该半导体衬底背面的后端。RDL在半导体衬底的背面上并连接到TSV的后端，其中RDL包括铜。硅化物层在RDL上并与RDL邻接，其中硅化物层包括硅化铜。钝化层在RDL上并通过该钝化层和硅化物层中的开口邻接RDL，其中RDL的一部分通过开口暴露。金属层位于开口中并与RDL连接。 
本发明的有利特点包括：由于降低了RDL的氧化，提高了接合能力，并提高了背面结构的可靠性。 
附图说明
为了更全面地理解本发明及其优点，现在结合附图参考下面的描述，其中： 
图1示出了包括穿透硅通孔(TSV)的传统集成电路结构，其中TSV穿过衬底的背面突出，并以铜柱的形式被接合到另一个芯片上的接合焊垫。 
图2至12C是本发明的实施例制造的中间阶段的剖面图。 
图13示出了两个叠置管芯的剖面图。 
具体实施方式
下面详细地论述本发明实施例的制作和使用。然而，应该意识到，本发明 的实施例提供了许多可应用的发明思想，其可在广泛的具体环境中实施。论述的这些具体实施例仅是说明制作和应用本发明的具体方式，并不限制本发明的范围。 
提供了新颖的连接穿透硅通孔(TSV)的背面连接结构及其形成方法。说明了制造本发明的实施例的中间阶段。论述了不同的实施例。在所有本发明的各种图和说明性实施例中，相同的附图标记用来指示相同的元件。 
参考图2，提供了芯片2，其包括衬底4和其中的有源电路6。衬底4可以是半导体衬底，例如体硅衬底，当然其可以是包括III族、IV族和/或V族元素的其它半导体材料。有源电路6中的有源器件，例如晶体管，可以形成在衬底4的前表面上(图2中面朝上的表面)。层间电介质(ILD)9形成在衬底4和有源电路6的上面。接触孔塞8形成在ILD 9中并连接到有源电路6。 
在形成ILD 9和接触孔塞8之后，在衬底4中形成TSV 20，并从ILD 9的顶部表面延伸至衬底4中。在实施例中，如图2所示，TSV 20利用先通孔方法形成，并且在形成互连结构12(在图2中没有示出，请参考图3)之前形成。因而，TSV 20仅向ILD 9延伸，没有延伸到随后形成的互连结构12中的金属间电介质(IMD)中。在可选实施例中，TSV 20可以利用后通孔方法形成，并且在形成互连结构12之后形成。从而，TSV 20将穿过衬底4和互连结构12。在TSV 20的侧壁上形成隔离层22，并使TSV 20与衬底4电绝缘。隔离层22可以由通常使用的电介质材料形成，例如氮化硅、硅氧化物(例如，四乙基原硅酸盐(TEOS)氧化物)和/或类似材料。 
参考图3，在衬底4上形成互连结构12并将其连接到有源器件，互连结构12包括形成在其中的金属线和通孔(未示出)。金属线和通孔可以由铜或铜合金形成，并且可以利用众所周知的镶嵌工艺形成。互连结构12通常可以包括已知的IMD。接合焊垫14形成在芯片2的前面的前侧上(图2中面朝上的一侧)，并且可以或不可以向外突出。接合焊垫14还可以通过互连结构12中的金属线和通孔连接到有源器件。 
参考图4，将带23(或玻璃晶片)粘附到芯片2的前侧(或所定位的芯片2的各个晶片上)，并研磨和抛光芯片2以移除多余的部分，直到通过衬底4的背面暴露TSV 20，如图5所示。还可以蚀刻衬底4的背面以移除在研磨和抛光工 艺中损坏的层。在图6中，形成覆盖衬底4背面的背面钝化层24。背面钝化层24可以由通常使用的电介质材料形成，例如氮化硅、硅氧化物(例如，四乙基原硅酸盐(TEOS)氧化物)、氮氧化硅、碳化硅、氮氧化碳化硅(siliconcarbo-oxynitride)等。在示范性实施例中，形成背面钝化层24包括：覆盖形成背面钝化层24，进行轻度化学机械抛光以移除直接覆盖在TSV 20上的那部分背面钝化层24，并可能地进行蚀刻以减小背面钝化层24的厚度。在可选实施例中，通过蚀刻形成背面钝化层24中的开口，通过该开口暴露TSV 20。 
参考图7，在背面钝化层24和TSV 20上覆盖形成薄的籽晶层26，也称为下底凸块金属化(UBM)。UBM 26可使用的材料包括铜或铜合金。然而，还可以包括其它金属，例如钛、银、金、铝以及它们的组合。在实施例中，UBM 26利用溅射形成。在其它实施例中，可以使用物理汽相沉积(PVD)或电镀。 
图7还说明了掩模46的形成。在实施例中，掩模46是干膜，其可以包括有机材料，例如Ajinomoto Buildup film(ABF)、Prepreg等。可选地，掩模46由光致抗蚀剂形成。接着，对掩模46进行构形以在掩模46中形成开口50，通过开口50暴露TSV 20和UBM 26的对应上覆盖部分。 
在图8中，选择性地用金属性材料填充开口50，在开口50中形成再分配线(RDL)52。在实施例中，填充材料包括铜或铜合金，但还可以使用其它金属，例如铝、银、金以及它们的组合。形成方法优选包括电化学电镀、无电电镀或其它通常使用的沉积方法，例如溅射、印刷和化学汽相沉积(CVD)方法。然后移除掩模46。最终，暴露掩模46下面的部分UBM 26。 
再如图8所示，通过闪光蚀刻移除UBM 26的暴露部分。剩余的RDL 52可以包括RDL带(还称为再分配迹线)，其包括直接在TSV 20上和/或连接到TSV20的部分以及任意的连接RDL带的RDL焊垫，其中RDL焊垫同TSV 20横向隔离开并且具有比RDL带更大的宽度。该RDL焊垫可以不直接在TSV 20上。在图8和随后的图中，没有示出UBM 26的剩余部分，由于其一般由与RDL 52相同的材料形成，由此表现为其被合并至RDL 52。作为闪光蚀刻的结果，也移除了一薄层的RDL 52。然而，与其全部厚度相比，RDL 52的移除部分可以忽略不计。 
图9示出了形成覆盖RDL 52的硅化物层54。在实施例中，硅化物层54是通 过在充满含硅前体例如硅烷(SiH4)的环境中处理如图8中所示的结构形成的，但还可以使用其它类似的前导气体。该处理可以是在大约100℃和大约400℃之间的温度下进行的等离子体处理或热处理。作为处理的结果，至少硅化了RDL52的暴露的表面，形成硅化物层54。硅化物层54的厚度可以在几埃和大约100 
Figure G2009102036134D00051
之间，但其还可以更厚或更薄。当由铜或铜合金形成RDL 52时，硅化物层54包括硅化铜。硅化物层54包括直接在RDL 52上面的部分和RDL 52所有侧壁上的部分。 
接下来，如图10所示，覆盖形成钝化层56。钝化层56可以由氮化物、氧化物、聚酰亚胺和/或类似材料形成。由于形成钝化层56可能需要含氧的前导气体，因此在形成钝化层56之前通过形成硅化物层54以覆盖RDL 52，所以避免了由形成钝化层56造成的对RDL 52的氧化和损害的可能。有利地是，未氧化的RDL具有与随后采用的形成在RDL 52上的材料更好的接合，例如金属层。 
在图11A中，对钝化层56进行构形以形成开口58。通过开口58暴露一部分RDL 52，例如RDL焊垫部分。开口58可以直接在RDL52中的RDL焊垫的中心部分上。在实施例中，开口58穿透硅化物层54，以便暴露下面的RDL 52。在可选实施例中，在形成开口58期间没有移除硅化物层54的暴露部分，如图11B所示，并且其将与随后形成的金属层物理接触。 
接下来，如图12A所示，形成金属层60，其延伸到开口58中。金属层60的形成方法包括ECP、无电电镀等。在实施例中，金属层60包括直接在RDL 52上且连接RDL 52的镍层62。优选地，可以在镍层62上形成其它层，例如金层66，或钯层(未示出)上的金层66。镍层62的厚度大于钝化层56的厚度，以便镍层62的顶部表面高于钝化层56的顶部表面。 
在可选实施例中，如图12B所示，除了RDL 52的上表面之外，在形成开口58的步骤期间，还暴露了RDL 52的一个或多个侧壁(参考图11A和11B)。因而，金属层60，除了连接到上表面之外，还可以连接到RDL 52的侧壁(如果蚀刻了硅化物层54)。在可选实施例中，如虚线68所指示的，没有移除通过开口58暴露的那部分硅化物层54，因此金属层60还接触硅化物层64的侧壁部分。 
图12C说明了可以在芯片2的背面上形成多层RDL，例如，除了RDL 52之外，还形成了RDL 70，其中RDL 70也可以由铜或其它金属性材料形成。如果 需要进一步布线，则可以形成更多的RDL层。根据工艺的需要，例如，随后形成的部件是否需要含氧的前导气体，芯片2背面上的RDL 54和70中的至少一个且尽可能多的可以包括形成在其上的硅化物(54和/或72)。 
图13说明了芯片2到芯片100的接合。在示范性实施例中，焊料74用来将芯片2的金属层60连接到铜柱76，铜柱76可以形成在芯片100的接合焊垫78上。需要注意的是，包括厚镍层62的金属层60的形成，具有增加芯片2和芯片100之间的间隔(standoff)功能。 
本发明的实施例具有几个有利特性。通过在形成钝化层之前在RDL上形成硅化物层，基本上消除了RDL的氧化。从而，增强了接合(焊接)能力，并提高了最终叠置管芯结构的可靠性。 
虽然已经详细描述了本发明和它的优点，但是应该理解，在没有偏离由附属权利要求定义的本发明的精神和范围的前提下，这里可以进行各种变化、置换和改造。而且，本申请的范围并不意指限制于本说明书中描述的工艺、机械、制造、以及物质的组成、方式、方法和步骤的具体实施例。作为本领域的一个普通技术人员，由本发明的公开，将很容易意识到，目前存在的或后来开发的，与这里描述的相应实施例进行基本相同的功能或实现基本相同的结果的工艺、机械、制造、物质的组成、方式、方法或步骤都可以根据本发明来利用。从而，附属权利要求指的是这些工艺、机械、制造、物质的组成、方式、方法或步骤包括在其范围内。另外，每个权利要求组成单独的实施例，并且不同权利要求和实施例的组合也在本发明的范围内。 

Claims (15)

1.一种集成电路结构，包括：
包括前面和背面的半导体衬底；
穿透所述半导体衬底的穿透硅通孔(TSV)，所述TSV包括延伸到所述半导体衬底背面的后端；
再分配线(RDL)，在所述半导体衬底背面上并且与所述TSV的后端连接；和
在所述RDL上的硅化物层。
2.根据权利要求1的集成电路结构，其中所述RDL包括铜，并且其中所述硅化物层包括硅化铜。
3.根据权利要求1的集成电路结构，还包括：
在所述RDL上的钝化层；和
在所述钝化层中且直接在所述RDL的一部分上的开口。
4.根据权利要求3的集成电路结构，其中所述开口穿过所述硅化物层，并且其中所述RDL的所述一部分通过所述开口暴露。
5.根据权利要求3的集成电路结构，其中通过硅化物层将所述开口与所述RDL隔离开。
6.根据权利要求3的集成电路结构，还包括所述开口中的镍层和在所述镍层上的金层。
7.根据权利要求3的集成电路结构，其中所述硅化物层分别与所述RDL和所述钝化层物理接触。
8.根据权利要求3的集成电路结构，其中所述RDL的侧壁直接位于所述开口的下面。
9.一种集成电路结构，包括：
包括前面和背面的半导体衬底；
穿透所述半导体衬底的穿透硅通孔(TSV)，所述TSV包括延伸超出所述半导体衬底背面的后端；
再分配线(RDL)，在所述半导体衬底背面上并且与所述TSV的后端相连，其中所述RDL包含铜；
在所述RDL上并与之相邻的硅化物层，其中所述硅化物层包含硅化铜；
在所述RDL上并与之相邻的钝化层；
在所述钝化层和所述硅化物层中的开口，其中所述RDL的一部分通过所述开口暴露；和
在所述开口中并与所述RDL接触的金属层。
10.根据权利要求3或9的集成电路结构，其中所述钝化层包括含氧电介质材料。
11.根据权利要求9的集成电路结构，其中所述金属层与所述RDL物理接触；或者其中所述金属层与所述硅化物层物理接触，并通过所述硅化物层与RDL分隔开。
12.根据权利要求9的集成电路结构，其中所述金属层包括镍层和在所述镍层上的金层。
13.根据权利要求9的集成电路结构，其中所述金属层的整体直接在所述RDL上；或者其中所述金属层包括直接在所述RDL上面的第一部分和在所述RDL的侧壁上的第二部分。
14.根据权利要求1或9的集成电路结构，其中所述硅化物层包括与所述RDL的上表面邻接的水平部分和在RDL侧壁上的侧壁部分。
15.根据权利要求14的集成电路结构，其中RDL的所有侧壁都与硅化物层接触。
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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8736050B2 (en) * 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US20100171197A1 (en) 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US9530726B2 (en) * 2010-06-28 2016-12-27 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US8586472B2 (en) 2010-07-14 2013-11-19 Infineon Technologies Ag Conductive lines and pads and method of manufacturing thereof
US8823166B2 (en) 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
KR101697573B1 (ko) * 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
KR20120090417A (ko) * 2011-02-08 2012-08-17 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8853857B2 (en) 2011-05-05 2014-10-07 International Business Machines Corporation 3-D integration using multi stage vias
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
CN102856303B (zh) * 2011-06-27 2015-07-22 成都锐华光电技术有限责任公司 一种半导体芯片
FR2978296A1 (fr) 2011-07-20 2013-01-25 St Microelectronics Crolles 2 Puce electronique comportant des piliers de connexion, et procede de fabrication
KR101906860B1 (ko) 2011-11-24 2018-10-12 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
CN102496570A (zh) * 2011-12-13 2012-06-13 日月光半导体制造股份有限公司 半导体元件及其制造方法
CN102496579B (zh) * 2011-12-19 2014-04-02 中国科学院微电子研究所 一种在转接板上实现电绝缘的方法
US9257392B2 (en) * 2012-04-11 2016-02-09 Mediatek Inc. Semiconductor package with through silicon via interconnect
KR102018885B1 (ko) 2012-12-20 2019-09-05 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US8912091B2 (en) 2013-01-10 2014-12-16 International Business Machines Corporation Backside metal ground plane with improved metal adhesion and design structures
US9059111B2 (en) 2013-04-11 2015-06-16 International Business Machines Corporation Reliable back-side-metal structure
KR20160052463A (ko) 2013-06-28 2016-05-12 인텔 코포레이션 미세 피치 재분배 라인들의 보존
US9754909B2 (en) * 2015-05-26 2017-09-05 Monolithic Power Systems, Inc. Copper structures with intermetallic coating for integrated circuit chips
US9881884B2 (en) * 2015-08-14 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US10147682B2 (en) * 2015-11-30 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for stacked logic performance improvement
US9805977B1 (en) 2016-06-08 2017-10-31 Globalfoundries Inc. Integrated circuit structure having through-silicon via and method of forming same
US9935079B1 (en) 2016-12-08 2018-04-03 Nxp Usa, Inc. Laser sintered interconnections between die
US10418311B2 (en) * 2017-03-28 2019-09-17 Micron Technology, Inc. Method of forming vias using silicon on insulator substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1218291A (zh) * 1997-11-21 1999-06-02 三菱电机株式会社 半导体器件
CN1638091A (zh) * 2004-01-08 2005-07-13 台湾积体电路制造股份有限公司 预防双重金属镶嵌结构的金属漏电的氮化物阻障层

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239746A (en) * 1991-06-07 1993-08-31 Norton Company Method of fabricating electronic circuits
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
KR950007358B1 (ko) * 1992-07-01 1995-07-10 현대전자산업주식회사 박막트랜지스터의 제조방법
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6675469B1 (en) * 1999-08-11 2004-01-13 Tessera, Inc. Vapor phase connection techniques
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
WO2003063242A1 (en) 2002-01-16 2003-07-31 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
KR100497111B1 (ko) * 2003-03-25 2005-06-28 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US6897125B2 (en) 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
US20050186339A1 (en) * 2004-02-20 2005-08-25 Applied Materials, Inc., A Delaware Corporation Methods and apparatuses promoting adhesion of dielectric barrier film to copper
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
JP4758712B2 (ja) * 2005-08-29 2011-08-31 新光電気工業株式会社 半導体装置の製造方法
KR100800161B1 (ko) 2006-09-30 2008-02-01 주식회사 하이닉스반도체 관통 실리콘 비아 형성방법
US7800238B2 (en) * 2008-06-27 2010-09-21 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods
US7936052B2 (en) * 2008-09-30 2011-05-03 Infineon Technologies Ag On-chip RF shields with backside redistribution lines

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1218291A (zh) * 1997-11-21 1999-06-02 三菱电机株式会社 半导体器件
CN1638091A (zh) * 2004-01-08 2005-07-13 台湾积体电路制造股份有限公司 预防双重金属镶嵌结构的金属漏电的氮化物阻障层

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